pme\-active\-high (full) in projects: freebsd

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Searched +full:pme +full:- +full:active +full:- +full:high (Results 1 – 23 of 23) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/net/
H A D	smsc911x.txt	1 * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller 4 - compatible : Should be "smsc,lan<model>", "smsc,lan9115" 5 - reg : Address and length of the io space for SMSC LAN 6 - interrupts : one or two interrupt specifiers 7 - The first interrupt is the SMSC LAN interrupt line 8 - The second interrupt (if present) is the PME (power 11 - phy-mode : See ethernet.txt file in the same directory 14 - reg-shift : Specify the quantity to shift the register offsets by 15 - reg-io-width : Specify the size (in bytes) of the IO accesses that 18 - smsc,irq-active-high : Indicates the IRQ polarity is active-high [all …]
H A D	smsc,lan9115.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller 10 - Shawn Guo <shawnguo@kernel.org> 13 - $ref: ethernet-controller.yaml# 18 - const: smsc,lan9115 19 - items: 20 - enum: 21 - smsc,lan89218 [all …]`
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A D	microchip,ksz.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marek Vasut <marex@denx.de> 11 - Woojung Huh <Woojung.Huh@microchip.com> 14 - $ref: /schemas/spi/spi-peripheral-props.yaml# 21 - microchip,ksz8765 22 - microchip,ksz8794 23 - microchip,ksz8795 24 - microchip,ksz8863 [all …]`
/freebsd/sys/contrib/alpine-hal/
H A D	al_hal_pcie_w_reg.h	1 /- 10 found at http://www.gnu.org/licenses/gpl-2.0.html 376 - If MSI-X is enabled and auto_clear control bit =TRUE, automatically 377 * cleared after MSI-X message associated with this specific interrupt 378 * bit is sent (MSI-X acknowledge is received). 379 * - Software can set a bit in this register by writing 1 to the 381 * Write-0 clears a bit. Write-1 has no effect. 382 * - On CPU Read - If clear_on_read control bit =TRUE, automatically 400 * If Auto-mask control bit =TRUE, automatically set to 1 after MSI-X 408 * Used when auto-mask control bit=True. Enables CPU to clear a specific [all …]
H A D	al_hal_pcie_axi_reg.h	1 /- 10 found at http://www.gnu.org/licenses/gpl-2.0.html 148 [0x28] this register override the Target-ID field in the AXUSER [19:4], 199 * [0x44] this register override the Target-ID field in the AXUSER [19:4], 385 * - If MSI-X is enabled, and auto_clear control bit =TRUE, 386 * automatically cleared after MSI-X message associated with this 387 * specific interrupt bit is sent (MSI-X acknowledge is received). 388 * - Software can set a bit in this register by writing 1 to the 390 * Write-0 clears a bit. Write-1 has no effect. 391 * - On CPU Read -- If clear_on_read control bit =TRUE, automatically [all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A D	qcom-apq8060-dragonboard.dts	`1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 #include <dt-bindings/input/input.h> 3 #include <dt-bindings/gpio/gpio.h> 4 #include <dt-bindings/leds/common.h> 5 #include <dt-bindings/pinctrl/qcom,pmic-gpi [all...]`
/freebsd/sys/dev/e1000/
H A D	e1000_defines.h	2 SPDX-License-Identifier: BSD-3-Clause 4 Copyright (c) 2001-2020, Intel Corporation 45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable / 46 #define E1000_WUC_PME_STATUS 0x00000004 / PME Status / 47 #define E1000_WUC_APMPME 0x00000008 / Assert PME on APM Wakeup / 94 #define E1000_CTRL_EXT_IAME 0x08000000 / Int ACK Auto-mask / 122 #define E1000_RXD_STAT_PIF 0x80 / passed in-exact filter / 173 #define E1000_MANC_SMBUS_EN 0x00000001 / SMBus Enabled - RO / 174 #define E1000_MANC_ASF_EN 0x00000002 / ASF Enabled - RO / 262 #define E1000_CTRL_ASDE 0x00000020 / Auto-speed detect enable */ [all …]
H A D	if_em.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2001-2024, Intel Corporation 40 static const char em_driver_version[] = "7.7.8-fbsd"; 41 static const char igb_driver_version[] = "2.5.28-fbsd"; 55 /* Intel(R) - lem-class legacy devices / 136 / Intel(R) - em-class devices */ 185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 189 "Intel(R) 82566DM-2 ICH9 AMT"), 190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), [all …]`
/freebsd/sys/dev/igc/
H A D	igc_defines.h	1 /- 4 SPDX-License-Identifier: BSD-3-Clause 17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable / 18 #define IGC_WUC_PME_STATUS 0x00000004 / PME Status / 19 #define IGC_WUC_APMPME 0x00000008 / Assert PME on APM Wakeup / 72 #define IGC_CTRL_EXT_IAME 0x08000000 / Int ACK Auto-mask / 89 #define IGC_RXD_STAT_PIF 0x80 / passed in-exact filter / 128 #define IGC_MANC_SMBUS_EN 0x00000001 / SMBus Enabled - RO / 129 #define IGC_MANC_ASF_EN 0x00000002 / ASF Enabled - RO / 215 #define IGC_CTRL_ASDE 0x00000020 / Auto-speed detect enable */ [all …]
H A D	if_igc.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2001-2024, Intel Corporation 6 * Copyright (c) 2021-2024 Rubicon Communications, LLC (Netgate) 51 /* Intel(R) PRO/1000 Network Connection - igc */ 53 "Intel(R) Ethernet Controller I225-LM"), 55 "Intel(R) Ethernet Controller I225-V"), 57 "Intel(R) Ethernet Controller I225-K"), 59 "Intel(R) Ethernet Controller I225-IT"), 61 "Intel(R) Ethernet Controller I220-V"), [all …]`
/freebsd/sys/contrib/ncsw/Peripherals/QM/
H A D	fsl_qman.h	3 � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. 50 /* QMan s/w corenet portal, low-level i/face / 53 e_QmPortalPCI = 0, / PI index, cache-inhibited / 54 e_QmPortalPCE, / PI index, cache-enabled / 55 e_QmPortalPVB / valid-bit / 59 e_QmPortalEqcrCCI = 0, / CI index, cache-inhibited / 60 e_QmPortalEqcrCCE / CI index, cache-enabled / 64 e_QmPortalDqrrCCI = 0, / CI index, cache-inhibited / 65 e_QmPortalDqrrCCE, / CI index, cache-enabled / 70 e_QmPortalMrCCI = 0, / CI index, cache-inhibited */ [all …]
/freebsd/sys/dev/fxp/
H A D	if_fxp.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 94 * the first thing in the packet is a 14-byte Ethernet header. 97 * alignes the packet after the Ethernet header at a 32-bit 156 * sub-vendor and sub-device field are extensively used to identify 161 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" }, 162 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" }, 163 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 164 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 165 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, [all …]
/freebsd/sys/dev/msk/
H A D	if_mskreg.h	`17 * are provided to you under the BSD-type license terms provided 22 * - Redistributions of source code must retain the above copyright 24 * - Redistributions in binary form must reproduce the above 28 * - Neither the name of Marvell nor the names of its contributors 48 /- 49 SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause 65 * 4. Neither the name of the author nor the names of any co-contributors 82 /- 110 D-Link PCI vendor ID 154 * D-Link gigabit ethernet device ID [all …]`
/freebsd/sys/dev/jme/
H A D	if_jme.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 195 { -1, 0, 0 } 200 { -1, 0, 0 } 205 { -1, 0, 0 } 221 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) in jme_miibus_readreg() 226 for (i = JME_PHY_TIMEOUT; i > 0; i--) { in jme_miibus_readreg() 233 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); in jme_miibus_readreg() 252 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) in jme_miibus_writereg() 258 for (i = JME_PHY_TIMEOUT; i > 0; i--) { in jme_miibus_writereg() [all …]`
/freebsd/sys/dev/ste/
H A D	if_ste.c	1 /- 2 SPDX-License-Identifier: BSD-4-Clause 18 * 4. Neither the name of the author nor the names of any co-contributors 92 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 142 * MII bit-bang glue 201 * Read the MII serial port for the MII bit-bang module. 219 * Write the MII serial port for the MII bit-bang module. 259 mii = device_get_softc(sc->ste_miibus); in ste_miibus_statchg() 260 ifp = sc->ste_ifp; in ste_miibus_statchg() 265 sc->ste_flags &= ~STE_FLAG_LINK; in ste_miibus_statchg() [all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A D	ar9300_power.c	30 ahp->ah_mcast_filter_l32_set = 0; in ar9300_wowoffload_prep() 31 ahp->ah_mcast_filter_u32_set = 0; in ar9300_wowoffload_prep() 39 if (ahp->ah_mcast_filter_l32_set != 0) { in ar9300_wowoffload_post() 41 val &= ~ahp->ah_mcast_filter_l32_set; in ar9300_wowoffload_post() 44 if (ahp->ah_mcast_filter_u32_set != 0) { in ar9300_wowoffload_post() 46 val &= ~ahp->ah_mcast_filter_u32_set; in ar9300_wowoffload_post() 50 ahp->ah_mcast_filter_l32_set = 0; in ar9300_wowoffload_post() 51 ahp->ah_mcast_filter_u32_set = 0; in ar9300_wowoffload_post() 72 ahp->ah_mcast_filter_u32_set \|= (1 << pos); in ar9300_wowoffload_add_mcast_filter() 74 ahp->ah_mcast_filter_l32_set \|= (1 << pos); in ar9300_wowoffload_add_mcast_filter() [all …]
/freebsd/sys/dev/ixgbe/
H A D	ixgbe_type.h	`2 SPDX-License-Identifier: BSD-3-Clause 4 Copyright (c) 2001-2020, Intel Corporation 42 * - IXGBE_ERROR_INVALID_STATE 48 * - IXGBE_ERROR_POLLING 53 * - IXGBE_ERROR_CAUTION 58 * - IXGBE_ERROR_SOFTWARE 64 * - IXGBE_ERROR_ARGUMENT 69 * - IXGBE_ERROR_UNSUPPORTED 162 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)]) 359 #define NVM_OEM_PROD_VER_OFF_H 0x3 /* OEM Product version offset high */ [all …]`
/freebsd/sys/dev/sis/
H A D	if_sis.c	1 /- 2 SPDX-License-Identifier: BSD-4-Clause 4 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 19 * 4. Neither the name of the author nor the names of any co-contributors 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 54 * Both chips offer the standard bit-bang MII interface as well as 111 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 112 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 113 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 118 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) [all …]
/freebsd/sys/dev/vge/
H A D	if_vge.c	1 /- 2 SPDX-License-Identifier: BSD-4-Clause 18 * 4. Neither the name of the author nor the names of any co-contributors 46 * combines a tri-speed ethernet MAC and PHY, with the following 54 * o 64-bit multicast hash table filter 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 71 * The other issue has to do with the way 64-bit addresses are handled. 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of [all …]
/freebsd/sys/dev/alc/
H A D	if_alc.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 98 * enable MSI-X in alc_attach() depending on the card type. The operator can 248 nitems(alc_ident_table) - 1); 253 { -1, 0, 0 } 258 { -1, 0, 0 } 263 { -1, 0, 0 } 268 { -1, 0, 0 } 280 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) in alc_miibus_readreg() 299 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && in alc_mii_readreg_813x() [all …]`
/freebsd/sys/dev/qlnx/qlnxe/
H A D	reg_addr.h	2 * Copyright (c) 2017-2018 Cavium, Inc. 78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 116 … (0x1<<9) // Fast back-to-back transaction ena… 128 … (0x1<<23) // Fast back-to-back capable. Not ap… 145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
/freebsd/sys/dev/re/
H A D	if_re.c	1 /- 2 SPDX-License-Identifier: BSD-4-Clause 4 * Copyright (c) 1997, 1998-2003 18 * 4. Neither the name of the author nor the names of any co-contributors 59 * o 64-bit DMA 63 * o High and normal priority transmit DMA rings 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs [all …]
/freebsd/sys/dev/vr/
H A D	if_vr.c	1 /- 2 SPDX-License-Identifier: BSD-4-Clause 18 * 4. Neither the name of the author nor the names of any co-contributors 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 52 * receiver has a one entry perfect filter and a 64-bit hash table 257 device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg); in vr_miibus_readreg() 281 device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy, in vr_miibus_writereg() 289 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 302 mii = device_get_softc(sc->vr_miibus); in vr_miibus_statchg() 303 ifp = sc->vr_ifp; in vr_miibus_statchg() [all …]