Lines Matching +full:pme +full:- +full:active +full:- +full:high
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001-2024, Intel Corporation
6 * Copyright (c) 2021-2024 Rubicon Communications, LLC (Netgate)
51 /* Intel(R) PRO/1000 Network Connection - igc */
53 "Intel(R) Ethernet Controller I225-LM"),
55 "Intel(R) Ethernet Controller I225-V"),
57 "Intel(R) Ethernet Controller I225-K"),
59 "Intel(R) Ethernet Controller I225-IT"),
61 "Intel(R) Ethernet Controller I220-V"),
63 "Intel(R) Ethernet Controller I225-K(2)"),
65 "Intel(R) Ethernet Controller I225-LMvP(2)"),
67 "Intel(R) Ethernet Controller I226-K"),
69 "Intel(R) Ethernet Controller I226-LMvP"),
71 "Intel(R) Ethernet Controller I225-IT(2)"),
73 "Intel(R) Ethernet Controller I226-LM"),
75 "Intel(R) Ethernet Controller I226-V"),
77 "Intel(R) Ethernet Controller I226-IT"),
79 "Intel(R) Ethernet Controller I221-V"),
157 /* MSI-X handlers */
259 /* Energy efficient ethernet - default to OFF */
320 struct igc_hw *hw = &sc->hw; in igc_get_regs()
396 if_softc_ctx_t scctx = sc->shared; in igc_get_regs()
397 struct rx_ring *rxr = &rx_que->rxr; in igc_get_regs()
398 struct tx_ring *txr = &tx_que->txr; in igc_get_regs()
399 int ntxd = scctx->isc_ntxd[0]; in igc_get_regs()
400 int nrxd = scctx->isc_nrxd[0]; in igc_get_regs()
404 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); in igc_get_regs()
405 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); in igc_get_regs()
408 j, rxr->rx_base[j].read.buffer_addr, staterr, length); in igc_get_regs()
412 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; in igc_get_regs()
416 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, in igc_get_regs()
417 buf->eop != -1 ? in igc_get_regs()
418 txr->tx_base[buf->eop].upper.fields.status & in igc_get_regs()
473 sc->ctx = sc->osdep.ctx = ctx; in igc_if_attach_pre()
474 sc->dev = sc->osdep.dev = dev; in igc_if_attach_pre()
475 scctx = sc->shared = iflib_get_softc_ctx(ctx); in igc_if_attach_pre()
476 sc->media = iflib_get_media(ctx); in igc_if_attach_pre()
477 hw = &sc->hw; in igc_if_attach_pre()
485 sc->enable_aim = igc_enable_aim; in igc_if_attach_pre()
489 &sc->enable_aim, 0, in igc_if_attach_pre()
550 scctx->isc_tx_nsegments = IGC_MAX_SCATTER; in igc_if_attach_pre()
551 scctx->isc_nrxqsets_max = in igc_if_attach_pre()
552 scctx->isc_ntxqsets_max = igc_set_num_queues(ctx); in igc_if_attach_pre()
555 scctx->isc_ntxqsets_max); in igc_if_attach_pre()
557 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * in igc_if_attach_pre()
559 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * in igc_if_attach_pre()
561 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc); in igc_if_attach_pre()
562 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc); in igc_if_attach_pre()
563 scctx->isc_txrx = &igc_txrx; in igc_if_attach_pre()
564 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER; in igc_if_attach_pre()
565 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE; in igc_if_attach_pre()
566 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE; in igc_if_attach_pre()
567 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS; in igc_if_attach_pre()
568 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | in igc_if_attach_pre()
576 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR); in igc_if_attach_pre()
577 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) in igc_if_attach_pre()
578 scctx->isc_msix_bar += 4; in igc_if_attach_pre()
599 hw->mac.autoneg = DO_AUTO_NEG; in igc_if_attach_pre()
600 hw->phy.autoneg_wait_to_complete = false; in igc_if_attach_pre()
601 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; in igc_if_attach_pre()
604 if (hw->phy.media_type == igc_media_type_copper) { in igc_if_attach_pre()
605 hw->phy.mdix = AUTO_ALL_MODES; in igc_if_attach_pre()
612 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = in igc_if_attach_pre()
616 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * in igc_if_attach_pre()
618 if (sc->mta == NULL) { in igc_if_attach_pre()
631 sc->hw.dev_spec._i225.eee_disable = igc_eee_setting; in igc_if_attach_pre()
649 ** Some PCI-E parts fail the first check due to in igc_if_attach_pre()
669 if (!igc_is_valid_ether_addr(hw->mac.addr)) { in igc_if_attach_pre()
681 * Get Wake-on-Lan and Management info for later use in igc_if_attach_pre()
686 scctx->isc_capenable &= ~IFCAP_WOL; in igc_if_attach_pre()
687 if (sc->wol != 0) in igc_if_attach_pre()
688 scctx->isc_capenable |= IFCAP_WOL_MAGIC; in igc_if_attach_pre()
690 iflib_set_mac(ctx, hw->mac.addr); in igc_if_attach_pre()
698 free(sc->mta, M_DEVBUF); in igc_if_attach_pre()
707 struct igc_hw *hw = &sc->hw; in igc_if_attach_post()
720 hw->mac.get_link_status = true; in igc_if_attach_post()
735 free(sc->mta, M_DEVBUF); in igc_if_attach_post()
756 igc_phy_hw_reset(&sc->hw); in igc_if_detach()
809 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { in igc_if_mtu_set()
813 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = in igc_if_mtu_set()
831 if_softc_ctx_t scctx = sc->shared; in igc_if_init()
839 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, in igc_if_init()
843 igc_rar_set(&sc->hw, sc->hw.mac.addr, 0); in igc_if_init()
849 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; in igc_if_init()
851 struct tx_ring *txr = &tx_que->txr; in igc_if_init()
853 txr->tx_rs_cidx = txr->tx_rs_pidx; in igc_if_init()
857 * off-by-one error when calculating how many descriptors are in igc_if_init()
860 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; in igc_if_init()
864 IGC_WRITE_REG(&sc->hw, IGC_VET, ETHERTYPE_VLAN); in igc_if_init()
872 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); in igc_if_init()
880 igc_clear_hw_cntrs_base_generic(&sc->hw); in igc_if_init()
882 if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ in igc_if_init()
886 IGC_READ_REG(&sc->hw, IGC_ICR); in igc_if_init()
887 IGC_WRITE_REG(&sc->hw, IGC_ICS, IGC_ICS_LSC); in igc_if_init()
893 igc_set_eee_i225(&sc->hw, true, true, true); in igc_if_init()
911 struct igc_hw *hw = &sc->hw; in igc_neweitr()
919 if ((txr->tx_bytes == 0) && (rxr->rx_bytes == 0)) in igc_neweitr()
924 if (sc->enable_aim) { in igc_neweitr()
925 nextlatency = rxr->rx_nextlatency; in igc_neweitr()
927 /* Use half default (4K) ITR if sub-gig */ in igc_neweitr()
928 if (sc->link_speed < 1000) { in igc_neweitr()
933 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { in igc_neweitr()
935 sc->enable_aim = 0; in igc_neweitr()
940 if (txr->tx_bytes && txr->tx_packets) { in igc_neweitr()
941 bytes = txr->tx_bytes; in igc_neweitr()
942 bytes_packets = txr->tx_bytes/txr->tx_packets; in igc_neweitr()
943 packets = txr->tx_packets; in igc_neweitr()
945 if (rxr->rx_bytes && rxr->rx_packets) { in igc_neweitr()
946 bytes = max(bytes, rxr->rx_bytes); in igc_neweitr()
948 rxr->rx_bytes/rxr->rx_packets); in igc_neweitr()
949 packets = max(packets, rxr->rx_packets); in igc_neweitr()
989 device_printf(sc->dev, in igc_neweitr()
996 if (sc->enable_aim == 1 && nextlatency == eitr_latency_lowest) in igc_neweitr()
1000 rxr->rx_nextlatency = nextlatency; in igc_neweitr()
1004 rxr->rx_nextlatency = nextlatency; in igc_neweitr()
1029 if (neweitr != que->eitr_setting) { in igc_neweitr()
1030 que->eitr_setting = neweitr; in igc_neweitr()
1031 IGC_WRITE_REG(hw, IGC_EITR(que->msix), que->eitr_setting); in igc_neweitr()
1044 struct igc_hw *hw = &sc->hw; in igc_intr()
1045 struct igc_rx_queue *que = &sc->rx_queues[0]; in igc_intr()
1046 struct tx_ring *txr = &sc->tx_queues[0].txr; in igc_intr()
1047 struct rx_ring *rxr = &que->rxr; in igc_intr()
1048 if_ctx_t ctx = sc->ctx; in igc_intr()
1065 * Only MSI-X interrupts have one-shot behavior by taking advantage in igc_intr()
1077 sc->rx_overruns++; in igc_intr()
1082 txr->tx_bytes = 0; in igc_intr()
1083 txr->tx_packets = 0; in igc_intr()
1084 rxr->rx_bytes = 0; in igc_intr()
1085 rxr->rx_packets = 0; in igc_intr()
1094 struct igc_rx_queue *rxq = &sc->rx_queues[rxqid]; in igc_if_rx_queue_intr_enable()
1096 IGC_WRITE_REG(&sc->hw, IGC_EIMS, rxq->eims); in igc_if_rx_queue_intr_enable()
1104 struct igc_tx_queue *txq = &sc->tx_queues[txqid]; in igc_if_tx_queue_intr_enable()
1106 IGC_WRITE_REG(&sc->hw, IGC_EIMS, txq->eims); in igc_if_tx_queue_intr_enable()
1112 * MSI-X RX Interrupt Service routine
1119 struct igc_softc *sc = que->sc; in igc_msix_que()
1120 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; in igc_msix_que()
1121 struct rx_ring *rxr = &que->rxr; in igc_msix_que()
1123 ++que->irqs; in igc_msix_que()
1128 txr->tx_bytes = 0; in igc_msix_que()
1129 txr->tx_packets = 0; in igc_msix_que()
1130 rxr->rx_bytes = 0; in igc_msix_que()
1131 rxr->rx_packets = 0; in igc_msix_que()
1138 * MSI-X Link Fast Interrupt Service routine
1147 ++sc->link_irq; in igc_msix_link()
1148 MPASS(sc->hw.back != NULL); in igc_msix_link()
1149 reg_icr = IGC_READ_REG(&sc->hw, IGC_ICR); in igc_msix_link()
1152 sc->rx_overruns++; in igc_msix_link()
1155 igc_handle_link(sc->ctx); in igc_msix_link()
1158 IGC_WRITE_REG(&sc->hw, IGC_IMS, IGC_IMS_LSC); in igc_msix_link()
1159 IGC_WRITE_REG(&sc->hw, IGC_EIMS, sc->link_mask); in igc_msix_link()
1170 sc->hw.mac.get_link_status = true; in igc_handle_link()
1191 ifmr->ifm_status = IFM_AVALID; in igc_if_media_status()
1192 ifmr->ifm_active = IFM_ETHER; in igc_if_media_status()
1194 if (!sc->link_active) { in igc_if_media_status()
1198 ifmr->ifm_status |= IFM_ACTIVE; in igc_if_media_status()
1200 switch (sc->link_speed) { in igc_if_media_status()
1202 ifmr->ifm_active |= IFM_10_T; in igc_if_media_status()
1205 ifmr->ifm_active |= IFM_100_TX; in igc_if_media_status()
1208 ifmr->ifm_active |= IFM_1000_T; in igc_if_media_status()
1211 ifmr->ifm_active |= IFM_2500_T; in igc_if_media_status()
1215 if (sc->link_duplex == FULL_DUPLEX) in igc_if_media_status()
1216 ifmr->ifm_active |= IFM_FDX; in igc_if_media_status()
1218 ifmr->ifm_active |= IFM_HDX; in igc_if_media_status()
1237 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) in igc_if_media_change()
1240 sc->hw.mac.autoneg = DO_AUTO_NEG; in igc_if_media_change()
1242 switch (IFM_SUBTYPE(ifm->ifm_media)) { in igc_if_media_change()
1244 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; in igc_if_media_change()
1247 sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; in igc_if_media_change()
1250 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; in igc_if_media_change()
1253 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) in igc_if_media_change()
1254 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; in igc_if_media_change()
1256 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; in igc_if_media_change()
1259 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) in igc_if_media_change()
1260 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; in igc_if_media_change()
1262 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; in igc_if_media_change()
1265 device_printf(sc->dev, "Unsupported media type\n"); in igc_if_media_change()
1281 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); in igc_if_set_promisc()
1291 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); in igc_if_set_promisc()
1298 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); in igc_if_set_promisc()
1302 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); in igc_if_set_promisc()
1338 mta = sc->mta; in igc_if_multi_set()
1343 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); in igc_if_multi_set()
1358 igc_update_mc_addr_list(&sc->hw, mta, mcnt); in igc_if_multi_set()
1360 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); in igc_if_multi_set()
1368 * controller-specific hardware patting.
1385 struct igc_hw *hw = &sc->hw; in igc_if_update_admin_status()
1391 switch (hw->phy.media_type) { in igc_if_update_admin_status()
1393 if (hw->mac.get_link_status == true) { in igc_if_update_admin_status()
1396 link_check = !hw->mac.get_link_status; in igc_if_update_admin_status()
1402 link_check = !hw->mac.get_link_status; in igc_if_update_admin_status()
1409 if (link_check && (sc->link_active == 0)) { in igc_if_update_admin_status()
1410 igc_get_speed_and_duplex(hw, &sc->link_speed, in igc_if_update_admin_status()
1411 &sc->link_duplex); in igc_if_update_admin_status()
1414 sc->link_speed, in igc_if_update_admin_status()
1415 ((sc->link_duplex == FULL_DUPLEX) ? in igc_if_update_admin_status()
1417 sc->link_active = 1; in igc_if_update_admin_status()
1419 IF_Mbps(sc->link_speed)); in igc_if_update_admin_status()
1420 } else if (!link_check && (sc->link_active == 1)) { in igc_if_update_admin_status()
1421 sc->link_speed = 0; in igc_if_update_admin_status()
1422 sc->link_duplex = 0; in igc_if_update_admin_status()
1423 sc->link_active = 0; in igc_if_update_admin_status()
1438 sc->watchdog_events++; in igc_if_watchdog_reset()
1454 igc_reset_hw(&sc->hw); in igc_if_stop()
1455 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); in igc_if_stop()
1470 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); in igc_identify_hardware()
1473 sc->hw.vendor_id = pci_get_vendor(dev); in igc_identify_hardware()
1474 sc->hw.device_id = pci_get_device(dev); in igc_identify_hardware()
1475 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); in igc_identify_hardware()
1476 sc->hw.subsystem_vendor_id = in igc_identify_hardware()
1478 sc->hw.subsystem_device_id = in igc_identify_hardware()
1482 if (igc_set_mac_type(&sc->hw)) { in igc_identify_hardware()
1496 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, in igc_allocate_pci_resources()
1498 if (sc->memory == NULL) { in igc_allocate_pci_resources()
1503 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); in igc_allocate_pci_resources()
1504 sc->osdep.mem_bus_space_handle = in igc_allocate_pci_resources()
1505 rman_get_bushandle(sc->memory); in igc_allocate_pci_resources()
1506 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; in igc_allocate_pci_resources()
1508 sc->hw.back = &sc->osdep; in igc_allocate_pci_resources()
1515 * Set up the MSI-X Interrupt handlers
1522 struct igc_rx_queue *rx_que = sc->rx_queues; in igc_if_msix_intr_assign()
1523 struct igc_tx_queue *tx_que = sc->tx_queues; in igc_if_msix_intr_assign()
1528 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { in igc_if_msix_intr_assign()
1531 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, in igc_if_msix_intr_assign()
1532 IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf); in igc_if_msix_intr_assign()
1537 sc->rx_num_queues = i + 1; in igc_if_msix_intr_assign()
1541 rx_que->msix = vector; in igc_if_msix_intr_assign()
1545 * in IGC_IMS -- bits 20 and 21 in igc_if_msix_intr_assign()
1547 * NOTHING to do with the MSI-X vector in igc_if_msix_intr_assign()
1549 rx_que->eims = 1 << vector; in igc_if_msix_intr_assign()
1554 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { in igc_if_msix_intr_assign()
1556 tx_que = &sc->tx_queues[i]; in igc_if_msix_intr_assign()
1558 &sc->rx_queues[i % sc->rx_num_queues].que_irq, in igc_if_msix_intr_assign()
1559 IFLIB_INTR_TX, tx_que, tx_que->me, buf); in igc_if_msix_intr_assign()
1561 tx_que->msix = (vector % sc->rx_num_queues); in igc_if_msix_intr_assign()
1565 * in IGC_IMS -- bits 22 and 23 in igc_if_msix_intr_assign()
1567 * NOTHING to do with the MSI-X vector in igc_if_msix_intr_assign()
1569 tx_que->eims = 1 << i; in igc_if_msix_intr_assign()
1574 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, in igc_if_msix_intr_assign()
1582 sc->linkvec = rx_vectors; in igc_if_msix_intr_assign()
1585 iflib_irq_free(ctx, &sc->irq); in igc_if_msix_intr_assign()
1586 rx_que = sc->rx_queues; in igc_if_msix_intr_assign()
1587 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) in igc_if_msix_intr_assign()
1588 iflib_irq_free(ctx, &rx_que->que_irq); in igc_if_msix_intr_assign()
1595 struct igc_hw *hw = &sc->hw; in igc_configure_queues()
1605 /* Turn on MSI-X */ in igc_configure_queues()
1607 for (int i = 0; i < sc->rx_num_queues; i++) { in igc_configure_queues()
1610 rx_que = &sc->rx_queues[i]; in igc_configure_queues()
1613 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16; in igc_configure_queues()
1616 ivar |= rx_que->msix | IGC_IVAR_VALID; in igc_configure_queues()
1621 for (int i = 0; i < sc->tx_num_queues; i++) { in igc_configure_queues()
1624 tx_que = &sc->tx_queues[i]; in igc_configure_queues()
1627 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24; in igc_configure_queues()
1630 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8; in igc_configure_queues()
1633 sc->que_mask |= tx_que->eims; in igc_configure_queues()
1637 ivar = (sc->linkvec | IGC_IVAR_VALID) << 8; in igc_configure_queues()
1638 sc->link_mask = 1 << sc->linkvec; in igc_configure_queues()
1647 for (int i = 0; i < sc->rx_num_queues; i++) { in igc_configure_queues()
1648 rx_que = &sc->rx_queues[i]; in igc_configure_queues()
1649 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), newitr); in igc_configure_queues()
1659 struct igc_rx_queue *que = sc->rx_queues; in igc_free_pci_resources()
1662 /* Release all MSI-X queue resources */ in igc_free_pci_resources()
1663 if (sc->intr_type == IFLIB_INTR_MSIX) in igc_free_pci_resources()
1664 iflib_irq_free(ctx, &sc->irq); in igc_free_pci_resources()
1666 for (int i = 0; i < sc->rx_num_queues; i++, que++) { in igc_free_pci_resources()
1667 iflib_irq_free(ctx, &que->que_irq); in igc_free_pci_resources()
1670 if (sc->memory != NULL) { in igc_free_pci_resources()
1672 rman_get_rid(sc->memory), sc->memory); in igc_free_pci_resources()
1673 sc->memory = NULL; in igc_free_pci_resources()
1676 if (sc->flash != NULL) { in igc_free_pci_resources()
1678 rman_get_rid(sc->flash), sc->flash); in igc_free_pci_resources()
1679 sc->flash = NULL; in igc_free_pci_resources()
1682 if (sc->ioport != NULL) { in igc_free_pci_resources()
1684 rman_get_rid(sc->ioport), sc->ioport); in igc_free_pci_resources()
1685 sc->ioport = NULL; in igc_free_pci_resources()
1689 /* Set up MSI or MSI-X */
1704 device_t dev = sc->dev; in igc_init_dmac()
1705 struct igc_hw *hw = &sc->hw; in igc_init_dmac()
1711 max_frame_size = sc->shared->isc_max_frame_size; in igc_init_dmac()
1713 if (sc->dmac == 0) { /* Disabling it */ in igc_init_dmac()
1722 hwm = 64 * pba - max_frame_size / 16; in igc_init_dmac()
1723 if (hwm < 64 * (pba - 6)) in igc_init_dmac()
1724 hwm = 64 * (pba - 6); in igc_init_dmac()
1731 dmac = pba - max_frame_size / 512; in igc_init_dmac()
1732 if (dmac < pba - 10) in igc_init_dmac()
1733 dmac = pba - 10; in igc_init_dmac()
1751 reg |= ((sc->dmac * 5) >> 6); in igc_init_dmac()
1753 reg |= (sc->dmac >> 5); in igc_init_dmac()
1777 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - in igc_init_dmac()
1797 struct igc_hw *hw = &sc->hw; in igc_reset()
1817 * - High water mark should allow for at least two frames to be in igc_reset()
1819 * - Low water mark works best when it is very near the high water in igc_reset()
1827 * - The pause time is fairly large at 1000 x 512ns = 512 usec. in igc_reset()
1830 hw->fc.high_water = rx_buffer_size - in igc_reset()
1831 roundup2(sc->hw.mac.max_frame_size, 1024); in igc_reset()
1832 /* 16-byte granularity */ in igc_reset()
1833 hw->fc.low_water = hw->fc.high_water - 16; in igc_reset()
1835 if (sc->fc) /* locally set flow control value? */ in igc_reset()
1836 hw->fc.requested_mode = sc->fc; in igc_reset()
1838 hw->fc.requested_mode = igc_fc_full; in igc_reset()
1840 hw->fc.pause_time = IGC_FC_PAUSE_TIME; in igc_reset()
1842 hw->fc.send_xon = true; in igc_reset()
1848 /* and a re-init */ in igc_reset()
1858 sc->pba = pba; in igc_reset()
1874 struct igc_hw *hw = &sc->hw; in igc_initialize_rss_mapping()
1886 * This just allocates buckets to queues using round-robin in igc_initialize_rss_mapping()
1911 queue_id = queue_id % sc->rx_num_queues; in igc_initialize_rss_mapping()
1913 queue_id = (i % sc->rx_num_queues); in igc_initialize_rss_mapping()
1972 if_softc_ctx_t scctx = sc->shared; in igc_setup_interface()
1977 if (sc->tx_num_queues == 1) { in igc_setup_interface()
1978 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); in igc_setup_interface()
1986 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); in igc_setup_interface()
1987 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); in igc_setup_interface()
1988 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); in igc_setup_interface()
1989 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); in igc_setup_interface()
1990 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); in igc_setup_interface()
1991 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); in igc_setup_interface()
1992 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL); in igc_setup_interface()
1994 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); in igc_setup_interface()
1995 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); in igc_setup_interface()
2004 if_softc_ctx_t scctx = sc->shared; in igc_if_tx_queues_alloc()
2009 MPASS(sc->tx_num_queues > 0); in igc_if_tx_queues_alloc()
2010 MPASS(sc->tx_num_queues == ntxqsets); in igc_if_tx_queues_alloc()
2013 if (!(sc->tx_queues = in igc_if_tx_queues_alloc()
2015 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { in igc_if_tx_queues_alloc()
2021 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { in igc_if_tx_queues_alloc()
2024 struct tx_ring *txr = &que->txr; in igc_if_tx_queues_alloc()
2025 txr->sc = que->sc = sc; in igc_if_tx_queues_alloc()
2026 que->me = txr->me = i; in igc_if_tx_queues_alloc()
2029 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * in igc_if_tx_queues_alloc()
2030 scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { in igc_if_tx_queues_alloc()
2036 for (j = 0; j < scctx->isc_ntxd[0]; j++) in igc_if_tx_queues_alloc()
2037 txr->tx_rsq[j] = QIDX_INVALID; in igc_if_tx_queues_alloc()
2039 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs]; in igc_if_tx_queues_alloc()
2040 txr->tx_paddr = paddrs[i*ntxqs]; in igc_if_tx_queues_alloc()
2045 "allocated for %d tx_queues\n", sc->tx_num_queues); in igc_if_tx_queues_alloc()
2061 MPASS(sc->rx_num_queues > 0); in igc_if_rx_queues_alloc()
2062 MPASS(sc->rx_num_queues == nrxqsets); in igc_if_rx_queues_alloc()
2065 if (!(sc->rx_queues = in igc_if_rx_queues_alloc()
2067 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { in igc_if_rx_queues_alloc()
2074 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { in igc_if_rx_queues_alloc()
2076 struct rx_ring *rxr = &que->rxr; in igc_if_rx_queues_alloc()
2077 rxr->sc = que->sc = sc; in igc_if_rx_queues_alloc()
2078 rxr->que = que; in igc_if_rx_queues_alloc()
2079 que->me = rxr->me = i; in igc_if_rx_queues_alloc()
2082 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs]; in igc_if_rx_queues_alloc()
2083 rxr->rx_paddr = paddrs[i*nrxqs]; in igc_if_rx_queues_alloc()
2088 "allocated for %d rx_queues\n", sc->rx_num_queues); in igc_if_rx_queues_alloc()
2100 struct igc_tx_queue *tx_que = sc->tx_queues; in igc_if_queues_free()
2101 struct igc_rx_queue *rx_que = sc->rx_queues; in igc_if_queues_free()
2104 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { in igc_if_queues_free()
2105 struct tx_ring *txr = &tx_que->txr; in igc_if_queues_free()
2106 if (txr->tx_rsq == NULL) in igc_if_queues_free()
2109 free(txr->tx_rsq, M_DEVBUF); in igc_if_queues_free()
2110 txr->tx_rsq = NULL; in igc_if_queues_free()
2112 free(sc->tx_queues, M_DEVBUF); in igc_if_queues_free()
2113 sc->tx_queues = NULL; in igc_if_queues_free()
2117 free(sc->rx_queues, M_DEVBUF); in igc_if_queues_free()
2118 sc->rx_queues = NULL; in igc_if_queues_free()
2121 if (sc->mta != NULL) { in igc_if_queues_free()
2122 free(sc->mta, M_DEVBUF); in igc_if_queues_free()
2135 if_softc_ctx_t scctx = sc->shared; in igc_initialize_transmit_unit()
2138 struct igc_hw *hw = &sc->hw; in igc_initialize_transmit_unit()
2143 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { in igc_initialize_transmit_unit()
2147 que = &sc->tx_queues[i]; in igc_initialize_transmit_unit()
2148 txr = &que->txr; in igc_initialize_transmit_unit()
2149 bus_addr = txr->tx_paddr; in igc_initialize_transmit_unit()
2152 offp = (caddr_t)&txr->csum_flags; in igc_initialize_transmit_unit()
2154 bzero(offp, endp - offp); in igc_initialize_transmit_unit()
2158 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc)); in igc_initialize_transmit_unit()
2168 IGC_READ_REG(&sc->hw, IGC_TDBAL(i)), in igc_initialize_transmit_unit()
2169 IGC_READ_REG(&sc->hw, IGC_TDLEN(i))); in igc_initialize_transmit_unit()
2183 tctl = IGC_READ_REG(&sc->hw, IGC_TCTL); in igc_initialize_transmit_unit()
2189 IGC_WRITE_REG(&sc->hw, IGC_TCTL, tctl); in igc_initialize_transmit_unit()
2197 #define BSIZEPKT_ROUNDUP ((1<<IGC_SRRCTL_BSIZEPKT_SHIFT)-1)
2203 if_softc_ctx_t scctx = sc->shared; in igc_initialize_receive_unit()
2205 struct igc_hw *hw = &sc->hw; in igc_initialize_receive_unit()
2223 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); in igc_initialize_receive_unit()
2241 if (sc->tx_num_queues > 1) in igc_initialize_receive_unit()
2246 if (sc->tx_num_queues > 1) in igc_initialize_receive_unit()
2253 if (sc->rx_num_queues > 1) in igc_initialize_receive_unit()
2257 psize = scctx->isc_max_frame_size; in igc_initialize_receive_unit()
2261 IGC_WRITE_REG(&sc->hw, IGC_RLPML, psize); in igc_initialize_receive_unit()
2265 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> in igc_initialize_receive_unit()
2276 if ((sc->rx_num_queues > 1) && in igc_initialize_receive_unit()
2277 (sc->fc == igc_fc_none || in igc_initialize_receive_unit()
2278 sc->fc == igc_fc_rx_pause)) { in igc_initialize_receive_unit()
2283 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { in igc_initialize_receive_unit()
2284 struct rx_ring *rxr = &que->rxr; in igc_initialize_receive_unit()
2285 u64 bus_addr = rxr->rx_paddr; in igc_initialize_receive_unit()
2289 /* Configure for header split? -- ignore for now */ in igc_initialize_receive_unit()
2290 rxr->hdr_split = igc_header_split; in igc_initialize_receive_unit()
2296 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc)); in igc_initialize_receive_unit()
2326 struct igc_hw *hw = &sc->hw; in igc_setup_vlan_hw_support()
2348 struct igc_hw *hw = &sc->hw; in igc_if_intr_enable()
2351 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { in igc_if_intr_enable()
2352 mask = (sc->que_mask | sc->link_mask); in igc_if_intr_enable()
2366 struct igc_hw *hw = &sc->hw; in igc_if_intr_disable()
2368 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { in igc_if_intr_disable()
2387 if (sc->vf_ifp) in igc_get_hw_control()
2390 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); in igc_get_hw_control()
2391 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, in igc_get_hw_control()
2406 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); in igc_release_hw_control()
2407 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, in igc_release_hw_control()
2426 ** to both system management and wake-on-lan for
2436 eeprom_data = IGC_READ_REG(&sc->hw, IGC_WUC); in igc_get_wakeup()
2439 sc->wol = IGC_WUFC_LNKC; in igc_get_wakeup()
2464 sc->wol &= ~IGC_WUFC_MAG; in igc_enable_wakeup()
2467 sc->wol &= ~IGC_WUFC_EX; in igc_enable_wakeup()
2470 sc->wol &= ~IGC_WUFC_MC; in igc_enable_wakeup()
2472 rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); in igc_enable_wakeup()
2474 IGC_WRITE_REG(&sc->hw, IGC_RCTL, rctl); in igc_enable_wakeup()
2477 if (!(sc->wol & (IGC_WUFC_EX | IGC_WUFC_MAG | IGC_WUFC_MC))) in igc_enable_wakeup()
2478 goto pme; in igc_enable_wakeup()
2481 ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL); in igc_enable_wakeup()
2483 IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl); in igc_enable_wakeup()
2486 IGC_WRITE_REG(&sc->hw, IGC_WUC, IGC_WUC_PME_EN); in igc_enable_wakeup()
2487 IGC_WRITE_REG(&sc->hw, IGC_WUFC, sc->wol); in igc_enable_wakeup()
2489 pme: in igc_enable_wakeup()
2507 u64 prev_xoffrxc = sc->stats.xoffrxc; in igc_update_stats_counters()
2509 sc->stats.crcerrs += IGC_READ_REG(&sc->hw, IGC_CRCERRS); in igc_update_stats_counters()
2510 sc->stats.mpc += IGC_READ_REG(&sc->hw, IGC_MPC); in igc_update_stats_counters()
2511 sc->stats.scc += IGC_READ_REG(&sc->hw, IGC_SCC); in igc_update_stats_counters()
2512 sc->stats.ecol += IGC_READ_REG(&sc->hw, IGC_ECOL); in igc_update_stats_counters()
2514 sc->stats.mcc += IGC_READ_REG(&sc->hw, IGC_MCC); in igc_update_stats_counters()
2515 sc->stats.latecol += IGC_READ_REG(&sc->hw, IGC_LATECOL); in igc_update_stats_counters()
2516 sc->stats.colc += IGC_READ_REG(&sc->hw, IGC_COLC); in igc_update_stats_counters()
2517 sc->stats.colc += IGC_READ_REG(&sc->hw, IGC_RERC); in igc_update_stats_counters()
2518 sc->stats.dc += IGC_READ_REG(&sc->hw, IGC_DC); in igc_update_stats_counters()
2519 sc->stats.rlec += IGC_READ_REG(&sc->hw, IGC_RLEC); in igc_update_stats_counters()
2520 sc->stats.xonrxc += IGC_READ_REG(&sc->hw, IGC_XONRXC); in igc_update_stats_counters()
2521 sc->stats.xontxc += IGC_READ_REG(&sc->hw, IGC_XONTXC); in igc_update_stats_counters()
2522 sc->stats.xoffrxc += IGC_READ_REG(&sc->hw, IGC_XOFFRXC); in igc_update_stats_counters()
2527 if (sc->stats.xoffrxc != prev_xoffrxc) in igc_update_stats_counters()
2528 sc->shared->isc_pause_frames = 1; in igc_update_stats_counters()
2529 sc->stats.xofftxc += IGC_READ_REG(&sc->hw, IGC_XOFFTXC); in igc_update_stats_counters()
2530 sc->stats.fcruc += IGC_READ_REG(&sc->hw, IGC_FCRUC); in igc_update_stats_counters()
2531 sc->stats.prc64 += IGC_READ_REG(&sc->hw, IGC_PRC64); in igc_update_stats_counters()
2532 sc->stats.prc127 += IGC_READ_REG(&sc->hw, IGC_PRC127); in igc_update_stats_counters()
2533 sc->stats.prc255 += IGC_READ_REG(&sc->hw, IGC_PRC255); in igc_update_stats_counters()
2534 sc->stats.prc511 += IGC_READ_REG(&sc->hw, IGC_PRC511); in igc_update_stats_counters()
2535 sc->stats.prc1023 += IGC_READ_REG(&sc->hw, IGC_PRC1023); in igc_update_stats_counters()
2536 sc->stats.prc1522 += IGC_READ_REG(&sc->hw, IGC_PRC1522); in igc_update_stats_counters()
2537 sc->stats.tlpic += IGC_READ_REG(&sc->hw, IGC_TLPIC); in igc_update_stats_counters()
2538 sc->stats.rlpic += IGC_READ_REG(&sc->hw, IGC_RLPIC); in igc_update_stats_counters()
2539 sc->stats.gprc += IGC_READ_REG(&sc->hw, IGC_GPRC); in igc_update_stats_counters()
2540 sc->stats.bprc += IGC_READ_REG(&sc->hw, IGC_BPRC); in igc_update_stats_counters()
2541 sc->stats.mprc += IGC_READ_REG(&sc->hw, IGC_MPRC); in igc_update_stats_counters()
2542 sc->stats.gptc += IGC_READ_REG(&sc->hw, IGC_GPTC); in igc_update_stats_counters()
2544 /* For the 64-bit byte counters the low dword must be read first. */ in igc_update_stats_counters()
2545 /* Both registers clear on the read of the high dword */ in igc_update_stats_counters()
2547 sc->stats.gorc += IGC_READ_REG(&sc->hw, IGC_GORCL) + in igc_update_stats_counters()
2548 ((u64)IGC_READ_REG(&sc->hw, IGC_GORCH) << 32); in igc_update_stats_counters()
2549 sc->stats.gotc += IGC_READ_REG(&sc->hw, IGC_GOTCL) + in igc_update_stats_counters()
2550 ((u64)IGC_READ_REG(&sc->hw, IGC_GOTCH) << 32); in igc_update_stats_counters()
2552 sc->stats.rnbc += IGC_READ_REG(&sc->hw, IGC_RNBC); in igc_update_stats_counters()
2553 sc->stats.ruc += IGC_READ_REG(&sc->hw, IGC_RUC); in igc_update_stats_counters()
2554 sc->stats.rfc += IGC_READ_REG(&sc->hw, IGC_RFC); in igc_update_stats_counters()
2555 sc->stats.roc += IGC_READ_REG(&sc->hw, IGC_ROC); in igc_update_stats_counters()
2556 sc->stats.rjc += IGC_READ_REG(&sc->hw, IGC_RJC); in igc_update_stats_counters()
2558 sc->stats.mgprc += IGC_READ_REG(&sc->hw, IGC_MGTPRC); in igc_update_stats_counters()
2559 sc->stats.mgpdc += IGC_READ_REG(&sc->hw, IGC_MGTPDC); in igc_update_stats_counters()
2560 sc->stats.mgptc += IGC_READ_REG(&sc->hw, IGC_MGTPTC); in igc_update_stats_counters()
2562 sc->stats.tor += IGC_READ_REG(&sc->hw, IGC_TORH); in igc_update_stats_counters()
2563 sc->stats.tot += IGC_READ_REG(&sc->hw, IGC_TOTH); in igc_update_stats_counters()
2565 sc->stats.tpr += IGC_READ_REG(&sc->hw, IGC_TPR); in igc_update_stats_counters()
2566 sc->stats.tpt += IGC_READ_REG(&sc->hw, IGC_TPT); in igc_update_stats_counters()
2567 sc->stats.ptc64 += IGC_READ_REG(&sc->hw, IGC_PTC64); in igc_update_stats_counters()
2568 sc->stats.ptc127 += IGC_READ_REG(&sc->hw, IGC_PTC127); in igc_update_stats_counters()
2569 sc->stats.ptc255 += IGC_READ_REG(&sc->hw, IGC_PTC255); in igc_update_stats_counters()
2570 sc->stats.ptc511 += IGC_READ_REG(&sc->hw, IGC_PTC511); in igc_update_stats_counters()
2571 sc->stats.ptc1023 += IGC_READ_REG(&sc->hw, IGC_PTC1023); in igc_update_stats_counters()
2572 sc->stats.ptc1522 += IGC_READ_REG(&sc->hw, IGC_PTC1522); in igc_update_stats_counters()
2573 sc->stats.mptc += IGC_READ_REG(&sc->hw, IGC_MPTC); in igc_update_stats_counters()
2574 sc->stats.bptc += IGC_READ_REG(&sc->hw, IGC_BPTC); in igc_update_stats_counters()
2577 sc->stats.iac += IGC_READ_REG(&sc->hw, IGC_IAC); in igc_update_stats_counters()
2578 sc->stats.rxdmtc += IGC_READ_REG(&sc->hw, IGC_RXDMTC); in igc_update_stats_counters()
2580 sc->stats.algnerrc += IGC_READ_REG(&sc->hw, IGC_ALGNERRC); in igc_update_stats_counters()
2581 sc->stats.tncrs += IGC_READ_REG(&sc->hw, IGC_TNCRS); in igc_update_stats_counters()
2582 sc->stats.htdpmc += IGC_READ_REG(&sc->hw, IGC_HTDPMC); in igc_update_stats_counters()
2583 sc->stats.tsctc += IGC_READ_REG(&sc->hw, IGC_TSCTC); in igc_update_stats_counters()
2594 return (sc->stats.colc); in igc_if_get_counter()
2596 return (sc->dropped_pkts + sc->stats.rxerrc + in igc_if_get_counter()
2597 sc->stats.crcerrs + sc->stats.algnerrc + in igc_if_get_counter()
2598 sc->stats.ruc + sc->stats.roc + in igc_if_get_counter()
2599 sc->stats.mpc + sc->stats.htdpmc); in igc_if_get_counter()
2601 return (sc->stats.ecol + sc->stats.latecol + in igc_if_get_counter()
2602 sc->watchdog_events); in igc_if_get_counter()
2608 /* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized
2626 /* Export a single 32-bit register via a read-only sysctl. */
2633 sc = oidp->oid_arg1; in igc_sysctl_reg_handler()
2634 val = IGC_READ_REG(&sc->hw, oidp->oid_arg2); in igc_sysctl_reg_handler()
2648 bool tx = oidp->oid_arg2; in igc_sysctl_interrupt_rate_handler()
2651 tque = oidp->oid_arg1; in igc_sysctl_interrupt_rate_handler()
2652 hw = &tque->sc->hw; in igc_sysctl_interrupt_rate_handler()
2653 reg = IGC_READ_REG(hw, IGC_EITR(tque->me)); in igc_sysctl_interrupt_rate_handler()
2655 rque = oidp->oid_arg1; in igc_sysctl_interrupt_rate_handler()
2656 hw = &rque->sc->hw; in igc_sysctl_interrupt_rate_handler()
2657 reg = IGC_READ_REG(hw, IGC_EITR(rque->msix)); in igc_sysctl_interrupt_rate_handler()
2667 if (error || !req->newptr) in igc_sysctl_interrupt_rate_handler()
2678 device_t dev = iflib_get_dev(sc->ctx); in igc_add_hw_stats()
2679 struct igc_tx_queue *tx_que = sc->tx_queues; in igc_add_hw_stats()
2680 struct igc_rx_queue *rx_que = sc->rx_queues; in igc_add_hw_stats()
2685 struct igc_hw_stats *stats = &sc->stats; in igc_add_hw_stats()
2695 CTLFLAG_RD, &sc->dropped_pkts, in igc_add_hw_stats()
2698 CTLFLAG_RD, &sc->link_irq, in igc_add_hw_stats()
2699 "Link MSI-X IRQ Handled"); in igc_add_hw_stats()
2701 CTLFLAG_RD, &sc->rx_overruns, in igc_add_hw_stats()
2704 CTLFLAG_RD, &sc->watchdog_events, in igc_add_hw_stats()
2715 CTLFLAG_RD, &sc->hw.fc.high_water, 0, in igc_add_hw_stats()
2716 "Flow Control High Watermark"); in igc_add_hw_stats()
2718 CTLFLAG_RD, &sc->hw.fc.low_water, 0, in igc_add_hw_stats()
2721 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { in igc_add_hw_stats()
2722 struct tx_ring *txr = &tx_que->txr; in igc_add_hw_stats()
2734 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU", in igc_add_hw_stats()
2738 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU", in igc_add_hw_stats()
2741 CTLFLAG_RD, &txr->tx_irq, in igc_add_hw_stats()
2742 "Queue MSI-X Transmit Interrupts"); in igc_add_hw_stats()
2745 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { in igc_add_hw_stats()
2746 struct rx_ring *rxr = &rx_que->rxr; in igc_add_hw_stats()
2758 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU", in igc_add_hw_stats()
2762 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU", in igc_add_hw_stats()
2765 CTLFLAG_RD, &rxr->rx_irq, in igc_add_hw_stats()
2766 "Queue MSI-X Receive Interrupts"); in igc_add_hw_stats()
2775 CTLFLAG_RD, &stats->ecol, in igc_add_hw_stats()
2778 CTLFLAG_RD, &stats->scc, in igc_add_hw_stats()
2781 CTLFLAG_RD, &stats->mcc, in igc_add_hw_stats()
2784 CTLFLAG_RD, &stats->latecol, in igc_add_hw_stats()
2787 CTLFLAG_RD, &stats->colc, in igc_add_hw_stats()
2790 CTLFLAG_RD, &sc->stats.symerrs, in igc_add_hw_stats()
2793 CTLFLAG_RD, &sc->stats.sec, in igc_add_hw_stats()
2796 CTLFLAG_RD, &sc->stats.dc, in igc_add_hw_stats()
2799 CTLFLAG_RD, &sc->stats.mpc, in igc_add_hw_stats()
2802 CTLFLAG_RD, &sc->stats.rlec, in igc_add_hw_stats()
2805 CTLFLAG_RD, &sc->stats.rnbc, in igc_add_hw_stats()
2808 CTLFLAG_RD, &sc->stats.ruc, in igc_add_hw_stats()
2811 CTLFLAG_RD, &sc->stats.rfc, in igc_add_hw_stats()
2814 CTLFLAG_RD, &sc->stats.roc, in igc_add_hw_stats()
2817 CTLFLAG_RD, &sc->stats.rjc, in igc_add_hw_stats()
2820 CTLFLAG_RD, &sc->stats.rxerrc, in igc_add_hw_stats()
2823 CTLFLAG_RD, &sc->stats.crcerrs, in igc_add_hw_stats()
2826 CTLFLAG_RD, &sc->stats.algnerrc, in igc_add_hw_stats()
2829 CTLFLAG_RD, &sc->stats.xonrxc, in igc_add_hw_stats()
2832 CTLFLAG_RD, &sc->stats.xontxc, in igc_add_hw_stats()
2835 CTLFLAG_RD, &sc->stats.xoffrxc, in igc_add_hw_stats()
2838 CTLFLAG_RD, &sc->stats.xofftxc, in igc_add_hw_stats()
2841 CTLFLAG_RD, &sc->stats.fcruc, in igc_add_hw_stats()
2844 CTLFLAG_RD, &sc->stats.mgprc, in igc_add_hw_stats()
2847 CTLFLAG_RD, &sc->stats.mgpdc, in igc_add_hw_stats()
2850 CTLFLAG_RD, &sc->stats.mgptc, in igc_add_hw_stats()
2855 CTLFLAG_RD, &sc->stats.tpr, in igc_add_hw_stats()
2858 CTLFLAG_RD, &sc->stats.gprc, in igc_add_hw_stats()
2861 CTLFLAG_RD, &sc->stats.bprc, in igc_add_hw_stats()
2864 CTLFLAG_RD, &sc->stats.mprc, in igc_add_hw_stats()
2867 CTLFLAG_RD, &sc->stats.prc64, in igc_add_hw_stats()
2870 CTLFLAG_RD, &sc->stats.prc127, in igc_add_hw_stats()
2871 "65-127 byte frames received"); in igc_add_hw_stats()
2873 CTLFLAG_RD, &sc->stats.prc255, in igc_add_hw_stats()
2874 "128-255 byte frames received"); in igc_add_hw_stats()
2876 CTLFLAG_RD, &sc->stats.prc511, in igc_add_hw_stats()
2877 "256-511 byte frames received"); in igc_add_hw_stats()
2879 CTLFLAG_RD, &sc->stats.prc1023, in igc_add_hw_stats()
2880 "512-1023 byte frames received"); in igc_add_hw_stats()
2882 CTLFLAG_RD, &sc->stats.prc1522, in igc_add_hw_stats()
2883 "1023-1522 byte frames received"); in igc_add_hw_stats()
2885 CTLFLAG_RD, &sc->stats.gorc, in igc_add_hw_stats()
2890 CTLFLAG_RD, &sc->stats.gotc, in igc_add_hw_stats()
2893 CTLFLAG_RD, &sc->stats.tpt, in igc_add_hw_stats()
2896 CTLFLAG_RD, &sc->stats.gptc, in igc_add_hw_stats()
2899 CTLFLAG_RD, &sc->stats.bptc, in igc_add_hw_stats()
2902 CTLFLAG_RD, &sc->stats.mptc, in igc_add_hw_stats()
2905 CTLFLAG_RD, &sc->stats.ptc64, in igc_add_hw_stats()
2908 CTLFLAG_RD, &sc->stats.ptc127, in igc_add_hw_stats()
2909 "65-127 byte frames transmitted"); in igc_add_hw_stats()
2911 CTLFLAG_RD, &sc->stats.ptc255, in igc_add_hw_stats()
2912 "128-255 byte frames transmitted"); in igc_add_hw_stats()
2914 CTLFLAG_RD, &sc->stats.ptc511, in igc_add_hw_stats()
2915 "256-511 byte frames transmitted"); in igc_add_hw_stats()
2917 CTLFLAG_RD, &sc->stats.ptc1023, in igc_add_hw_stats()
2918 "512-1023 byte frames transmitted"); in igc_add_hw_stats()
2920 CTLFLAG_RD, &sc->stats.ptc1522, in igc_add_hw_stats()
2921 "1024-1522 byte frames transmitted"); in igc_add_hw_stats()
2923 CTLFLAG_RD, &sc->stats.tsctc, in igc_add_hw_stats()
2932 CTLFLAG_RD, &sc->stats.iac, in igc_add_hw_stats()
2936 CTLFLAG_RD, &sc->stats.rxdmtc, in igc_add_hw_stats()
2943 struct igc_hw *hw = &sc->hw; in igc_fw_version()
2944 struct igc_fw_version *fw_ver = &sc->fw_ver; in igc_fw_version()
2956 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { in igc_sbuf_fw_version()
2957 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, in igc_sbuf_fw_version()
2958 fw_ver->eep_minor, fw_ver->eep_build); in igc_sbuf_fw_version()
2962 if (fw_ver->invm_major || fw_ver->invm_minor || in igc_sbuf_fw_version()
2963 fw_ver->invm_img_type) { in igc_sbuf_fw_version()
2965 space, fw_ver->invm_major, fw_ver->invm_minor, in igc_sbuf_fw_version()
2966 fw_ver->invm_img_type); in igc_sbuf_fw_version()
2970 if (fw_ver->or_valid) { in igc_sbuf_fw_version()
2971 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", in igc_sbuf_fw_version()
2972 space, fw_ver->or_major, fw_ver->or_build, in igc_sbuf_fw_version()
2973 fw_ver->or_patch); in igc_sbuf_fw_version()
2977 if (fw_ver->etrack_id) in igc_sbuf_fw_version()
2978 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); in igc_sbuf_fw_version()
2984 device_t dev = sc->dev; in igc_print_fw_version()
2994 igc_sbuf_fw_version(&sc->fw_ver, buf); in igc_print_fw_version()
3009 device_t dev = sc->dev; in igc_sysctl_print_fw_version()
3019 igc_sbuf_fw_version(&sc->fw_ver, buf); in igc_sysctl_print_fw_version()
3044 result = -1; in igc_sysctl_nvm_info()
3047 if (error || !req->newptr) in igc_sysctl_nvm_info()
3052 * first 32 16-bit words of the EEPROM to in igc_sysctl_nvm_info()
3075 igc_read_nvm(&sc->hw, i, 1, &eeprom_data); in igc_print_nvm_info()
3088 sc = oidp->oid_arg1; in igc_sysctl_tso_tcp_flags_mask()
3089 switch (oidp->oid_arg2) { in igc_sysctl_tso_tcp_flags_mask()
3106 val = IGC_READ_REG(&sc->hw, reg); in igc_sysctl_tso_tcp_flags_mask()
3109 if (error != 0 || req->newptr == NULL) in igc_sysctl_tso_tcp_flags_mask()
3114 IGC_WRITE_REG(&sc->hw, reg, val); in igc_sysctl_tso_tcp_flags_mask()
3121 * 0 - off
3122 * 1 - rx pause
3123 * 2 - tx pause
3124 * 3 - full
3135 if ((error) || (req->newptr == NULL)) in igc_set_flowcntl()
3138 if (input == sc->fc) /* no change? */ in igc_set_flowcntl()
3146 sc->hw.fc.requested_mode = input; in igc_set_flowcntl()
3147 sc->fc = input; in igc_set_flowcntl()
3154 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; in igc_set_flowcntl()
3155 igc_force_mac_fc(&sc->hw); in igc_set_flowcntl()
3162 * 0/1 - off/on
3164 * 250,500,1000-10000 in thousands
3172 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); in igc_sysctl_dmac()
3174 if ((error) || (req->newptr == NULL)) in igc_sysctl_dmac()
3177 switch (sc->dmac) { in igc_sysctl_dmac()
3182 sc->dmac = 1000; in igc_sysctl_dmac()
3196 /* Legal values - allow */ in igc_sysctl_dmac()
3200 sc->dmac = 0; in igc_sysctl_dmac()
3204 igc_if_init(sc->ctx); in igc_sysctl_dmac()
3211 * 0/1 - enabled/disabled
3219 value = sc->hw.dev_spec._i225.eee_disable; in igc_sysctl_eee()
3221 if (error || req->newptr == NULL) in igc_sysctl_eee()
3224 sc->hw.dev_spec._i225.eee_disable = (value != 0); in igc_sysctl_eee()
3225 igc_if_init(sc->ctx); in igc_sysctl_eee()
3237 result = -1; in igc_sysctl_debug_info()
3240 if (error || !req->newptr) in igc_sysctl_debug_info()
3261 if (error || !req->newptr || result != 1) in igc_get_rs()
3276 * needed for debugging a problem. -jfv
3281 device_t dev = iflib_get_dev(sc->ctx); in igc_print_debug_info()
3282 if_t ifp = iflib_get_ifp(sc->ctx); in igc_print_debug_info()
3283 struct tx_ring *txr = &sc->tx_queues->txr; in igc_print_debug_info()
3284 struct rx_ring *rxr = &sc->rx_queues->rxr; in igc_print_debug_info()
3294 printf("and ACTIVE\n"); in igc_print_debug_info()
3296 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { in igc_print_debug_info()
3297 device_printf(dev, "TX Queue %d ------\n", i); in igc_print_debug_info()
3299 IGC_READ_REG(&sc->hw, IGC_TDH(i)), in igc_print_debug_info()
3300 IGC_READ_REG(&sc->hw, IGC_TDT(i))); in igc_print_debug_info()
3303 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { in igc_print_debug_info()
3304 device_printf(dev, "RX Queue %d ------\n", j); in igc_print_debug_info()
3306 IGC_READ_REG(&sc->hw, IGC_RDH(j)), in igc_print_debug_info()
3307 IGC_READ_REG(&sc->hw, IGC_RDT(j))); in igc_print_debug_info()