| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | sifive,plic-1.0.0.yaml | 5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
26 with priority below this threshold will not cause the PLIC to raise its
29 The PLIC supports both edge-triggered and level-triggered interrupts. For
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31 seen while an interrupt handler is active; the PLIC may either queue them or
36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
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| H A D | riscv,cpu-intc.yaml | 23 (PLIC).
28 tree entry, though external interrupt controllers (like the PLIC, for
30 This means a PLIC interrupt property will typically list the HLICs for all
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| H A D | sophgo,sg2042-msi.yaml | 14 PCIe MSI to PLIC interrupts.
62 msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>;
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| H A D | starfive,jh8100-intc.yaml | 12 interrupt signal to RISC-V PLIC.
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| H A D | andestech,plicsw.yaml | 10 In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
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| /linux/arch/riscv/boot/dts/microchip/ |
| H A D | mpfs.dtsi | 217 interrupt-parent = <&plic>;
231 plic: interrupt-controller@c000000 { label
232 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
248 interrupt-parent = <&plic>;
299 interrupt-parent = <&plic>;
311 interrupt-parent = <&plic>;
323 interrupt-parent = <&plic>;
335 interrupt-parent = <&plic>;
347 interrupt-parent = <&plic>;
358 interrupt-parent = <&plic>;
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| H A D | mpfs-icicle-kit-fabric.dtsi | 23 interrupt-parent = <&plic>;
39 interrupt-parent = <&plic>;
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| H A D | mpfs-polarberry-fabric.dtsi | 27 interrupt-parent = <&plic>;
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| H A D | mpfs-m100pfs-fabric.dtsi | 27 interrupt-parent = <&plic>;
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| /linux/arch/riscv/boot/dts/sophgo/ |
| H A D | cv1800b.dtsi | 21 interrupt-parent = <&plic>;
38 plic: interrupt-controller@70000000 { label
39 compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
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| H A D | sg2002.dtsi | 23 interrupt-parent = <&plic>;
40 plic: interrupt-controller@70000000 { label
41 compatible = "sophgo,sg2002-plic", "thead,c900-plic";
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| H A D | cv1812h.dtsi | 23 interrupt-parent = <&plic>;
40 plic: interrupt-controller@70000000 { label
41 compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
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| /linux/drivers/irqchip/ |
| H A D | irq-sifive-plic.c | 6 #define pr_fmt(fmt) "riscv-plic: " fmt
25 * This driver implements a version of the RISC-V PLIC with the actual layout
30 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
194 .name = "SiFive PLIC",
209 .name = "SiFive PLIC",
427 { .compatible = "sifive,plic-1.0.0" },
431 { .compatible = "thead,c900-plic",
460 pr_err("%pfwP: no PLIC context available\n", fwnode); in plic_parse_nr_irqs_and_contexts()
475 pr_err("%pfwP: no PLIC context available\n", fwnode); in plic_parse_nr_irqs_and_contexts()
650 * We can have multiple PLIC instances so setup global state in plic_probe()
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| /linux/arch/riscv/boot/dts/allwinner/ |
| H A D | sun20i-d1s.dtsi | 57 interrupt-parent = <&plic>;
67 plic: interrupt-controller@10000000 { label
68 compatible = "allwinner,sun20i-d1-plic",
69 "thead,c900-plic";
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| /linux/drivers/acpi/riscv/ |
| H A D | irq.c | 43 * the incremental order like RINTC(24)->IMSIC(25)->APLIC(26)->PLIC(27).
170 struct acpi_madt_plic *plic = (struct acpi_madt_plic *)header; in riscv_acpi_plic_parse_madt() local
172 return riscv_acpi_register_ext_intc(plic->gsi_base, plic->num_irqs, 0, in riscv_acpi_plic_parse_madt()
173 plic->id, ACPI_RISCV_IRQCHIP_PLIC); in riscv_acpi_plic_parse_madt()
178 /* There can be either PLIC or APLIC */ in riscv_acpi_init_gsi_mapping()
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| /linux/arch/riscv/boot/dts/renesas/ |
| H A D | r9a07g043f.dtsi | 55 interrupt-parent = <&plic>;
132 plic: interrupt-controller@12c00000 { label
133 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
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| /linux/arch/riscv/boot/dts/andes/ |
| H A D | qilai.dtsi | 126 interrupt-parent = <&plic>;
161 plic: interrupt-controller@2000000 { label
162 compatible = "andestech,qilai-plic",
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| /linux/arch/riscv/boot/dts/thead/ |
| H A D | th1520.dtsi | 245 interrupt-parent = <&plic>;
251 plic: interrupt-controller@ffd8000000 { label
252 compatible = "thead,th1520-plic", "thead,c900-plic";
639 interrupt-parent = <&plic>;
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | spacemit,sdhci.yaml | 50 interrupt-parent = <&plic>;
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| /linux/arch/riscv/boot/dts/spacemit/ |
| H A D | k1.dtsi | 343 interrupt-parent = <&plic>;
381 interrupt-parent = <&plic>;
610 plic: interrupt-controller@e0000000 { label
611 compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
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| /linux/arch/m68k/include/asm/ |
| H A D | m5272sim.h | 110 #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
111 #define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | microchip,mpfs-spi.yaml | 83 interrupt-parent = <&plic>;
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| /linux/arch/powerpc/include/asm/ |
| H A D | paca.h | 5 * There are some pointers defined that are utilized by PLIC.
70 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
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| /linux/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/ |
| H A D | microarch.json | 62 "BriefDescription": "PLIC arbitration time when the interrupt is not responded",
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| /linux/Documentation/devicetree/bindings/pwm/ |
| H A D | pwm-sifive.yaml | 69 interrupt-parent = <&plic>;
|