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/linux/Documentation/devicetree/bindings/virtio/
H A Dpci-iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: virtio-iommu device using the virtio-pci transport
10 - Jean-Philippe Brucker <jean-philippe@linaro.org>
13 When virtio-iommu uses the PCI transport, its programming interface is
14 discovered dynamically by the PCI probing infrastructure. However the
15 device tree statically describes the relation between IOMMU and DMA
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
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/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <tjeznach@rivosinc.com>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
17 It supports identical translation table format to the RISC-V address
19 Hardware uses in-memory command and fault reporting queues with wired
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H A Diommu.txt5 IOMMU device node:
8 An IOMMU can provide the following services:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
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/linux/drivers/acpi/
H A Dviot.c1 // SPDX-License-Identifier: GPL-2.0
6 * para-virtual IOMMUs and the endpoints they manage. The OS uses it to
8 * before their IOMMU is ready.
12 * VIOT driver looks for an IOMMU associated to the device in the VIOT table.
13 * If an IOMMU exists and has been initialized, the VIOT driver initializes the
14 * device's IOMMU fwspec, allowing the DMA infrastructure to invoke the IOMMU
15 * ops when the device driver configures DMA mappings. If an IOMMU exists and
16 * hasn't yet been initialized, VIOT returns -EPROBE_DEFER to postpone probing
17 * the device until the IOMMU is available.
22 #include <linux/iommu.h>
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/linux/Documentation/devicetree/bindings/pci/
H A Dpci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/pci-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCI Endpoint Controller
10 Common properties for PCI Endpoint Controller Nodes.
13 - Kishon Vijay Abraham I <kishon@kernel.org>
14 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 pattern: "^pcie-ep@"
20 iommu-map:
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H A Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
25 used to take the PCI devices on those ports out of reset. Therefore
26 the standard "reset-gpios" and "max-link-speed" properties appear on
27 the child nodes that represent the PCI bridges that correspond to
38 - items:
39 - enum:
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/linux/arch/sparc/kernel/
H A Dpsycho_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* psycho_common.c: Code common to PSYCHO and derivative PCI controllers.
39 struct strbuf *strbuf = &pbm->stc; in psycho_check_stc_error()
43 if (!strbuf->strbuf_control) in psycho_check_stc_error()
46 err_base = strbuf->strbuf_err_stat; in psycho_check_stc_error()
47 tag_base = strbuf->strbuf_tag_diag; in psycho_check_stc_error()
48 line_base = strbuf->strbuf_line_diag; in psycho_check_stc_error()
55 * before re-enabling the streaming buffer. If any dirty data in psycho_check_stc_error()
60 control = upa_readq(strbuf->strbuf_control); in psycho_check_stc_error()
61 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); in psycho_check_stc_error()
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H A Dpci_impl.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* pci_impl.h: Helper definitions for PCI controller support.
12 #include <linux/pci.h>
16 #include <asm/iommu.h>
18 /* The abstraction used here is that there are PCI controllers,
19 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
20 * underneath. Each PCI bus module uses an IOMMU (shared by both
21 * PBMs of a controller, or per-PBM), and if a streaming buffer
22 * is present, each PCI bus module has its own. (ie. the IOMMU
24 * Furthermore, each PCI bus module controls its own autonomous
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H A Dpci_schizo.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
9 #include <linux/pci.h>
20 #include <asm/iommu.h>
49 /* IOMMU control register. */
56 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
57 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
58 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
59 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
60 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
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H A Dpci_psycho.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
11 #include <linux/pci.h>
20 #include <asm/iommu.h>
33 /* Misc. PSYCHO PCI controller register offsets and definitions. */
49 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
51 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
55 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
57 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
61 /* Helper function of IOMMU error checking, which checks out
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H A Dpci_sabre.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_sabre.c: Sabre specific PCI controller support.
11 #include <linux/pci.h>
22 #include <asm/iommu.h>
34 /* SABRE PCI controller register offsets and definitions. */
36 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
37 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
38 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
39 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
47 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
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H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci.c: UltraSparc PCI controller support.
8 * OF tree based PCI bus probing taken from the PowerPC port
18 #include <linux/pci.h>
35 /* List of all PCI controllers found in the system. */
42 volatile int pci_poke_cpu = -1;
63 pci_poke_cpu = -1; in pci_config_read8()
85 pci_poke_cpu = -1; in pci_config_read16()
107 pci_poke_cpu = -1; in pci_config_read32()
128 pci_poke_cpu = -1; in pci_config_write8()
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H A Dpci_fire.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_fire.c: Sun4u platform PCI-E controller support.
7 #include <linux/pci.h>
33 struct iommu *iommu = pbm->iommu; in pci_fire_pbm_iommu_init() local
38 /* No virtual-dma property on these guys, use largest size. */ in pci_fire_pbm_iommu_init()
45 iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL; in pci_fire_pbm_iommu_init()
46 iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE; in pci_fire_pbm_iommu_init()
47 iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH; in pci_fire_pbm_iommu_init()
48 iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV; in pci_fire_pbm_iommu_init()
53 iommu->write_complete_reg = pbm->controller_regs + 0x410000UL; in pci_fire_pbm_iommu_init()
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/linux/drivers/iommu/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
15 bool "IOMMU Hardware Support"
26 menu "Generic IOMMU Pagetable Support"
40 sizes at both stage-1 and stage-2, as well as address spaces
41 up to 48-bits in size.
47 Enable self-tests for LPAE page table allocator. This performs
48 a series of page-table consistency checks during boot.
57 Enable support for the ARM Short-descriptor pagetable format.
58 This supports 32-bit virtual and physical addresses mapped using
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/linux/drivers/iommu/intel/
H A Dirq_remapping.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
11 #include <linux/pci.h>
13 #include <linux/irqchip/irq-msi-lib.h>
22 #include <asm/pci-direct.h>
25 #include "iommu.h"
27 #include "../iommu-pages.h"
30 struct intel_iommu *iommu; member
32 unsigned int bus; /* PCI bus number */
33 unsigned int devfn; /* PCI devfn number */
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H A Dsvm.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/pci.h>
14 #include <linux/pci-ats.h>
22 #include "iommu.h"
25 #include "../iommu-pages.h"
28 void intel_svm_check(struct intel_iommu *iommu) in intel_svm_check() argument
30 if (!pasid_supported(iommu)) in intel_svm_check()
34 !cap_fl1gp_support(iommu->cap)) { in intel_svm_check()
36 iommu->name); in intel_svm_check()
41 !cap_fl5lp_support(iommu->cap)) { in intel_svm_check()
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H A Dnested.c1 // SPDX-License-Identifier: GPL-2.0
3 * nested.c - nested mode translation support
14 #include <linux/iommu.h>
15 #include <linux/pci.h>
16 #include <linux/pci-ats.h>
18 #include "iommu.h"
26 struct intel_iommu *iommu = info->iommu; in intel_nested_attach_dev() local
32 if (iommu->agaw < dmar_domain->s2_domain->agaw) { in intel_nested_attach_dev()
34 return -ENODEV; in intel_nested_attach_dev()
38 * Stage-1 domain cannot work alone, it is nested on a s2_domain. in intel_nested_attach_dev()
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/linux/arch/arm64/boot/dts/arm/
H A Dmorello-sdp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
6 /dts-v1/;
11 compatible = "arm,morello-sdp", "arm,morello";
18 stdout-path = "serial0:115200n8";
21 dpu_aclk: clock-350000000 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <350000000>;
26 clock-output-names = "aclk";
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/linux/arch/powerpc/boot/dts/fsl/
H A Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp3041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp2041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp5040si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp4080si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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/linux/Documentation/arch/x86/
H A Diommu.rst2 x86 IOMMU Support
7 - Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-dire…
8 - AMD: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_…
13 -----------
16 device scope relationships between devices and which IOMMU controls
21 - DMAR - Intel DMA Remapping table
22 - DRHD - Intel DMA Remapping Hardware Unit Definition
23 - RMRR - Intel Reserved Memory Region Reporting Structure
24 - IVRS - AMD I/O Virtualization Reporting Structure
25 - IVDB - AMD I/O Virtualization Definition Block
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/linux/drivers/iommu/amd/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # AMD IOMMU support
4 bool "AMD IOMMU support"
18 depends on X86_64 && PCI && ACPI && HAVE_CMPXCHG_DOUBLE
20 With this option you can enable support for AMD IOMMU hardware in
21 your system. An IOMMU is a hardware component which provides
22 remapping of DMA memory accesses from devices. With an AMD IOMMU you
26 You can find out if your system has an AMD IOMMU if you look into
31 bool "Enable AMD IOMMU internals in DebugFS"
36 DO NOT ENABLE THIS OPTION UNLESS YOU REALLY, -REALLY- KNOW WHAT YOU ARE DOING!!!
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