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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-t.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 #include "rk3399-base.dtsi"
10 cluster0_opp: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
15 opp-hz = /bits/ 64 <408000000>;
16 opp-microvolt = <875000 875000 1250000>;
17 clock-latency-ns = <40000>;
20 opp-hz = /bits/ 64 <600000000>;
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H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include "rk3399-base.dtsi"
9 cluster0_opp: opp-table-0 {
10 compatible = "operating-points-v2";
11 opp-shared;
14 opp-hz = /bits/ 64 <408000000>;
15 opp-microvolt = <825000 825000 1250000>;
16 clock-latency-ns = <40000>;
19 opp-hz = /bits/ 64 <600000000>;
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H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
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/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-qcom-level.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm OPP
10 - Niklas Cassel <nks@flawful.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2-qcom-level
20 '^opp-?[0-9]+$':
25 opp-level: true
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H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. NVMEM OPP
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
23 the OPP framework with required information (existing HW bitmap).
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H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points)
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
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H A Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points) Common Properties
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
25 pattern: '^opp-table(-[a-z0-9]+)?$'
27 opp-shared:
29 Indicates that device nodes using this OPP Table Node's phandle switch
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/linux/Documentation/devicetree/bindings/power/avs/
H A Dqcom,cpr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <nks@flawful.org>
14 or other device. Each OPP of a device corresponds to a "corner" that has
23 - enum:
24 - qcom,qcs404-cpr
25 - const: qcom,cpr
28 description: Base address and size of the RBCPR register region.
36 - description: Reference clock.
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/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cells = <0>;
19 d-cache-block-size = <64>;
20 d-cache-sets = <256>;
21 d-cache-size = <32768>;
22 i-cache-block-size = <64>;
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/linux/drivers/clk/qcom/
H A Da53-pll.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
18 #include "clk-regmap.h"
67 struct dev_pm_opp *opp; in qcom_a53pll_get_freq_tbl() local
69 opp = dev_pm_opp_find_freq_ceil(dev, &freq); in qcom_a53pll_get_freq_tbl()
70 if (IS_ERR(opp)) in qcom_a53pll_get_freq_tbl()
81 dev_pm_opp_put(opp); in qcom_a53pll_get_freq_tbl()
89 struct device *dev = &pdev->dev; in qcom_a53pll_probe()
90 struct device_node *np = dev->of_node; in qcom_a53pll_probe()
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/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dimx8m-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
18 switching is implemented by TF-A code which runs from a SRAM area.
22 capabilities through standard Linux mechanism like devfreq and OPP tables.
27 - enum:
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
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/linux/drivers/opp/
H A Dti-opp-supply.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
5 * Dave Gerlach <d-gerlach@ti.com>
7 * TI OPP supply driver that provides override into the regulator control
8 * for generic opp core to handle devices with ABB regulator and/or
26 * struct ti_opp_supply_optimum_voltage_table - optimized voltage table
36 * struct ti_opp_supply_data - OMAP specific opp supply data
40 * @old_supplies: Placeholder for supplies information for old OPP.
41 * @new_supplies: Placeholder for supplies information for new OPP.
54 * struct ti_opp_supply_of_data - device tree match data
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/linux/Documentation/devicetree/bindings/power/
H A Dpower-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafael J. Wysocki <rafael@kernel.org>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
25 \#power-domain-cells property in the PM domain provider node.
29 pattern: "^(power-controller|power-domain|performance-domain)([@-].*)?$"
31 domain-idle-states:
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/linux/arch/arm64/boot/dts/qcom/
H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
8 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
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/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779f0.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
19 opp-shared;
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
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/linux/drivers/nvmem/
H A Dmtk-efuse.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
11 #include <linux/nvmem-provider.h>
20 void __iomem *base; member
27 void __iomem *addr = priv->base + reg; in mtk_reg_read()
51 size_t sz = strlen(cell->name); in mtk_efuse_fixup_dt_cell_info()
55 * a number with range [0-7] (max 3 bits): post process to use in mtk_efuse_fixup_dt_cell_info()
56 * it in OPP tables to describe supported-hw. in mtk_efuse_fixup_dt_cell_info()
58 if (cell->nbits <= 3 && in mtk_efuse_fixup_dt_cell_info()
59 strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0) in mtk_efuse_fixup_dt_cell_info()
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/linux/drivers/pmdomain/qcom/
H A Dcpr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
27 #include <linux/nvmem-consumer.h>
29 /* Register Offsets for RB-CPR and Bit Definitions */
125 #define FUSE_REVISION_UNKNOWN (-1)
233 void __iomem *base; member
254 return !drv->loop_disabled; in cpr_is_allowed()
259 writel_relaxed(value, drv->base + offset); in cpr_write()
264 return readl_relaxed(drv->base + offset); in cpr_read()
272 val = readl_relaxed(drv->base + offset); in cpr_masked_write()
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/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
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/linux/drivers/pci/controller/dwc/
H A Dpcie-qcom.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
26 #include <linux/pci-ecam.h>
39 #include "../pci-host-common.h"
40 #include "pcie-designware.h"
41 #include "pcie-qcom-common.h"
271 * struct qcom_pcie_cfg - Per SoC config struct
304 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
311 list_for_each_entry(port, &pcie->ports, list) in qcom_perst_assert()
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/linux/drivers/mfd/
H A Ddb8500-prcmu.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) ST-Ericsson SA 2010
35 #include <linux/mfd/dbx500-prcmu.h>
37 #include <linux/regulator/db8500-prcmu.h>
39 #include "db8500-prcmu-regs.h"
227 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
332 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
347 * mb0_transfer - state needed for mailbox 0 communication.
368 * mb1_transfer - state needed for mailbox 1 communication.
371 * @ape_opp: The current APE OPP.
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/linux/drivers/regulator/
H A Dti-abb-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2012-2013 Texas Instruments, Inc.
26 * FAST_OPP: sets ABB LDO to Forward Body-Bias
27 * SLOW_OPP: sets ABB LDO to Reverse Body-Bias
34 * struct ti_abb_info - ABB information per voltage setting
47 * struct ti_abb_reg - Register description for ABB block
48 * @setup_off: setup register offset from base
49 * @control_off: control register offset from base
50 * @sr2_wtcnt_value_mask: setup register- sr2_wtcnt_value mask
51 * @fbb_sel_mask: setup register- FBB sel mask
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/linux/drivers/tty/serial/
H A Dqcom_geni_serial.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
21 #include <linux/soc/qcom/geni-se.h>
27 #include <dt-bindings/interconnect/qcom,icc.h>
175 * qcom_geni_set_rs485_mode - Set RTS pin state for RS485 mode
184 if (!(uport->rs485.flags & SER_RS485_ENABLED)) in qcom_geni_set_rs485_mode()
189 if (uport->rs485.flags & flag) in qcom_geni_set_rs485_mode()
194 writel(rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_set_rs485_mode()
199 struct platform_device *pdev = to_platform_device(uport->dev); in qcom_geni_serial_request_port()
202 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
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/linux/drivers/ufs/core/
H A Dufshcd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
17 #include <linux/blk-pm.h>
31 #include "ufshcd-priv.h"
34 #include "ufs-sysfs.h"
35 #include "ufs-debugfs.h"
36 #include "ufs-fault-injection.h"
38 #include "ufshcd-crypto.h"
76 /* maximum number of link-startup retries */
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