Lines Matching +full:opp +full:- +full:v2 +full:- +full:base
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cells = <0>;
19 d-cache-block-size = <64>;
20 d-cache-sets = <256>;
21 d-cache-size = <32768>;
22 i-cache-block-size = <64>;
23 i-cache-sets = <128>;
24 i-cache-size = <32768>;
25 mmu-type = "riscv,sv39";
26 operating-points-v2 = <&opp_table_cpu>;
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
31 #cooling-cells = <2>;
33 cpu0_intc: interrupt-controller {
34 compatible = "riscv,cpu-intc";
35 interrupt-controller;
36 #interrupt-cells = <1>;
41 opp_table_cpu: opp-table-cpu {
42 compatible = "operating-points-v2";
44 opp-408000000 {
45 opp-hz = /bits/ 64 <408000000>;
46 opp-microvolt = <900000 900000 1100000>;
49 opp-1080000000 {
50 opp-hz = /bits/ 64 <1008000000>;
51 opp-microvolt = <900000 900000 1100000>;
56 interrupt-parent = <&plic>;
59 compatible = "allwinner,sun20i-d1-wdt";
63 clock-names = "hosc", "losc";
66 plic: interrupt-controller@10000000 {
67 compatible = "allwinner,sun20i-d1-plic",
68 "thead,c900-plic";
70 interrupts-extended = <&cpu0_intc 11>,
72 interrupt-controller;
74 #address-cells = <0>;
75 #interrupt-cells = <2>;
81 riscv,event-to-mhpmcounters =
92 riscv,event-to-mhpmevent =
103 riscv,raw-event-to-mhpmcounters =