Lines Matching +full:opp +full:- +full:v2 +full:- +full:base
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sc7280.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/mailbox/qcom-ipcc.h>
23 #include <dt-bindings/phy/phy-qcom-qmp.h>
24 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/sound/qcom,lpass.h>
30 #include <dt-bindings/thermal/thermal.h>
33 interrupt-parent = <&intc>;
35 #address-cells = <2>;
36 #size-cells = <2>;
78 xo_board: xo-board {
79 compatible = "fixed-clock";
80 clock-frequency = <76800000>;
81 #clock-cells = <0>;
84 sleep_clk: sleep-clk {
85 compatible = "fixed-clock";
86 clock-frequency = <32000>;
87 #clock-cells = <0>;
91 reserved-memory {
92 #address-cells = <2>;
93 #size-cells = <2>;
96 wlan_ce_mem: wlan-ce@4cd000 {
97 no-map;
103 no-map;
108 no-map;
113 no-map;
116 aop_cmd_db_mem: aop-cmd-db@80860000 {
118 compatible = "qcom,cmd-db";
119 no-map;
122 reserved_xbl_uefi_log: xbl-uefi-res@80880000 {
124 no-map;
127 sec_apps_mem: sec-apps@808ff000 {
129 no-map;
134 no-map;
138 no-map;
142 wlan_fw_mem: wlan-fw@80c00000 {
144 no-map;
149 no-map;
154 no-map;
159 no-map;
162 ipa_fw_mem: ipa-fw@8b700000 {
164 no-map;
169 no-map;
174 no-map;
179 no-map;
183 compatible = "qcom,rmtfs-mem";
185 no-map;
187 qcom,client-id = <1>;
193 #address-cells = <2>;
194 #size-cells = <0>;
201 enable-method = "psci";
202 power-domains = <&CPU_PD0>;
203 power-domain-names = "psci";
204 next-level-cache = <&L2_0>;
205 operating-points-v2 = <&cpu0_opp_table>;
206 capacity-dmips-mhz = <1024>;
207 dynamic-power-coefficient = <100>;
210 qcom,freq-domain = <&cpufreq_hw 0>;
211 #cooling-cells = <2>;
212 L2_0: l2-cache {
214 cache-level = <2>;
215 cache-unified;
216 next-level-cache = <&L3_0>;
217 L3_0: l3-cache {
219 cache-level = <3>;
220 cache-unified;
230 enable-method = "psci";
231 power-domains = <&CPU_PD1>;
232 power-domain-names = "psci";
233 next-level-cache = <&L2_100>;
234 operating-points-v2 = <&cpu0_opp_table>;
235 capacity-dmips-mhz = <1024>;
236 dynamic-power-coefficient = <100>;
239 qcom,freq-domain = <&cpufreq_hw 0>;
240 #cooling-cells = <2>;
241 L2_100: l2-cache {
243 cache-level = <2>;
244 cache-unified;
245 next-level-cache = <&L3_0>;
254 enable-method = "psci";
255 power-domains = <&CPU_PD2>;
256 power-domain-names = "psci";
257 next-level-cache = <&L2_200>;
258 operating-points-v2 = <&cpu0_opp_table>;
259 capacity-dmips-mhz = <1024>;
260 dynamic-power-coefficient = <100>;
263 qcom,freq-domain = <&cpufreq_hw 0>;
264 #cooling-cells = <2>;
265 L2_200: l2-cache {
267 cache-level = <2>;
268 cache-unified;
269 next-level-cache = <&L3_0>;
278 enable-method = "psci";
279 power-domains = <&CPU_PD3>;
280 power-domain-names = "psci";
281 next-level-cache = <&L2_300>;
282 operating-points-v2 = <&cpu0_opp_table>;
283 capacity-dmips-mhz = <1024>;
284 dynamic-power-coefficient = <100>;
287 qcom,freq-domain = <&cpufreq_hw 0>;
288 #cooling-cells = <2>;
289 L2_300: l2-cache {
291 cache-level = <2>;
292 cache-unified;
293 next-level-cache = <&L3_0>;
302 enable-method = "psci";
303 power-domains = <&CPU_PD4>;
304 power-domain-names = "psci";
305 next-level-cache = <&L2_400>;
306 operating-points-v2 = <&cpu4_opp_table>;
307 capacity-dmips-mhz = <1946>;
308 dynamic-power-coefficient = <520>;
311 qcom,freq-domain = <&cpufreq_hw 1>;
312 #cooling-cells = <2>;
313 L2_400: l2-cache {
315 cache-level = <2>;
316 cache-unified;
317 next-level-cache = <&L3_0>;
326 enable-method = "psci";
327 power-domains = <&CPU_PD5>;
328 power-domain-names = "psci";
329 next-level-cache = <&L2_500>;
330 operating-points-v2 = <&cpu4_opp_table>;
331 capacity-dmips-mhz = <1946>;
332 dynamic-power-coefficient = <520>;
335 qcom,freq-domain = <&cpufreq_hw 1>;
336 #cooling-cells = <2>;
337 L2_500: l2-cache {
339 cache-level = <2>;
340 cache-unified;
341 next-level-cache = <&L3_0>;
350 enable-method = "psci";
351 power-domains = <&CPU_PD6>;
352 power-domain-names = "psci";
353 next-level-cache = <&L2_600>;
354 operating-points-v2 = <&cpu4_opp_table>;
355 capacity-dmips-mhz = <1946>;
356 dynamic-power-coefficient = <520>;
359 qcom,freq-domain = <&cpufreq_hw 1>;
360 #cooling-cells = <2>;
361 L2_600: l2-cache {
363 cache-level = <2>;
364 cache-unified;
365 next-level-cache = <&L3_0>;
374 enable-method = "psci";
375 power-domains = <&CPU_PD7>;
376 power-domain-names = "psci";
377 next-level-cache = <&L2_700>;
378 operating-points-v2 = <&cpu7_opp_table>;
379 capacity-dmips-mhz = <1985>;
380 dynamic-power-coefficient = <552>;
383 qcom,freq-domain = <&cpufreq_hw 2>;
384 #cooling-cells = <2>;
385 L2_700: l2-cache {
387 cache-level = <2>;
388 cache-unified;
389 next-level-cache = <&L3_0>;
393 cpu-map {
429 idle-states {
430 entry-method = "psci";
432 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
433 compatible = "arm,idle-state";
434 idle-state-name = "little-power-down";
435 arm,psci-suspend-param = <0x40000003>;
436 entry-latency-us = <549>;
437 exit-latency-us = <901>;
438 min-residency-us = <1774>;
439 local-timer-stop;
442 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
443 compatible = "arm,idle-state";
444 idle-state-name = "little-rail-power-down";
445 arm,psci-suspend-param = <0x40000004>;
446 entry-latency-us = <702>;
447 exit-latency-us = <915>;
448 min-residency-us = <4001>;
449 local-timer-stop;
452 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
453 compatible = "arm,idle-state";
454 idle-state-name = "big-power-down";
455 arm,psci-suspend-param = <0x40000003>;
456 entry-latency-us = <523>;
457 exit-latency-us = <1244>;
458 min-residency-us = <2207>;
459 local-timer-stop;
462 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
463 compatible = "arm,idle-state";
464 idle-state-name = "big-rail-power-down";
465 arm,psci-suspend-param = <0x40000004>;
466 entry-latency-us = <526>;
467 exit-latency-us = <1854>;
468 min-residency-us = <5555>;
469 local-timer-stop;
473 domain_idle_states: domain-idle-states {
474 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
475 compatible = "domain-idle-state";
476 arm,psci-suspend-param = <0x41000044>;
477 entry-latency-us = <2752>;
478 exit-latency-us = <3048>;
479 min-residency-us = <6118>;
482 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
483 compatible = "domain-idle-state";
484 arm,psci-suspend-param = <0x41001344>;
485 entry-latency-us = <3263>;
486 exit-latency-us = <4562>;
487 min-residency-us = <8467>;
490 CLUSTER_SLEEP_LLCC_OFF: cluster-sleep-2 {
491 compatible = "domain-idle-state";
492 arm,psci-suspend-param = <0x4100b344>;
493 entry-latency-us = <3638>;
494 exit-latency-us = <6562>;
495 min-residency-us = <9826>;
500 cpu0_opp_table: opp-table-cpu0 {
501 compatible = "operating-points-v2";
502 opp-shared;
504 cpu0_opp_300mhz: opp-300000000 {
505 opp-hz = /bits/ 64 <300000000>;
506 opp-peak-kBps = <800000 9600000>;
509 cpu0_opp_691mhz: opp-691200000 {
510 opp-hz = /bits/ 64 <691200000>;
511 opp-peak-kBps = <800000 17817600>;
514 cpu0_opp_806mhz: opp-806400000 {
515 opp-hz = /bits/ 64 <806400000>;
516 opp-peak-kBps = <800000 20889600>;
519 cpu0_opp_941mhz: opp-940800000 {
520 opp-hz = /bits/ 64 <940800000>;
521 opp-peak-kBps = <1804000 24576000>;
524 cpu0_opp_1152mhz: opp-1152000000 {
525 opp-hz = /bits/ 64 <1152000000>;
526 opp-peak-kBps = <2188000 27033600>;
529 cpu0_opp_1325mhz: opp-1324800000 {
530 opp-hz = /bits/ 64 <1324800000>;
531 opp-peak-kBps = <2188000 33792000>;
534 cpu0_opp_1517mhz: opp-1516800000 {
535 opp-hz = /bits/ 64 <1516800000>;
536 opp-peak-kBps = <3072000 38092800>;
539 cpu0_opp_1651mhz: opp-1651200000 {
540 opp-hz = /bits/ 64 <1651200000>;
541 opp-peak-kBps = <3072000 41779200>;
544 cpu0_opp_1805mhz: opp-1804800000 {
545 opp-hz = /bits/ 64 <1804800000>;
546 opp-peak-kBps = <4068000 48537600>;
549 cpu0_opp_1958mhz: opp-1958400000 {
550 opp-hz = /bits/ 64 <1958400000>;
551 opp-peak-kBps = <4068000 48537600>;
554 cpu0_opp_2016mhz: opp-2016000000 {
555 opp-hz = /bits/ 64 <2016000000>;
556 opp-peak-kBps = <6220000 48537600>;
560 cpu4_opp_table: opp-table-cpu4 {
561 compatible = "operating-points-v2";
562 opp-shared;
564 cpu4_opp_691mhz: opp-691200000 {
565 opp-hz = /bits/ 64 <691200000>;
566 opp-peak-kBps = <1804000 9600000>;
569 cpu4_opp_941mhz: opp-940800000 {
570 opp-hz = /bits/ 64 <940800000>;
571 opp-peak-kBps = <2188000 17817600>;
574 cpu4_opp_1229mhz: opp-1228800000 {
575 opp-hz = /bits/ 64 <1228800000>;
576 opp-peak-kBps = <4068000 24576000>;
579 cpu4_opp_1344mhz: opp-1344000000 {
580 opp-hz = /bits/ 64 <1344000000>;
581 opp-peak-kBps = <4068000 24576000>;
584 cpu4_opp_1517mhz: opp-1516800000 {
585 opp-hz = /bits/ 64 <1516800000>;
586 opp-peak-kBps = <4068000 24576000>;
589 cpu4_opp_1651mhz: opp-1651200000 {
590 opp-hz = /bits/ 64 <1651200000>;
591 opp-peak-kBps = <6220000 38092800>;
594 cpu4_opp_1901mhz: opp-1900800000 {
595 opp-hz = /bits/ 64 <1900800000>;
596 opp-peak-kBps = <6220000 44851200>;
599 cpu4_opp_2054mhz: opp-2054400000 {
600 opp-hz = /bits/ 64 <2054400000>;
601 opp-peak-kBps = <6220000 44851200>;
604 cpu4_opp_2112mhz: opp-2112000000 {
605 opp-hz = /bits/ 64 <2112000000>;
606 opp-peak-kBps = <6220000 44851200>;
609 cpu4_opp_2131mhz: opp-2131200000 {
610 opp-hz = /bits/ 64 <2131200000>;
611 opp-peak-kBps = <6220000 44851200>;
614 cpu4_opp_2208mhz: opp-2208000000 {
615 opp-hz = /bits/ 64 <2208000000>;
616 opp-peak-kBps = <6220000 44851200>;
619 cpu4_opp_2400mhz: opp-2400000000 {
620 opp-hz = /bits/ 64 <2400000000>;
621 opp-peak-kBps = <8532000 48537600>;
624 cpu4_opp_2611mhz: opp-2611200000 {
625 opp-hz = /bits/ 64 <2611200000>;
626 opp-peak-kBps = <8532000 48537600>;
630 cpu7_opp_table: opp-table-cpu7 {
631 compatible = "operating-points-v2";
632 opp-shared;
634 cpu7_opp_806mhz: opp-806400000 {
635 opp-hz = /bits/ 64 <806400000>;
636 opp-peak-kBps = <1804000 9600000>;
639 cpu7_opp_1056mhz: opp-1056000000 {
640 opp-hz = /bits/ 64 <1056000000>;
641 opp-peak-kBps = <2188000 17817600>;
644 cpu7_opp_1325mhz: opp-1324800000 {
645 opp-hz = /bits/ 64 <1324800000>;
646 opp-peak-kBps = <4068000 24576000>;
649 cpu7_opp_1517mhz: opp-1516800000 {
650 opp-hz = /bits/ 64 <1516800000>;
651 opp-peak-kBps = <4068000 24576000>;
654 cpu7_opp_1766mhz: opp-1766400000 {
655 opp-hz = /bits/ 64 <1766400000>;
656 opp-peak-kBps = <6220000 38092800>;
659 cpu7_opp_1862mhz: opp-1862400000 {
660 opp-hz = /bits/ 64 <1862400000>;
661 opp-peak-kBps = <6220000 38092800>;
664 cpu7_opp_2035mhz: opp-2035200000 {
665 opp-hz = /bits/ 64 <2035200000>;
666 opp-peak-kBps = <6220000 38092800>;
669 cpu7_opp_2112mhz: opp-2112000000 {
670 opp-hz = /bits/ 64 <2112000000>;
671 opp-peak-kBps = <6220000 44851200>;
674 cpu7_opp_2208mhz: opp-2208000000 {
675 opp-hz = /bits/ 64 <2208000000>;
676 opp-peak-kBps = <6220000 44851200>;
679 cpu7_opp_2381mhz: opp-2380800000 {
680 opp-hz = /bits/ 64 <2380800000>;
681 opp-peak-kBps = <6832000 44851200>;
684 cpu7_opp_2400mhz: opp-2400000000 {
685 opp-hz = /bits/ 64 <2400000000>;
686 opp-peak-kBps = <8532000 48537600>;
689 cpu7_opp_2515mhz: opp-2515200000 {
690 opp-hz = /bits/ 64 <2515200000>;
691 opp-peak-kBps = <8532000 48537600>;
694 cpu7_opp_2707mhz: opp-2707200000 {
695 opp-hz = /bits/ 64 <2707200000>;
696 opp-peak-kBps = <8532000 48537600>;
699 cpu7_opp_3014mhz: opp-3014400000 {
700 opp-hz = /bits/ 64 <3014400000>;
701 opp-peak-kBps = <8532000 48537600>;
713 compatible = "qcom,scm-sc7280", "qcom,scm";
714 qcom,dload-mode = <&tcsr_2 0x13000>;
719 compatible = "qcom,sc7280-clk-virt";
720 #interconnect-cells = <2>;
721 qcom,bcm-voters = <&apps_bcm_voter>;
726 memory-region = <&smem_mem>;
730 smp2p-adsp {
733 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
739 qcom,local-pid = <0>;
740 qcom,remote-pid = <2>;
742 adsp_smp2p_out: master-kernel {
743 qcom,entry-name = "master-kernel";
744 #qcom,smem-state-cells = <1>;
747 adsp_smp2p_in: slave-kernel {
748 qcom,entry-name = "slave-kernel";
749 interrupt-controller;
750 #interrupt-cells = <2>;
754 smp2p-cdsp {
757 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
763 qcom,local-pid = <0>;
764 qcom,remote-pid = <5>;
766 cdsp_smp2p_out: master-kernel {
767 qcom,entry-name = "master-kernel";
768 #qcom,smem-state-cells = <1>;
771 cdsp_smp2p_in: slave-kernel {
772 qcom,entry-name = "slave-kernel";
773 interrupt-controller;
774 #interrupt-cells = <2>;
778 smp2p-mpss {
781 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
787 qcom,local-pid = <0>;
788 qcom,remote-pid = <1>;
790 modem_smp2p_out: master-kernel {
791 qcom,entry-name = "master-kernel";
792 #qcom,smem-state-cells = <1>;
795 modem_smp2p_in: slave-kernel {
796 qcom,entry-name = "slave-kernel";
797 interrupt-controller;
798 #interrupt-cells = <2>;
801 ipa_smp2p_out: ipa-ap-to-modem {
802 qcom,entry-name = "ipa";
803 #qcom,smem-state-cells = <1>;
806 ipa_smp2p_in: ipa-modem-to-ap {
807 qcom,entry-name = "ipa";
808 interrupt-controller;
809 #interrupt-cells = <2>;
813 smp2p-wpss {
816 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
822 qcom,local-pid = <0>;
823 qcom,remote-pid = <13>;
825 wpss_smp2p_out: master-kernel {
826 qcom,entry-name = "master-kernel";
827 #qcom,smem-state-cells = <1>;
830 wpss_smp2p_in: slave-kernel {
831 qcom,entry-name = "slave-kernel";
832 interrupt-controller;
833 #interrupt-cells = <2>;
836 wlan_smp2p_out: wlan-ap-to-wpss {
837 qcom,entry-name = "wlan";
838 #qcom,smem-state-cells = <1>;
841 wlan_smp2p_in: wlan-wpss-to-ap {
842 qcom,entry-name = "wlan";
843 interrupt-controller;
844 #interrupt-cells = <2>;
849 compatible = "arm,armv8-pmuv3";
854 compatible = "arm,psci-1.0";
857 CPU_PD0: power-domain-cpu0 {
858 #power-domain-cells = <0>;
859 power-domains = <&CLUSTER_PD>;
860 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
863 CPU_PD1: power-domain-cpu1 {
864 #power-domain-cells = <0>;
865 power-domains = <&CLUSTER_PD>;
866 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
869 CPU_PD2: power-domain-cpu2 {
870 #power-domain-cells = <0>;
871 power-domains = <&CLUSTER_PD>;
872 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
875 CPU_PD3: power-domain-cpu3 {
876 #power-domain-cells = <0>;
877 power-domains = <&CLUSTER_PD>;
878 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
881 CPU_PD4: power-domain-cpu4 {
882 #power-domain-cells = <0>;
883 power-domains = <&CLUSTER_PD>;
884 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
887 CPU_PD5: power-domain-cpu5 {
888 #power-domain-cells = <0>;
889 power-domains = <&CLUSTER_PD>;
890 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
893 CPU_PD6: power-domain-cpu6 {
894 #power-domain-cells = <0>;
895 power-domains = <&CLUSTER_PD>;
896 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
899 CPU_PD7: power-domain-cpu7 {
900 #power-domain-cells = <0>;
901 power-domains = <&CLUSTER_PD>;
902 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
905 CLUSTER_PD: power-domain-cluster {
906 #power-domain-cells = <0>;
907 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_CX_RET &CLUSTER_SLEEP_LLCC_OFF>;
911 qspi_opp_table: opp-table-qspi {
912 compatible = "operating-points-v2";
914 opp-75000000 {
915 opp-hz = /bits/ 64 <75000000>;
916 required-opps = <&rpmhpd_opp_low_svs>;
919 opp-150000000 {
920 opp-hz = /bits/ 64 <150000000>;
921 required-opps = <&rpmhpd_opp_svs>;
924 opp-200000000 {
925 opp-hz = /bits/ 64 <200000000>;
926 required-opps = <&rpmhpd_opp_svs_l1>;
929 opp-300000000 {
930 opp-hz = /bits/ 64 <300000000>;
931 required-opps = <&rpmhpd_opp_nom>;
935 qup_opp_table: opp-table-qup {
936 compatible = "operating-points-v2";
938 opp-75000000 {
939 opp-hz = /bits/ 64 <75000000>;
940 required-opps = <&rpmhpd_opp_low_svs>;
943 opp-100000000 {
944 opp-hz = /bits/ 64 <100000000>;
945 required-opps = <&rpmhpd_opp_svs>;
948 opp-128000000 {
949 opp-hz = /bits/ 64 <128000000>;
950 required-opps = <&rpmhpd_opp_nom>;
955 #address-cells = <2>;
956 #size-cells = <2>;
958 dma-ranges = <0 0 0 0 0x10 0>;
959 compatible = "simple-bus";
961 gcc: clock-controller@100000 {
962 compatible = "qcom,gcc-sc7280";
969 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
974 #clock-cells = <1>;
975 #reset-cells = <1>;
976 #power-domain-cells = <1>;
977 power-domains = <&rpmhpd SC7280_CX>;
981 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
984 interrupt-controller;
985 #interrupt-cells = <3>;
986 #mbox-cells = <2>;
990 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
996 clock-names = "core";
997 power-domains = <&rpmhpd SC7280_MX>;
998 #address-cells = <1>;
999 #size-cells = <1>;
1001 gpu_speed_bin: gpu-speed-bin@1e9 {
1008 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
1009 pinctrl-names = "default", "sleep";
1010 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
1011 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
1016 reg-names = "hc", "cqhci";
1021 interrupt-names = "hc_irq", "pwr_irq";
1026 clock-names = "iface", "core", "xo";
1029 interconnect-names = "sdhc-ddr","cpu-sdhc";
1030 power-domains = <&rpmhpd SC7280_CX>;
1031 operating-points-v2 = <&sdhc1_opp_table>;
1033 bus-width = <8>;
1034 supports-cqe;
1035 dma-coherent;
1037 qcom,dll-config = <0x0007642c>;
1038 qcom,ddr-config = <0x80040868>;
1040 mmc-ddr-1_8v;
1041 mmc-hs200-1_8v;
1042 mmc-hs400-1_8v;
1043 mmc-hs400-enhanced-strobe;
1047 sdhc1_opp_table: opp-table {
1048 compatible = "operating-points-v2";
1050 opp-100000000 {
1051 opp-hz = /bits/ 64 <100000000>;
1052 required-opps = <&rpmhpd_opp_low_svs>;
1053 opp-peak-kBps = <1800000 400000>;
1054 opp-avg-kBps = <100000 0>;
1057 opp-384000000 {
1058 opp-hz = /bits/ 64 <384000000>;
1059 required-opps = <&rpmhpd_opp_nom>;
1060 opp-peak-kBps = <5400000 1600000>;
1061 opp-avg-kBps = <390000 0>;
1066 gpi_dma0: dma-controller@900000 {
1067 #dma-cells = <3>;
1068 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1082 dma-channels = <12>;
1083 dma-channel-mask = <0x7f>;
1089 compatible = "qcom,geni-se-qup";
1093 clock-names = "m-ahb", "s-ahb";
1094 #address-cells = <2>;
1095 #size-cells = <2>;
1101 compatible = "qcom,geni-i2c";
1104 clock-names = "se";
1105 pinctrl-names = "default";
1106 pinctrl-0 = <&qup_i2c0_data_clk>;
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1113 interconnect-names = "qup-core", "qup-config",
1114 "qup-memory";
1115 power-domains = <&rpmhpd SC7280_CX>;
1116 required-opps = <&rpmhpd_opp_low_svs>;
1119 dma-names = "tx", "rx";
1124 compatible = "qcom,geni-spi";
1127 clock-names = "se";
1128 pinctrl-names = "default";
1129 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133 power-domains = <&rpmhpd SC7280_CX>;
1134 operating-points-v2 = <&qup_opp_table>;
1137 interconnect-names = "qup-core", "qup-config";
1140 dma-names = "tx", "rx";
1145 compatible = "qcom,geni-uart";
1148 clock-names = "se";
1149 pinctrl-names = "default";
1150 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1152 power-domains = <&rpmhpd SC7280_CX>;
1153 operating-points-v2 = <&qup_opp_table>;
1156 interconnect-names = "qup-core", "qup-config";
1161 compatible = "qcom,geni-i2c";
1164 clock-names = "se";
1165 pinctrl-names = "default";
1166 pinctrl-0 = <&qup_i2c1_data_clk>;
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1173 interconnect-names = "qup-core", "qup-config",
1174 "qup-memory";
1175 power-domains = <&rpmhpd SC7280_CX>;
1176 required-opps = <&rpmhpd_opp_low_svs>;
1179 dma-names = "tx", "rx";
1184 compatible = "qcom,geni-spi";
1187 clock-names = "se";
1188 pinctrl-names = "default";
1189 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1191 #address-cells = <1>;
1192 #size-cells = <0>;
1193 power-domains = <&rpmhpd SC7280_CX>;
1194 operating-points-v2 = <&qup_opp_table>;
1197 interconnect-names = "qup-core", "qup-config";
1200 dma-names = "tx", "rx";
1205 compatible = "qcom,geni-uart";
1208 clock-names = "se";
1209 pinctrl-names = "default";
1210 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1212 power-domains = <&rpmhpd SC7280_CX>;
1213 operating-points-v2 = <&qup_opp_table>;
1216 interconnect-names = "qup-core", "qup-config";
1221 compatible = "qcom,geni-i2c";
1224 clock-names = "se";
1225 pinctrl-names = "default";
1226 pinctrl-0 = <&qup_i2c2_data_clk>;
1228 #address-cells = <1>;
1229 #size-cells = <0>;
1233 interconnect-names = "qup-core", "qup-config",
1234 "qup-memory";
1235 power-domains = <&rpmhpd SC7280_CX>;
1236 required-opps = <&rpmhpd_opp_low_svs>;
1239 dma-names = "tx", "rx";
1244 compatible = "qcom,geni-spi";
1247 clock-names = "se";
1248 pinctrl-names = "default";
1249 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1251 #address-cells = <1>;
1252 #size-cells = <0>;
1253 power-domains = <&rpmhpd SC7280_CX>;
1254 operating-points-v2 = <&qup_opp_table>;
1257 interconnect-names = "qup-core", "qup-config";
1260 dma-names = "tx", "rx";
1265 compatible = "qcom,geni-uart";
1268 clock-names = "se";
1269 pinctrl-names = "default";
1270 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1272 power-domains = <&rpmhpd SC7280_CX>;
1273 operating-points-v2 = <&qup_opp_table>;
1276 interconnect-names = "qup-core", "qup-config";
1281 compatible = "qcom,geni-i2c";
1284 clock-names = "se";
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&qup_i2c3_data_clk>;
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1293 interconnect-names = "qup-core", "qup-config",
1294 "qup-memory";
1295 power-domains = <&rpmhpd SC7280_CX>;
1296 required-opps = <&rpmhpd_opp_low_svs>;
1299 dma-names = "tx", "rx";
1304 compatible = "qcom,geni-spi";
1307 clock-names = "se";
1308 pinctrl-names = "default";
1309 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1311 #address-cells = <1>;
1312 #size-cells = <0>;
1313 power-domains = <&rpmhpd SC7280_CX>;
1314 operating-points-v2 = <&qup_opp_table>;
1317 interconnect-names = "qup-core", "qup-config";
1320 dma-names = "tx", "rx";
1325 compatible = "qcom,geni-uart";
1328 clock-names = "se";
1329 pinctrl-names = "default";
1330 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1332 power-domains = <&rpmhpd SC7280_CX>;
1333 operating-points-v2 = <&qup_opp_table>;
1336 interconnect-names = "qup-core", "qup-config";
1341 compatible = "qcom,geni-i2c";
1344 clock-names = "se";
1345 pinctrl-names = "default";
1346 pinctrl-0 = <&qup_i2c4_data_clk>;
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1353 interconnect-names = "qup-core", "qup-config",
1354 "qup-memory";
1355 power-domains = <&rpmhpd SC7280_CX>;
1356 required-opps = <&rpmhpd_opp_low_svs>;
1359 dma-names = "tx", "rx";
1364 compatible = "qcom,geni-spi";
1367 clock-names = "se";
1368 pinctrl-names = "default";
1369 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1371 #address-cells = <1>;
1372 #size-cells = <0>;
1373 power-domains = <&rpmhpd SC7280_CX>;
1374 operating-points-v2 = <&qup_opp_table>;
1377 interconnect-names = "qup-core", "qup-config";
1380 dma-names = "tx", "rx";
1385 compatible = "qcom,geni-uart";
1388 clock-names = "se";
1389 pinctrl-names = "default";
1390 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1392 power-domains = <&rpmhpd SC7280_CX>;
1393 operating-points-v2 = <&qup_opp_table>;
1396 interconnect-names = "qup-core", "qup-config";
1401 compatible = "qcom,geni-i2c";
1404 clock-names = "se";
1405 pinctrl-names = "default";
1406 pinctrl-0 = <&qup_i2c5_data_clk>;
1408 #address-cells = <1>;
1409 #size-cells = <0>;
1413 interconnect-names = "qup-core", "qup-config",
1414 "qup-memory";
1415 power-domains = <&rpmhpd SC7280_CX>;
1416 required-opps = <&rpmhpd_opp_low_svs>;
1419 dma-names = "tx", "rx";
1424 compatible = "qcom,geni-spi";
1427 clock-names = "se";
1428 pinctrl-names = "default";
1429 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1433 power-domains = <&rpmhpd SC7280_CX>;
1434 operating-points-v2 = <&qup_opp_table>;
1437 interconnect-names = "qup-core", "qup-config";
1440 dma-names = "tx", "rx";
1445 compatible = "qcom,geni-debug-uart";
1448 clock-names = "se";
1449 pinctrl-names = "default";
1450 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
1452 power-domains = <&rpmhpd SC7280_CX>;
1453 operating-points-v2 = <&qup_opp_table>;
1456 interconnect-names = "qup-core", "qup-config";
1461 compatible = "qcom,geni-i2c";
1464 clock-names = "se";
1465 pinctrl-names = "default";
1466 pinctrl-0 = <&qup_i2c6_data_clk>;
1468 #address-cells = <1>;
1469 #size-cells = <0>;
1473 interconnect-names = "qup-core", "qup-config",
1474 "qup-memory";
1475 power-domains = <&rpmhpd SC7280_CX>;
1476 required-opps = <&rpmhpd_opp_low_svs>;
1479 dma-names = "tx", "rx";
1484 compatible = "qcom,geni-spi";
1487 clock-names = "se";
1488 pinctrl-names = "default";
1489 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1493 power-domains = <&rpmhpd SC7280_CX>;
1494 operating-points-v2 = <&qup_opp_table>;
1497 interconnect-names = "qup-core", "qup-config";
1500 dma-names = "tx", "rx";
1505 compatible = "qcom,geni-uart";
1508 clock-names = "se";
1509 pinctrl-names = "default";
1510 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1512 power-domains = <&rpmhpd SC7280_CX>;
1513 operating-points-v2 = <&qup_opp_table>;
1516 interconnect-names = "qup-core", "qup-config";
1521 compatible = "qcom,geni-i2c";
1524 clock-names = "se";
1525 pinctrl-names = "default";
1526 pinctrl-0 = <&qup_i2c7_data_clk>;
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1533 interconnect-names = "qup-core", "qup-config",
1534 "qup-memory";
1535 power-domains = <&rpmhpd SC7280_CX>;
1536 required-opps = <&rpmhpd_opp_low_svs>;
1539 dma-names = "tx", "rx";
1544 compatible = "qcom,geni-spi";
1547 clock-names = "se";
1548 pinctrl-names = "default";
1549 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1553 power-domains = <&rpmhpd SC7280_CX>;
1554 operating-points-v2 = <&qup_opp_table>;
1557 interconnect-names = "qup-core", "qup-config";
1560 dma-names = "tx", "rx";
1565 compatible = "qcom,geni-uart";
1568 clock-names = "se";
1569 pinctrl-names = "default";
1570 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1572 power-domains = <&rpmhpd SC7280_CX>;
1573 operating-points-v2 = <&qup_opp_table>;
1576 interconnect-names = "qup-core", "qup-config";
1581 gpi_dma1: dma-controller@a00000 {
1582 #dma-cells = <3>;
1583 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1597 dma-channels = <12>;
1598 dma-channel-mask = <0x1e>;
1604 compatible = "qcom,geni-se-qup";
1608 clock-names = "m-ahb", "s-ahb";
1609 #address-cells = <2>;
1610 #size-cells = <2>;
1616 compatible = "qcom,geni-i2c";
1619 clock-names = "se";
1620 pinctrl-names = "default";
1621 pinctrl-0 = <&qup_i2c8_data_clk>;
1623 #address-cells = <1>;
1624 #size-cells = <0>;
1628 interconnect-names = "qup-core", "qup-config",
1629 "qup-memory";
1630 power-domains = <&rpmhpd SC7280_CX>;
1631 required-opps = <&rpmhpd_opp_low_svs>;
1634 dma-names = "tx", "rx";
1639 compatible = "qcom,geni-spi";
1642 clock-names = "se";
1643 pinctrl-names = "default";
1644 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1648 power-domains = <&rpmhpd SC7280_CX>;
1649 operating-points-v2 = <&qup_opp_table>;
1652 interconnect-names = "qup-core", "qup-config";
1655 dma-names = "tx", "rx";
1660 compatible = "qcom,geni-uart";
1663 clock-names = "se";
1664 pinctrl-names = "default";
1665 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1667 power-domains = <&rpmhpd SC7280_CX>;
1668 operating-points-v2 = <&qup_opp_table>;
1671 interconnect-names = "qup-core", "qup-config";
1676 compatible = "qcom,geni-i2c";
1679 clock-names = "se";
1680 pinctrl-names = "default";
1681 pinctrl-0 = <&qup_i2c9_data_clk>;
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1688 interconnect-names = "qup-core", "qup-config",
1689 "qup-memory";
1690 power-domains = <&rpmhpd SC7280_CX>;
1691 required-opps = <&rpmhpd_opp_low_svs>;
1694 dma-names = "tx", "rx";
1699 compatible = "qcom,geni-spi";
1702 clock-names = "se";
1703 pinctrl-names = "default";
1704 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1706 #address-cells = <1>;
1707 #size-cells = <0>;
1708 power-domains = <&rpmhpd SC7280_CX>;
1709 operating-points-v2 = <&qup_opp_table>;
1712 interconnect-names = "qup-core", "qup-config";
1715 dma-names = "tx", "rx";
1720 compatible = "qcom,geni-uart";
1723 clock-names = "se";
1724 pinctrl-names = "default";
1725 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1727 power-domains = <&rpmhpd SC7280_CX>;
1728 operating-points-v2 = <&qup_opp_table>;
1731 interconnect-names = "qup-core", "qup-config";
1736 compatible = "qcom,geni-i2c";
1739 clock-names = "se";
1740 pinctrl-names = "default";
1741 pinctrl-0 = <&qup_i2c10_data_clk>;
1743 #address-cells = <1>;
1744 #size-cells = <0>;
1748 interconnect-names = "qup-core", "qup-config",
1749 "qup-memory";
1750 power-domains = <&rpmhpd SC7280_CX>;
1751 required-opps = <&rpmhpd_opp_low_svs>;
1754 dma-names = "tx", "rx";
1759 compatible = "qcom,geni-spi";
1762 clock-names = "se";
1763 pinctrl-names = "default";
1764 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1766 #address-cells = <1>;
1767 #size-cells = <0>;
1768 power-domains = <&rpmhpd SC7280_CX>;
1769 operating-points-v2 = <&qup_opp_table>;
1772 interconnect-names = "qup-core", "qup-config";
1775 dma-names = "tx", "rx";
1780 compatible = "qcom,geni-uart";
1783 clock-names = "se";
1784 pinctrl-names = "default";
1785 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1787 power-domains = <&rpmhpd SC7280_CX>;
1788 operating-points-v2 = <&qup_opp_table>;
1791 interconnect-names = "qup-core", "qup-config";
1796 compatible = "qcom,geni-i2c";
1799 clock-names = "se";
1800 pinctrl-names = "default";
1801 pinctrl-0 = <&qup_i2c11_data_clk>;
1803 #address-cells = <1>;
1804 #size-cells = <0>;
1808 interconnect-names = "qup-core", "qup-config",
1809 "qup-memory";
1810 power-domains = <&rpmhpd SC7280_CX>;
1811 required-opps = <&rpmhpd_opp_low_svs>;
1814 dma-names = "tx", "rx";
1819 compatible = "qcom,geni-spi";
1822 clock-names = "se";
1823 pinctrl-names = "default";
1824 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1828 power-domains = <&rpmhpd SC7280_CX>;
1829 operating-points-v2 = <&qup_opp_table>;
1832 interconnect-names = "qup-core", "qup-config";
1835 dma-names = "tx", "rx";
1840 compatible = "qcom,geni-uart";
1843 clock-names = "se";
1844 pinctrl-names = "default";
1845 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1847 power-domains = <&rpmhpd SC7280_CX>;
1848 operating-points-v2 = <&qup_opp_table>;
1851 interconnect-names = "qup-core", "qup-config";
1856 compatible = "qcom,geni-i2c";
1859 clock-names = "se";
1860 pinctrl-names = "default";
1861 pinctrl-0 = <&qup_i2c12_data_clk>;
1863 #address-cells = <1>;
1864 #size-cells = <0>;
1868 interconnect-names = "qup-core", "qup-config",
1869 "qup-memory";
1870 power-domains = <&rpmhpd SC7280_CX>;
1871 required-opps = <&rpmhpd_opp_low_svs>;
1874 dma-names = "tx", "rx";
1879 compatible = "qcom,geni-spi";
1882 clock-names = "se";
1883 pinctrl-names = "default";
1884 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1886 #address-cells = <1>;
1887 #size-cells = <0>;
1888 power-domains = <&rpmhpd SC7280_CX>;
1889 operating-points-v2 = <&qup_opp_table>;
1892 interconnect-names = "qup-core", "qup-config";
1895 dma-names = "tx", "rx";
1900 compatible = "qcom,geni-uart";
1903 clock-names = "se";
1904 pinctrl-names = "default";
1905 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1907 power-domains = <&rpmhpd SC7280_CX>;
1908 operating-points-v2 = <&qup_opp_table>;
1911 interconnect-names = "qup-core", "qup-config";
1916 compatible = "qcom,geni-i2c";
1919 clock-names = "se";
1920 pinctrl-names = "default";
1921 pinctrl-0 = <&qup_i2c13_data_clk>;
1923 #address-cells = <1>;
1924 #size-cells = <0>;
1928 interconnect-names = "qup-core", "qup-config",
1929 "qup-memory";
1930 power-domains = <&rpmhpd SC7280_CX>;
1931 required-opps = <&rpmhpd_opp_low_svs>;
1934 dma-names = "tx", "rx";
1939 compatible = "qcom,geni-spi";
1942 clock-names = "se";
1943 pinctrl-names = "default";
1944 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1946 #address-cells = <1>;
1947 #size-cells = <0>;
1948 power-domains = <&rpmhpd SC7280_CX>;
1949 operating-points-v2 = <&qup_opp_table>;
1952 interconnect-names = "qup-core", "qup-config";
1955 dma-names = "tx", "rx";
1960 compatible = "qcom,geni-uart";
1963 clock-names = "se";
1964 pinctrl-names = "default";
1965 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1967 power-domains = <&rpmhpd SC7280_CX>;
1968 operating-points-v2 = <&qup_opp_table>;
1971 interconnect-names = "qup-core", "qup-config";
1976 compatible = "qcom,geni-i2c";
1979 clock-names = "se";
1980 pinctrl-names = "default";
1981 pinctrl-0 = <&qup_i2c14_data_clk>;
1983 #address-cells = <1>;
1984 #size-cells = <0>;
1988 interconnect-names = "qup-core", "qup-config",
1989 "qup-memory";
1990 power-domains = <&rpmhpd SC7280_CX>;
1991 required-opps = <&rpmhpd_opp_low_svs>;
1994 dma-names = "tx", "rx";
1999 compatible = "qcom,geni-spi";
2002 clock-names = "se";
2003 pinctrl-names = "default";
2004 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2006 #address-cells = <1>;
2007 #size-cells = <0>;
2008 power-domains = <&rpmhpd SC7280_CX>;
2009 operating-points-v2 = <&qup_opp_table>;
2012 interconnect-names = "qup-core", "qup-config";
2015 dma-names = "tx", "rx";
2020 compatible = "qcom,geni-uart";
2023 clock-names = "se";
2024 pinctrl-names = "default";
2025 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
2027 power-domains = <&rpmhpd SC7280_CX>;
2028 operating-points-v2 = <&qup_opp_table>;
2031 interconnect-names = "qup-core", "qup-config";
2036 compatible = "qcom,geni-i2c";
2039 clock-names = "se";
2040 pinctrl-names = "default";
2041 pinctrl-0 = <&qup_i2c15_data_clk>;
2043 #address-cells = <1>;
2044 #size-cells = <0>;
2048 interconnect-names = "qup-core", "qup-config",
2049 "qup-memory";
2050 power-domains = <&rpmhpd SC7280_CX>;
2051 required-opps = <&rpmhpd_opp_low_svs>;
2054 dma-names = "tx", "rx";
2059 compatible = "qcom,geni-spi";
2062 clock-names = "se";
2063 pinctrl-names = "default";
2064 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2066 #address-cells = <1>;
2067 #size-cells = <0>;
2068 power-domains = <&rpmhpd SC7280_CX>;
2069 operating-points-v2 = <&qup_opp_table>;
2072 interconnect-names = "qup-core", "qup-config";
2075 dma-names = "tx", "rx";
2080 compatible = "qcom,geni-uart";
2083 clock-names = "se";
2084 pinctrl-names = "default";
2085 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2087 power-domains = <&rpmhpd SC7280_CX>;
2088 operating-points-v2 = <&qup_opp_table>;
2091 interconnect-names = "qup-core", "qup-config";
2097 compatible = "qcom,sc7280-trng", "qcom,trng";
2103 compatible = "qcom,sc7280-cnoc2";
2104 #interconnect-cells = <2>;
2105 qcom,bcm-voters = <&apps_bcm_voter>;
2110 compatible = "qcom,sc7280-cnoc3";
2111 #interconnect-cells = <2>;
2112 qcom,bcm-voters = <&apps_bcm_voter>;
2117 compatible = "qcom,sc7280-mc-virt";
2118 #interconnect-cells = <2>;
2119 qcom,bcm-voters = <&apps_bcm_voter>;
2124 compatible = "qcom,sc7280-system-noc";
2125 #interconnect-cells = <2>;
2126 qcom,bcm-voters = <&apps_bcm_voter>;
2130 compatible = "qcom,sc7280-aggre1-noc";
2132 #interconnect-cells = <2>;
2133 qcom,bcm-voters = <&apps_bcm_voter>;
2140 compatible = "qcom,sc7280-aggre2-noc";
2141 #interconnect-cells = <2>;
2142 qcom,bcm-voters = <&apps_bcm_voter>;
2148 compatible = "qcom,sc7280-mmss-noc";
2149 #interconnect-cells = <2>;
2150 qcom,bcm-voters = <&apps_bcm_voter>;
2154 compatible = "qcom,wcn6750-wifi";
2190 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2192 qcom,smem-states = <&wlan_smp2p_out 0>;
2193 qcom,smem-state-names = "wlan-smp2p-out";
2197 compatible = "qcom,pcie-sc7280";
2204 reg-names = "parf", "dbi", "elbi", "atu", "config";
2206 linux,pci-domain = <1>;
2207 bus-range = <0x00 0xff>;
2208 num-lanes = <2>;
2210 #address-cells = <3>;
2211 #size-cells = <2>;
2224 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2226 #interrupt-cells = <1>;
2227 interrupt-map-mask = <0 0 0 0x7>;
2228 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2247 clock-names = "pipe",
2261 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2262 assigned-clock-rates = <19200000>;
2265 reset-names = "pci";
2267 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2270 phy-names = "pciephy";
2272 pinctrl-names = "default";
2273 pinctrl-0 = <&pcie1_clkreq_n>;
2275 dma-coherent;
2277 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2285 bus-range = <0x01 0xff>;
2287 #address-cells = <3>;
2288 #size-cells = <2>;
2294 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2301 clock-names = "aux",
2307 clock-output-names = "pcie_1_pipe_clk";
2308 #clock-cells = <0>;
2310 #phy-cells = <0>;
2313 reset-names = "phy";
2315 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2316 assigned-clock-rates = <100000000>;
2322 compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
2323 "jedec,ufs-2.0";
2327 phy-names = "ufsphy";
2328 lanes-per-direction = <2>;
2329 #reset-cells = <1>;
2331 reset-names = "rst";
2333 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
2334 required-opps = <&rpmhpd_opp_nom>;
2337 dma-coherent;
2343 interconnect-names = "ufs-ddr", "cpu-ufs";
2353 clock-names = "core_clk",
2361 freq-table-hz =
2376 compatible = "qcom,sc7280-qmp-ufs-phy";
2381 clock-names = "ref", "ref_aux", "qref";
2383 power-domains = <&rpmhpd SC7280_MX>;
2386 reset-names = "ufsphy";
2388 #clock-cells = <1>;
2389 #phy-cells = <0>;
2395 compatible = "qcom,sc7280-inline-crypto-engine",
2396 "qcom,inline-crypto-engine";
2401 cryptobam: dma-controller@1dc4000 {
2402 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2405 #dma-cells = <1>;
2409 qcom,controlled-remotely;
2410 num-channels = <16>;
2411 qcom,num-ees = <4>;
2415 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";
2418 dma-names = "rx", "tx";
2422 interconnect-names = "memory";
2426 compatible = "qcom,sc7280-ipa";
2433 reg-names = "ipa-reg",
2434 "ipa-shared",
2437 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2441 interrupt-names = "ipa",
2443 "ipa-clock-query",
2444 "ipa-setup-ready";
2447 clock-names = "core";
2451 interconnect-names = "memory",
2456 qcom,smem-states = <&ipa_smp2p_out 0>,
2458 qcom,smem-state-names = "ipa-clock-enabled-valid",
2459 "ipa-clock-enabled";
2465 compatible = "qcom,tcsr-mutex";
2467 #hwlock-cells = <1>;
2471 compatible = "qcom,sc7280-tcsr", "syscon";
2476 compatible = "qcom,sc7280-tcsr", "syscon";
2481 compatible = "qcom,sc7280-lpasscc";
2484 reg-names = "qdsp6ss", "top_cc";
2486 clock-names = "iface";
2487 #clock-cells = <1>;
2492 compatible = "qcom,sc7280-lpass-rx-macro";
2495 pinctrl-names = "default";
2496 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2501 clock-names = "mclk", "npl", "fsgen";
2503 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2505 power-domain-names = "macro", "dcodec";
2507 #clock-cells = <0>;
2508 #sound-dai-cells = <1>;
2514 compatible = "qcom,soundwire-v1.6.0";
2519 clock-names = "iface";
2521 qcom,din-ports = <0>;
2522 qcom,dout-ports = <5>;
2525 reset-names = "swr_audio_cgcr";
2527 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2528 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2529 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2530 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2531 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2532 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2533 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2534 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2535 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2537 #sound-dai-cells = <1>;
2538 #address-cells = <2>;
2539 #size-cells = <0>;
2545 compatible = "qcom,sc7280-lpass-tx-macro";
2548 pinctrl-names = "default";
2549 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2554 clock-names = "mclk", "npl", "fsgen";
2556 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2558 power-domain-names = "macro", "dcodec";
2560 #clock-cells = <0>;
2561 #sound-dai-cells = <1>;
2567 compatible = "qcom,soundwire-v1.6.0";
2570 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2573 clock-names = "iface";
2575 qcom,din-ports = <3>;
2576 qcom,dout-ports = <0>;
2579 reset-names = "swr_audio_cgcr";
2581 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2582 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2583 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2584 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2585 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2586 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2587 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2588 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2589 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2591 #sound-dai-cells = <1>;
2592 #address-cells = <2>;
2593 #size-cells = <0>;
2598 lpass_audiocc: clock-controller@3300000 {
2599 compatible = "qcom,sc7280-lpassaudiocc";
2604 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2605 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2606 #clock-cells = <1>;
2607 #power-domain-cells = <1>;
2608 #reset-cells = <1>;
2612 compatible = "qcom,sc7280-lpass-va-macro";
2615 pinctrl-names = "default";
2616 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2619 clock-names = "mclk";
2621 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2623 power-domain-names = "macro", "dcodec";
2625 #clock-cells = <0>;
2626 #sound-dai-cells = <1>;
2631 lpass_aon: clock-controller@3380000 {
2632 compatible = "qcom,sc7280-lpassaoncc";
2637 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2638 #clock-cells = <1>;
2639 #power-domain-cells = <1>;
2643 lpass_core: clock-controller@3900000 {
2644 compatible = "qcom,sc7280-lpasscorecc";
2647 clock-names = "bi_tcxo";
2648 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2649 #clock-cells = <1>;
2650 #power-domain-cells = <1>;
2655 compatible = "qcom,sc7280-lpass-cpu";
2663 reg-names = "lpass-hdmiif",
2664 "lpass-lpaif",
2665 "lpass-rxtx-cdc-dma-lpm",
2666 "lpass-rxtx-lpaif",
2667 "lpass-va-lpaif",
2668 "lpass-va-cdc-dma-lpm";
2674 power-domains = <&rpmhpd SC7280_LCX>;
2675 power-domain-names = "lcx";
2676 required-opps = <&rpmhpd_opp_nom>;
2688 clock-names = "aon_cc_audio_hm_h",
2699 #sound-dai-cells = <1>;
2700 #address-cells = <1>;
2701 #size-cells = <0>;
2707 interrupt-names = "lpass-irq-lpaif",
2708 "lpass-irq-hdmi",
2709 "lpass-irq-vaif",
2710 "lpass-irq-rxtxif";
2715 slimbam: dma-controller@3a84000 {
2716 compatible = "qcom,bam-v1.7.0";
2719 #dma-cells = <1>;
2720 qcom,controlled-remotely;
2721 num-channels = <31>;
2723 qcom,num-ees = <2>;
2728 slim: slim-ngd@3ac0000 {
2729 compatible = "qcom,slim-ngd-v1.5.0";
2733 dma-names = "rx", "tx";
2735 #address-cells = <1>;
2736 #size-cells = <0>;
2740 lpass_hm: clock-controller@3c00000 {
2741 compatible = "qcom,sc7280-lpasshm";
2744 clock-names = "bi_tcxo";
2745 #clock-cells = <1>;
2746 #power-domain-cells = <1>;
2752 compatible = "qcom,sc7280-lpass-ag-noc";
2753 #interconnect-cells = <2>;
2754 qcom,bcm-voters = <&apps_bcm_voter>;
2758 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2761 gpio-controller;
2762 #gpio-cells = <2>;
2763 gpio-ranges = <&lpass_tlmm 0 0 15>;
2765 lpass_dmic01_clk: dmic01-clk-state {
2770 lpass_dmic01_data: dmic01-data-state {
2775 lpass_dmic23_clk: dmic23-clk-state {
2780 lpass_dmic23_data: dmic23-data-state {
2785 lpass_rx_swr_clk: rx-swr-clk-state {
2790 lpass_rx_swr_data: rx-swr-data-state {
2795 lpass_tx_swr_clk: tx-swr-clk-state {
2800 lpass_tx_swr_data: tx-swr-data-state {
2807 compatible = "qcom,adreno-635.0", "qcom,adreno";
2811 reg-names = "kgsl_3d0_reg_memory",
2817 operating-points-v2 = <&gpu_opp_table>;
2820 interconnect-names = "gfx-mem";
2821 #cooling-cells = <2>;
2823 nvmem-cells = <&gpu_speed_bin>;
2824 nvmem-cell-names = "speed_bin";
2826 gpu_zap_shader: zap-shader {
2827 memory-region = <&gpu_zap_mem>;
2830 gpu_opp_table: opp-table {
2831 compatible = "operating-points-v2";
2833 opp-315000000 {
2834 opp-hz = /bits/ 64 <315000000>;
2835 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2836 opp-peak-kBps = <1804000>;
2837 opp-supported-hw = <0x07>;
2840 opp-450000000 {
2841 opp-hz = /bits/ 64 <450000000>;
2842 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2843 opp-peak-kBps = <4068000>;
2844 opp-supported-hw = <0x07>;
2848 opp-550000000-0 {
2849 opp-hz = /bits/ 64 <550000000>;
2850 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2851 opp-peak-kBps = <8368000>;
2852 opp-supported-hw = <0x01>;
2855 opp-550000000-1 {
2856 opp-hz = /bits/ 64 <550000000>;
2857 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2858 opp-peak-kBps = <6832000>;
2859 opp-supported-hw = <0x06>;
2862 opp-608000000 {
2863 opp-hz = /bits/ 64 <608000000>;
2864 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2865 opp-peak-kBps = <8368000>;
2866 opp-supported-hw = <0x06>;
2869 opp-700000000 {
2870 opp-hz = /bits/ 64 <700000000>;
2871 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2872 opp-peak-kBps = <8532000>;
2873 opp-supported-hw = <0x06>;
2876 opp-812000000 {
2877 opp-hz = /bits/ 64 <812000000>;
2878 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2879 opp-peak-kBps = <8532000>;
2880 opp-supported-hw = <0x06>;
2883 opp-840000000 {
2884 opp-hz = /bits/ 64 <840000000>;
2885 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2886 opp-peak-kBps = <8532000>;
2887 opp-supported-hw = <0x02>;
2890 opp-900000000 {
2891 opp-hz = /bits/ 64 <900000000>;
2892 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2893 opp-peak-kBps = <8532000>;
2894 opp-supported-hw = <0x02>;
2900 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2904 reg-names = "gmu", "rscc", "gmu_pdc";
2907 interrupt-names = "hfi", "gmu";
2915 clock-names = "gmu",
2922 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2924 power-domain-names = "cx",
2927 operating-points-v2 = <&gmu_opp_table>;
2929 gmu_opp_table: opp-table {
2930 compatible = "operating-points-v2";
2932 opp-200000000 {
2933 opp-hz = /bits/ 64 <200000000>;
2934 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2939 gpucc: clock-controller@3d90000 {
2940 compatible = "qcom,sc7280-gpucc";
2945 clock-names = "bi_tcxo",
2948 #clock-cells = <1>;
2949 #reset-cells = <1>;
2950 #power-domain-cells = <1>;
2954 compatible = "qcom,sc7280-dcc", "qcom,dcc";
2960 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
2961 "qcom,smmu-500", "arm,mmu-500";
2963 #iommu-cells = <2>;
2964 #global-interrupts = <2>;
2985 clock-names = "gcc_gpu_memnoc_gfx_clk",
2993 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2994 dma-coherent;
2998 compatible = "qcom,sc7280-tbu";
3000 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>;
3004 compatible = "qcom,sc7280-tbu";
3006 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>;
3010 compatible = "qcom,sc7280-mpss-pas";
3013 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
3019 interrupt-names = "wdog", "fatal", "ready", "handover",
3020 "stop-ack", "shutdown-ack";
3023 clock-names = "xo";
3025 power-domains = <&rpmhpd SC7280_CX>,
3027 power-domain-names = "cx", "mss";
3029 memory-region = <&mpss_mem>;
3033 qcom,smem-states = <&modem_smp2p_out 0>;
3034 qcom,smem-state-names = "stop";
3038 glink-edge {
3039 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
3045 qcom,remote-pid = <1>;
3050 compatible = "arm,coresight-stm", "arm,primecell";
3053 reg-names = "stm-base", "stm-stimulus-base";
3056 clock-names = "apb_pclk";
3058 out-ports {
3061 remote-endpoint = <&funnel0_in7>;
3068 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3072 clock-names = "apb_pclk";
3074 out-ports {
3077 remote-endpoint = <&merge_funnel_in0>;
3082 in-ports {
3083 #address-cells = <1>;
3084 #size-cells = <0>;
3089 remote-endpoint = <&stm_out>;
3096 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3100 clock-names = "apb_pclk";
3102 out-ports {
3105 remote-endpoint = <&merge_funnel_in1>;
3110 in-ports {
3111 #address-cells = <1>;
3112 #size-cells = <0>;
3117 remote-endpoint = <&apss_merge_funnel_out>;
3124 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3128 clock-names = "apb_pclk";
3130 out-ports {
3133 remote-endpoint = <&swao_funnel_in>;
3138 in-ports {
3139 #address-cells = <1>;
3140 #size-cells = <0>;
3145 remote-endpoint = <&funnel0_out>;
3152 remote-endpoint = <&funnel1_out>;
3159 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3163 clock-names = "apb_pclk";
3165 out-ports {
3168 remote-endpoint = <&etr_in>;
3173 in-ports {
3176 remote-endpoint = <&swao_replicator_out>;
3183 compatible = "arm,coresight-tmc", "arm,primecell";
3188 clock-names = "apb_pclk";
3189 arm,scatter-gather;
3191 in-ports {
3194 remote-endpoint = <&replicator_out>;
3201 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3205 clock-names = "apb_pclk";
3207 out-ports {
3210 remote-endpoint = <&etf_in>;
3215 in-ports {
3216 #address-cells = <1>;
3217 #size-cells = <0>;
3222 remote-endpoint = <&merge_funnel_out>;
3229 compatible = "arm,coresight-tmc", "arm,primecell";
3233 clock-names = "apb_pclk";
3235 out-ports {
3238 remote-endpoint = <&swao_replicator_in>;
3243 in-ports {
3246 remote-endpoint = <&swao_funnel_out>;
3253 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3257 clock-names = "apb_pclk";
3258 qcom,replicator-loses-context;
3260 out-ports {
3263 remote-endpoint = <&replicator_in>;
3268 in-ports {
3271 remote-endpoint = <&etf_out>;
3278 compatible = "arm,coresight-etm4x", "arm,primecell";
3284 clock-names = "apb_pclk";
3285 arm,coresight-loses-context-with-cpu;
3286 qcom,skip-power-up;
3288 out-ports {
3291 remote-endpoint = <&apss_funnel_in0>;
3298 compatible = "arm,coresight-etm4x", "arm,primecell";
3304 clock-names = "apb_pclk";
3305 arm,coresight-loses-context-with-cpu;
3306 qcom,skip-power-up;
3308 out-ports {
3311 remote-endpoint = <&apss_funnel_in1>;
3318 compatible = "arm,coresight-etm4x", "arm,primecell";
3324 clock-names = "apb_pclk";
3325 arm,coresight-loses-context-with-cpu;
3326 qcom,skip-power-up;
3328 out-ports {
3331 remote-endpoint = <&apss_funnel_in2>;
3338 compatible = "arm,coresight-etm4x", "arm,primecell";
3344 clock-names = "apb_pclk";
3345 arm,coresight-loses-context-with-cpu;
3346 qcom,skip-power-up;
3348 out-ports {
3351 remote-endpoint = <&apss_funnel_in3>;
3358 compatible = "arm,coresight-etm4x", "arm,primecell";
3364 clock-names = "apb_pclk";
3365 arm,coresight-loses-context-with-cpu;
3366 qcom,skip-power-up;
3368 out-ports {
3371 remote-endpoint = <&apss_funnel_in4>;
3378 compatible = "arm,coresight-etm4x", "arm,primecell";
3384 clock-names = "apb_pclk";
3385 arm,coresight-loses-context-with-cpu;
3386 qcom,skip-power-up;
3388 out-ports {
3391 remote-endpoint = <&apss_funnel_in5>;
3398 compatible = "arm,coresight-etm4x", "arm,primecell";
3404 clock-names = "apb_pclk";
3405 arm,coresight-loses-context-with-cpu;
3406 qcom,skip-power-up;
3408 out-ports {
3411 remote-endpoint = <&apss_funnel_in6>;
3418 compatible = "arm,coresight-etm4x", "arm,primecell";
3424 clock-names = "apb_pclk";
3425 arm,coresight-loses-context-with-cpu;
3426 qcom,skip-power-up;
3428 out-ports {
3431 remote-endpoint = <&apss_funnel_in7>;
3438 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3442 clock-names = "apb_pclk";
3444 out-ports {
3447 remote-endpoint = <&apss_merge_funnel_in>;
3452 in-ports {
3453 #address-cells = <1>;
3454 #size-cells = <0>;
3459 remote-endpoint = <&etm0_out>;
3466 remote-endpoint = <&etm1_out>;
3473 remote-endpoint = <&etm2_out>;
3480 remote-endpoint = <&etm3_out>;
3487 remote-endpoint = <&etm4_out>;
3494 remote-endpoint = <&etm5_out>;
3501 remote-endpoint = <&etm6_out>;
3508 remote-endpoint = <&etm7_out>;
3515 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3519 clock-names = "apb_pclk";
3521 out-ports {
3524 remote-endpoint = <&funnel1_in4>;
3529 in-ports {
3532 remote-endpoint = <&apss_funnel_out>;
3539 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3540 pinctrl-names = "default", "sleep";
3541 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3542 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3550 interrupt-names = "hc_irq", "pwr_irq";
3555 clock-names = "iface", "core", "xo";
3558 interconnect-names = "sdhc-ddr","cpu-sdhc";
3559 power-domains = <&rpmhpd SC7280_CX>;
3560 operating-points-v2 = <&sdhc2_opp_table>;
3562 bus-width = <4>;
3563 dma-coherent;
3565 qcom,dll-config = <0x0007642c>;
3569 sdhc2_opp_table: opp-table {
3570 compatible = "operating-points-v2";
3572 opp-100000000 {
3573 opp-hz = /bits/ 64 <100000000>;
3574 required-opps = <&rpmhpd_opp_low_svs>;
3575 opp-peak-kBps = <1800000 400000>;
3576 opp-avg-kBps = <100000 0>;
3579 opp-202000000 {
3580 opp-hz = /bits/ 64 <202000000>;
3581 required-opps = <&rpmhpd_opp_nom>;
3582 opp-peak-kBps = <5400000 1600000>;
3583 opp-avg-kBps = <200000 0>;
3589 compatible = "qcom,sc7280-usb-hs-phy",
3590 "qcom,usb-snps-hs-7nm-phy";
3593 #phy-cells = <0>;
3596 clock-names = "ref";
3602 compatible = "qcom,sc7280-usb-hs-phy",
3603 "qcom,usb-snps-hs-7nm-phy";
3606 #phy-cells = <0>;
3609 clock-names = "ref";
3615 compatible = "qcom,sc7280-qmp-usb3-dp-phy";
3623 clock-names = "aux",
3630 reset-names = "phy", "common";
3632 #clock-cells = <1>;
3633 #phy-cells = <1>;
3636 #address-cells = <1>;
3637 #size-cells = <0>;
3663 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3666 #address-cells = <2>;
3667 #size-cells = <2>;
3669 dma-ranges;
3676 clock-names = "cfg_noc",
3682 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3684 assigned-clock-rates = <19200000>, <200000000>;
3686 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3690 interrupt-names = "pwr_event",
3695 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3696 required-opps = <&rpmhpd_opp_nom>;
3702 interconnect-names = "usb-ddr", "apps-usb";
3712 phy-names = "usb2-phy";
3713 maximum-speed = "high-speed";
3714 usb-role-switch;
3718 remote-endpoint = <&eud_ep>;
3725 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3728 #address-cells = <1>;
3729 #size-cells = <0>;
3733 clock-names = "iface", "core";
3736 interconnect-names = "qspi-config";
3737 power-domains = <&rpmhpd SC7280_CX>;
3738 operating-points-v2 = <&qspi_opp_table>;
3743 compatible = "qcom,sc7280-adsp-pas";
3746 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3752 interrupt-names = "wdog", "fatal", "ready", "handover",
3753 "stop-ack", "shutdown-ack";
3756 clock-names = "xo";
3758 power-domains = <&rpmhpd SC7280_LCX>,
3760 power-domain-names = "lcx", "lmx";
3762 memory-region = <&adsp_mem>;
3766 qcom,smem-states = <&adsp_smp2p_out 0>;
3767 qcom,smem-state-names = "stop";
3771 glink-edge {
3772 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3780 qcom,remote-pid = <2>;
3783 compatible = "qcom,apr-v2";
3784 qcom,glink-channels = "apr_audio_svc";
3786 #address-cells = <1>;
3787 #size-cells = <0>;
3792 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3798 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3801 compatible = "qcom,q6afe-dais";
3802 #address-cells = <1>;
3803 #size-cells = <0>;
3804 #sound-dai-cells = <1>;
3807 q6afecc: clock-controller {
3808 compatible = "qcom,q6afe-clocks";
3809 #clock-cells = <2>;
3816 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3819 compatible = "qcom,q6asm-dais";
3820 #address-cells = <1>;
3821 #size-cells = <0>;
3822 #sound-dai-cells = <1>;
3842 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3845 compatible = "qcom,q6adm-routing";
3846 #sound-dai-cells = <0>;
3853 qcom,glink-channels = "fastrpcglink-apps-dsp";
3855 qcom,non-secure-domain;
3856 #address-cells = <1>;
3857 #size-cells = <0>;
3859 compute-cb@3 {
3860 compatible = "qcom,fastrpc-compute-cb";
3865 compute-cb@4 {
3866 compatible = "qcom,fastrpc-compute-cb";
3871 compute-cb@5 {
3872 compatible = "qcom,fastrpc-compute-cb";
3881 compatible = "qcom,sc7280-wpss-pas";
3884 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3890 interrupt-names = "wdog", "fatal", "ready", "handover",
3891 "stop-ack", "shutdown-ack";
3894 clock-names = "xo";
3896 power-domains = <&rpmhpd SC7280_CX>,
3898 power-domain-names = "cx", "mx";
3900 memory-region = <&wpss_mem>;
3904 qcom,smem-states = <&wpss_smp2p_out 0>;
3905 qcom,smem-state-names = "stop";
3910 glink-edge {
3911 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3918 qcom,remote-pid = <13>;
3923 compatible = "qcom,sc7280-llcc-bwmon";
3930 operating-points-v2 = <&llcc_bwmon_opp_table>;
3932 llcc_bwmon_opp_table: opp-table {
3933 compatible = "operating-points-v2";
3935 opp-0 {
3936 opp-peak-kBps = <800000>;
3938 opp-1 {
3939 opp-peak-kBps = <1804000>;
3941 opp-2 {
3942 opp-peak-kBps = <2188000>;
3944 opp-3 {
3945 opp-peak-kBps = <3072000>;
3947 opp-4 {
3948 opp-peak-kBps = <4068000>;
3950 opp-5 {
3951 opp-peak-kBps = <6220000>;
3953 opp-6 {
3954 opp-peak-kBps = <6832000>;
3956 opp-7 {
3957 opp-peak-kBps = <8532000>;
3963 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
3969 operating-points-v2 = <&cpu_bwmon_opp_table>;
3971 cpu_bwmon_opp_table: opp-table {
3972 compatible = "operating-points-v2";
3974 opp-0 {
3975 opp-peak-kBps = <2400000>;
3977 opp-1 {
3978 opp-peak-kBps = <4800000>;
3980 opp-2 {
3981 opp-peak-kBps = <7456000>;
3983 opp-3 {
3984 opp-peak-kBps = <9600000>;
3986 opp-4 {
3987 opp-peak-kBps = <12896000>;
3989 opp-5 {
3990 opp-peak-kBps = <14928000>;
3992 opp-6 {
3993 opp-peak-kBps = <17056000>;
4000 compatible = "qcom,sc7280-dc-noc";
4001 #interconnect-cells = <2>;
4002 qcom,bcm-voters = <&apps_bcm_voter>;
4007 compatible = "qcom,sc7280-gem-noc";
4008 #interconnect-cells = <2>;
4009 qcom,bcm-voters = <&apps_bcm_voter>;
4012 system-cache-controller@9200000 {
4013 compatible = "qcom,sc7280-llcc";
4016 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
4021 compatible = "qcom,sc7280-eud", "qcom,eud";
4024 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
4029 #address-cells = <1>;
4030 #size-cells = <0>;
4035 remote-endpoint = <&usb2_role_switch>;
4043 compatible = "qcom,sc7280-nsp-noc";
4044 #interconnect-cells = <2>;
4045 qcom,bcm-voters = <&apps_bcm_voter>;
4049 compatible = "qcom,sc7280-cdsp-pas";
4052 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4058 interrupt-names = "wdog", "fatal", "ready", "handover",
4059 "stop-ack", "shutdown-ack";
4062 clock-names = "xo";
4064 power-domains = <&rpmhpd SC7280_CX>,
4066 power-domain-names = "cx", "mx";
4070 memory-region = <&cdsp_mem>;
4074 qcom,smem-states = <&cdsp_smp2p_out 0>;
4075 qcom,smem-state-names = "stop";
4079 glink-edge {
4080 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4087 qcom,remote-pid = <5>;
4091 qcom,glink-channels = "fastrpcglink-apps-dsp";
4093 qcom,non-secure-domain;
4094 #address-cells = <1>;
4095 #size-cells = <0>;
4097 compute-cb@1 {
4098 compatible = "qcom,fastrpc-compute-cb";
4104 compute-cb@2 {
4105 compatible = "qcom,fastrpc-compute-cb";
4111 compute-cb@3 {
4112 compatible = "qcom,fastrpc-compute-cb";
4118 compute-cb@4 {
4119 compatible = "qcom,fastrpc-compute-cb";
4125 compute-cb@5 {
4126 compatible = "qcom,fastrpc-compute-cb";
4132 compute-cb@6 {
4133 compatible = "qcom,fastrpc-compute-cb";
4139 compute-cb@7 {
4140 compatible = "qcom,fastrpc-compute-cb";
4146 compute-cb@8 {
4147 compatible = "qcom,fastrpc-compute-cb";
4155 compute-cb@11 {
4156 compatible = "qcom,fastrpc-compute-cb";
4162 compute-cb@12 {
4163 compatible = "qcom,fastrpc-compute-cb";
4169 compute-cb@13 {
4170 compatible = "qcom,fastrpc-compute-cb";
4176 compute-cb@14 {
4177 compatible = "qcom,fastrpc-compute-cb";
4187 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
4190 #address-cells = <2>;
4191 #size-cells = <2>;
4193 dma-ranges;
4200 clock-names = "cfg_noc",
4206 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4208 assigned-clock-rates = <19200000>, <200000000>;
4210 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4215 interrupt-names = "pwr_event",
4221 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4222 required-opps = <&rpmhpd_opp_nom>;
4228 interconnect-names = "usb-ddr", "apps-usb";
4230 wakeup-source;
4239 snps,parkmode-disable-ss-quirk;
4241 phy-names = "usb2-phy", "usb3-phy";
4242 maximum-speed = "super-speed";
4245 #address-cells = <1>;
4246 #size-cells = <0>;
4265 venus: video-codec@aa00000 {
4266 compatible = "qcom,sc7280-venus";
4275 clock-names = "core", "bus", "iface",
4278 power-domains = <&videocc MVSC_GDSC>,
4281 power-domain-names = "venus", "vcodec0", "cx";
4282 operating-points-v2 = <&venus_opp_table>;
4286 interconnect-names = "cpu-cfg", "video-mem";
4289 memory-region = <&video_mem>;
4293 video-decoder {
4294 compatible = "venus-decoder";
4297 video-encoder {
4298 compatible = "venus-encoder";
4301 venus_opp_table: opp-table {
4302 compatible = "operating-points-v2";
4304 opp-133330000 {
4305 opp-hz = /bits/ 64 <133330000>;
4306 required-opps = <&rpmhpd_opp_low_svs>;
4309 opp-240000000 {
4310 opp-hz = /bits/ 64 <240000000>;
4311 required-opps = <&rpmhpd_opp_svs>;
4314 opp-335000000 {
4315 opp-hz = /bits/ 64 <335000000>;
4316 required-opps = <&rpmhpd_opp_svs_l1>;
4319 opp-424000000 {
4320 opp-hz = /bits/ 64 <424000000>;
4321 required-opps = <&rpmhpd_opp_nom>;
4324 opp-460000048 {
4325 opp-hz = /bits/ 64 <460000048>;
4326 required-opps = <&rpmhpd_opp_turbo>;
4331 videocc: clock-controller@aaf0000 {
4332 compatible = "qcom,sc7280-videocc";
4336 clock-names = "bi_tcxo", "bi_tcxo_ao";
4337 #clock-cells = <1>;
4338 #reset-cells = <1>;
4339 #power-domain-cells = <1>;
4343 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4346 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4353 clock-names = "camnoc_axi",
4358 pinctrl-0 = <&cci0_default &cci1_default>;
4359 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4360 pinctrl-names = "default", "sleep";
4362 #address-cells = <1>;
4363 #size-cells = <0>;
4367 cci0_i2c0: i2c-bus@0 {
4369 clock-frequency = <1000000>;
4370 #address-cells = <1>;
4371 #size-cells = <0>;
4374 cci0_i2c1: i2c-bus@1 {
4376 clock-frequency = <1000000>;
4377 #address-cells = <1>;
4378 #size-cells = <0>;
4383 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4386 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4393 clock-names = "camnoc_axi",
4398 pinctrl-0 = <&cci2_default &cci3_default>;
4399 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
4400 pinctrl-names = "default", "sleep";
4402 #address-cells = <1>;
4403 #size-cells = <0>;
4407 cci1_i2c0: i2c-bus@0 {
4409 clock-frequency = <1000000>;
4410 #address-cells = <1>;
4411 #size-cells = <0>;
4414 cci1_i2c1: i2c-bus@1 {
4416 clock-frequency = <1000000>;
4417 #address-cells = <1>;
4418 #size-cells = <0>;
4422 camcc: clock-controller@ad00000 {
4423 compatible = "qcom,sc7280-camcc";
4428 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4429 #clock-cells = <1>;
4430 #reset-cells = <1>;
4431 #power-domain-cells = <1>;
4434 dispcc: clock-controller@af00000 {
4435 compatible = "qcom,sc7280-dispcc";
4445 clock-names = "bi_tcxo",
4453 #clock-cells = <1>;
4454 #reset-cells = <1>;
4455 #power-domain-cells = <1>;
4458 mdss: display-subsystem@ae00000 {
4459 compatible = "qcom,sc7280-mdss";
4461 reg-names = "mdss";
4463 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
4468 clock-names = "iface",
4473 interrupt-controller;
4474 #interrupt-cells = <1>;
4480 interconnect-names = "mdp0-mem",
4481 "cpu-cfg";
4485 #address-cells = <2>;
4486 #size-cells = <2>;
4491 mdss_mdp: display-controller@ae01000 {
4492 compatible = "qcom,sc7280-dpu";
4495 reg-names = "mdp", "vbif";
4503 clock-names = "bus",
4509 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
4511 assigned-clock-rates = <19200000>,
4513 operating-points-v2 = <&mdp_opp_table>;
4514 power-domains = <&rpmhpd SC7280_CX>;
4516 interrupt-parent = <&mdss>;
4520 #address-cells = <1>;
4521 #size-cells = <0>;
4526 remote-endpoint = <&mdss_dsi0_in>;
4533 remote-endpoint = <&edp_in>;
4540 remote-endpoint = <&dp_in>;
4545 mdp_opp_table: opp-table {
4546 compatible = "operating-points-v2";
4548 opp-200000000 {
4549 opp-hz = /bits/ 64 <200000000>;
4550 required-opps = <&rpmhpd_opp_low_svs>;
4553 opp-300000000 {
4554 opp-hz = /bits/ 64 <300000000>;
4555 required-opps = <&rpmhpd_opp_svs>;
4558 opp-380000000 {
4559 opp-hz = /bits/ 64 <380000000>;
4560 required-opps = <&rpmhpd_opp_svs_l1>;
4563 opp-506666667 {
4564 opp-hz = /bits/ 64 <506666667>;
4565 required-opps = <&rpmhpd_opp_nom>;
4568 opp-608000000 {
4569 opp-hz = /bits/ 64 <608000000>;
4570 required-opps = <&rpmhpd_opp_turbo>;
4576 compatible = "qcom,sc7280-dsi-ctrl",
4577 "qcom,mdss-dsi-ctrl";
4579 reg-names = "dsi_ctrl";
4581 interrupt-parent = <&mdss>;
4590 clock-names = "byte",
4597 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4598 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
4600 operating-points-v2 = <&dsi_opp_table>;
4601 power-domains = <&rpmhpd SC7280_CX>;
4605 #address-cells = <1>;
4606 #size-cells = <0>;
4611 #address-cells = <1>;
4612 #size-cells = <0>;
4617 remote-endpoint = <&dpu_intf1_out>;
4628 dsi_opp_table: opp-table {
4629 compatible = "operating-points-v2";
4631 opp-187500000 {
4632 opp-hz = /bits/ 64 <187500000>;
4633 required-opps = <&rpmhpd_opp_low_svs>;
4636 opp-300000000 {
4637 opp-hz = /bits/ 64 <300000000>;
4638 required-opps = <&rpmhpd_opp_svs>;
4641 opp-358000000 {
4642 opp-hz = /bits/ 64 <358000000>;
4643 required-opps = <&rpmhpd_opp_svs_l1>;
4649 compatible = "qcom,sc7280-dsi-phy-7nm";
4653 reg-names = "dsi_phy",
4657 #clock-cells = <1>;
4658 #phy-cells = <0>;
4662 clock-names = "iface", "ref";
4668 compatible = "qcom,sc7280-edp";
4669 pinctrl-names = "default";
4670 pinctrl-0 = <&edp_hot_plug_det>;
4677 interrupt-parent = <&mdss>;
4685 clock-names = "core_iface",
4690 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4692 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4695 phy-names = "dp";
4697 operating-points-v2 = <&edp_opp_table>;
4698 power-domains = <&rpmhpd SC7280_CX>;
4703 #address-cells = <1>;
4704 #size-cells = <0>;
4709 remote-endpoint = <&dpu_intf5_out>;
4719 edp_opp_table: opp-table {
4720 compatible = "operating-points-v2";
4722 opp-160000000 {
4723 opp-hz = /bits/ 64 <160000000>;
4724 required-opps = <&rpmhpd_opp_low_svs>;
4727 opp-270000000 {
4728 opp-hz = /bits/ 64 <270000000>;
4729 required-opps = <&rpmhpd_opp_svs>;
4732 opp-540000000 {
4733 opp-hz = /bits/ 64 <540000000>;
4734 required-opps = <&rpmhpd_opp_nom>;
4737 opp-810000000 {
4738 opp-hz = /bits/ 64 <810000000>;
4739 required-opps = <&rpmhpd_opp_nom>;
4745 compatible = "qcom,sc7280-edp-phy";
4754 clock-names = "aux",
4757 #clock-cells = <1>;
4758 #phy-cells = <0>;
4763 mdss_dp: displayport-controller@ae90000 {
4764 compatible = "qcom,sc7280-dp";
4772 interrupt-parent = <&mdss>;
4780 clock-names = "core_iface",
4785 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4787 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4790 phy-names = "dp";
4792 operating-points-v2 = <&dp_opp_table>;
4793 power-domains = <&rpmhpd SC7280_CX>;
4795 #sound-dai-cells = <0>;
4800 #address-cells = <1>;
4801 #size-cells = <0>;
4806 remote-endpoint = <&dpu_intf0_out>;
4816 dp_opp_table: opp-table {
4817 compatible = "operating-points-v2";
4819 opp-160000000 {
4820 opp-hz = /bits/ 64 <160000000>;
4821 required-opps = <&rpmhpd_opp_low_svs>;
4824 opp-270000000 {
4825 opp-hz = /bits/ 64 <270000000>;
4826 required-opps = <&rpmhpd_opp_svs>;
4829 opp-540000000 {
4830 opp-hz = /bits/ 64 <540000000>;
4831 required-opps = <&rpmhpd_opp_svs_l1>;
4834 opp-810000000 {
4835 opp-hz = /bits/ 64 <810000000>;
4836 required-opps = <&rpmhpd_opp_nom>;
4842 pdc: interrupt-controller@b220000 {
4843 compatible = "qcom,sc7280-pdc", "qcom,pdc";
4845 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4850 #interrupt-cells = <2>;
4851 interrupt-parent = <&intc>;
4852 interrupt-controller;
4855 pdc_reset: reset-controller@b5e0000 {
4856 compatible = "qcom,sc7280-pdc-global";
4858 #reset-cells = <1>;
4862 tsens0: thermal-sensor@c263000 {
4863 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4869 interrupt-names = "uplow","critical";
4870 #thermal-sensor-cells = <1>;
4873 tsens1: thermal-sensor@c265000 {
4874 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4880 interrupt-names = "uplow","critical";
4881 #thermal-sensor-cells = <1>;
4884 aoss_reset: reset-controller@c2a0000 {
4885 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4887 #reset-cells = <1>;
4890 aoss_qmp: power-management@c300000 {
4891 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4893 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4899 #clock-cells = <0>;
4903 compatible = "qcom,rpmh-stats";
4908 compatible = "qcom,spmi-pmic-arb";
4914 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4915 interrupt-names = "periph_irq";
4916 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4919 #address-cells = <2>;
4920 #size-cells = <0>;
4921 interrupt-controller;
4922 #interrupt-cells = <4>;
4926 compatible = "qcom,sc7280-pinctrl";
4929 gpio-controller;
4930 #gpio-cells = <2>;
4931 interrupt-controller;
4932 #interrupt-cells = <2>;
4933 gpio-ranges = <&tlmm 0 0 175>;
4934 wakeup-parent = <&pdc>;
4936 cci0_default: cci0-default-state {
4939 drive-strength = <2>;
4940 bias-pull-up;
4943 cci0_sleep: cci0-sleep-state {
4946 drive-strength = <2>;
4947 bias-pull-down;
4950 cci1_default: cci1-default-state {
4953 drive-strength = <2>;
4954 bias-pull-up;
4957 cci1_sleep: cci1-sleep-state {
4960 drive-strength = <2>;
4961 bias-pull-down;
4964 cci2_default: cci2-default-state {
4967 drive-strength = <2>;
4968 bias-pull-up;
4971 cci2_sleep: cci2-sleep-state {
4974 drive-strength = <2>;
4975 bias-pull-down;
4978 cci3_default: cci3-default-state {
4981 drive-strength = <2>;
4982 bias-pull-up;
4985 cci3_sleep: cci3-sleep-state {
4988 drive-strength = <2>;
4989 bias-pull-down;
4992 dp_hot_plug_det: dp-hot-plug-det-state {
4997 edp_hot_plug_det: edp-hot-plug-det-state {
5002 mi2s0_data0: mi2s0-data0-state {
5007 mi2s0_data1: mi2s0-data1-state {
5012 mi2s0_mclk: mi2s0-mclk-state {
5017 mi2s0_sclk: mi2s0-sclk-state {
5022 mi2s0_ws: mi2s0-ws-state {
5027 mi2s1_data0: mi2s1-data0-state {
5032 mi2s1_sclk: mi2s1-sclk-state {
5037 mi2s1_ws: mi2s1-ws-state {
5042 pcie1_clkreq_n: pcie1-clkreq-n-state {
5047 qspi_clk: qspi-clk-state {
5052 qspi_cs0: qspi-cs0-state {
5057 qspi_cs1: qspi-cs1-state {
5062 qspi_data0: qspi-data0-state {
5067 qspi_data1: qspi-data1-state {
5072 qspi_data23: qspi-data23-state {
5077 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5082 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5087 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5092 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5097 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5102 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5107 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5112 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5117 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5122 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5127 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5132 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5137 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5142 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5147 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5152 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5157 qup_spi0_data_clk: qup-spi0-data-clk-state {
5162 qup_spi0_cs: qup-spi0-cs-state {
5167 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5172 qup_spi1_data_clk: qup-spi1-data-clk-state {
5177 qup_spi1_cs: qup-spi1-cs-state {
5182 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5187 qup_spi2_data_clk: qup-spi2-data-clk-state {
5192 qup_spi2_cs: qup-spi2-cs-state {
5197 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5202 qup_spi3_data_clk: qup-spi3-data-clk-state {
5207 qup_spi3_cs: qup-spi3-cs-state {
5212 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5217 qup_spi4_data_clk: qup-spi4-data-clk-state {
5222 qup_spi4_cs: qup-spi4-cs-state {
5227 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5232 qup_spi5_data_clk: qup-spi5-data-clk-state {
5237 qup_spi5_cs: qup-spi5-cs-state {
5242 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5247 qup_spi6_data_clk: qup-spi6-data-clk-state {
5252 qup_spi6_cs: qup-spi6-cs-state {
5257 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5262 qup_spi7_data_clk: qup-spi7-data-clk-state {
5267 qup_spi7_cs: qup-spi7-cs-state {
5272 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5277 qup_spi8_data_clk: qup-spi8-data-clk-state {
5282 qup_spi8_cs: qup-spi8-cs-state {
5287 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5292 qup_spi9_data_clk: qup-spi9-data-clk-state {
5297 qup_spi9_cs: qup-spi9-cs-state {
5302 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5307 qup_spi10_data_clk: qup-spi10-data-clk-state {
5312 qup_spi10_cs: qup-spi10-cs-state {
5317 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5322 qup_spi11_data_clk: qup-spi11-data-clk-state {
5327 qup_spi11_cs: qup-spi11-cs-state {
5332 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5337 qup_spi12_data_clk: qup-spi12-data-clk-state {
5342 qup_spi12_cs: qup-spi12-cs-state {
5347 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5352 qup_spi13_data_clk: qup-spi13-data-clk-state {
5357 qup_spi13_cs: qup-spi13-cs-state {
5362 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5367 qup_spi14_data_clk: qup-spi14-data-clk-state {
5372 qup_spi14_cs: qup-spi14-cs-state {
5377 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5382 qup_spi15_data_clk: qup-spi15-data-clk-state {
5387 qup_spi15_cs: qup-spi15-cs-state {
5392 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5397 qup_uart0_cts: qup-uart0-cts-state {
5402 qup_uart0_rts: qup-uart0-rts-state {
5407 qup_uart0_tx: qup-uart0-tx-state {
5412 qup_uart0_rx: qup-uart0-rx-state {
5417 qup_uart1_cts: qup-uart1-cts-state {
5422 qup_uart1_rts: qup-uart1-rts-state {
5427 qup_uart1_tx: qup-uart1-tx-state {
5432 qup_uart1_rx: qup-uart1-rx-state {
5437 qup_uart2_cts: qup-uart2-cts-state {
5442 qup_uart2_rts: qup-uart2-rts-state {
5447 qup_uart2_tx: qup-uart2-tx-state {
5452 qup_uart2_rx: qup-uart2-rx-state {
5457 qup_uart3_cts: qup-uart3-cts-state {
5462 qup_uart3_rts: qup-uart3-rts-state {
5467 qup_uart3_tx: qup-uart3-tx-state {
5472 qup_uart3_rx: qup-uart3-rx-state {
5477 qup_uart4_cts: qup-uart4-cts-state {
5482 qup_uart4_rts: qup-uart4-rts-state {
5487 qup_uart4_tx: qup-uart4-tx-state {
5492 qup_uart4_rx: qup-uart4-rx-state {
5497 qup_uart5_tx: qup-uart5-tx-state {
5502 qup_uart5_rx: qup-uart5-rx-state {
5507 qup_uart6_cts: qup-uart6-cts-state {
5512 qup_uart6_rts: qup-uart6-rts-state {
5517 qup_uart6_tx: qup-uart6-tx-state {
5522 qup_uart6_rx: qup-uart6-rx-state {
5527 qup_uart7_cts: qup-uart7-cts-state {
5532 qup_uart7_rts: qup-uart7-rts-state {
5537 qup_uart7_tx: qup-uart7-tx-state {
5542 qup_uart7_rx: qup-uart7-rx-state {
5547 qup_uart8_cts: qup-uart8-cts-state {
5552 qup_uart8_rts: qup-uart8-rts-state {
5557 qup_uart8_tx: qup-uart8-tx-state {
5562 qup_uart8_rx: qup-uart8-rx-state {
5567 qup_uart9_cts: qup-uart9-cts-state {
5572 qup_uart9_rts: qup-uart9-rts-state {
5577 qup_uart9_tx: qup-uart9-tx-state {
5582 qup_uart9_rx: qup-uart9-rx-state {
5587 qup_uart10_cts: qup-uart10-cts-state {
5592 qup_uart10_rts: qup-uart10-rts-state {
5597 qup_uart10_tx: qup-uart10-tx-state {
5602 qup_uart10_rx: qup-uart10-rx-state {
5607 qup_uart11_cts: qup-uart11-cts-state {
5612 qup_uart11_rts: qup-uart11-rts-state {
5617 qup_uart11_tx: qup-uart11-tx-state {
5622 qup_uart11_rx: qup-uart11-rx-state {
5627 qup_uart12_cts: qup-uart12-cts-state {
5632 qup_uart12_rts: qup-uart12-rts-state {
5637 qup_uart12_tx: qup-uart12-tx-state {
5642 qup_uart12_rx: qup-uart12-rx-state {
5647 qup_uart13_cts: qup-uart13-cts-state {
5652 qup_uart13_rts: qup-uart13-rts-state {
5657 qup_uart13_tx: qup-uart13-tx-state {
5662 qup_uart13_rx: qup-uart13-rx-state {
5667 qup_uart14_cts: qup-uart14-cts-state {
5672 qup_uart14_rts: qup-uart14-rts-state {
5677 qup_uart14_tx: qup-uart14-tx-state {
5682 qup_uart14_rx: qup-uart14-rx-state {
5687 qup_uart15_cts: qup-uart15-cts-state {
5692 qup_uart15_rts: qup-uart15-rts-state {
5697 qup_uart15_tx: qup-uart15-tx-state {
5702 qup_uart15_rx: qup-uart15-rx-state {
5707 sdc1_clk: sdc1-clk-state {
5711 sdc1_cmd: sdc1-cmd-state {
5715 sdc1_data: sdc1-data-state {
5719 sdc1_rclk: sdc1-rclk-state {
5723 sdc1_clk_sleep: sdc1-clk-sleep-state {
5725 drive-strength = <2>;
5726 bias-bus-hold;
5729 sdc1_cmd_sleep: sdc1-cmd-sleep-state {
5731 drive-strength = <2>;
5732 bias-bus-hold;
5735 sdc1_data_sleep: sdc1-data-sleep-state {
5737 drive-strength = <2>;
5738 bias-bus-hold;
5741 sdc1_rclk_sleep: sdc1-rclk-sleep-state {
5743 drive-strength = <2>;
5744 bias-bus-hold;
5747 sdc2_clk: sdc2-clk-state {
5751 sdc2_cmd: sdc2-cmd-state {
5755 sdc2_data: sdc2-data-state {
5759 sdc2_clk_sleep: sdc2-clk-sleep-state {
5761 drive-strength = <2>;
5762 bias-bus-hold;
5765 sdc2_cmd_sleep: sdc2-cmd-sleep-state {
5767 drive-strength = <2>;
5768 bias-bus-hold;
5771 sdc2_data_sleep: sdc2-data-sleep-state {
5773 drive-strength = <2>;
5774 bias-bus-hold;
5779 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5782 #address-cells = <1>;
5783 #size-cells = <1>;
5787 pil-reloc@594c {
5788 compatible = "qcom,pil-reloc-info";
5794 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5796 #iommu-cells = <2>;
5797 #global-interrupts = <1>;
5798 dma-coherent;
5883 compatible = "qcom,sc7280-tbu";
5887 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
5891 compatible = "qcom,sc7280-tbu";
5895 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
5899 compatible = "qcom,sc7280-tbu";
5903 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
5904 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
5908 compatible = "qcom,sc7280-tbu";
5912 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
5913 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
5917 compatible = "qcom,sc7280-tbu";
5921 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>;
5922 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
5926 compatible = "qcom,sc7280-tbu";
5930 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>;
5931 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
5935 compatible = "qcom,sc7280-tbu";
5939 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
5943 compatible = "qcom,sc7280-tbu";
5947 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
5951 compatible = "qcom,sc7280-tbu";
5955 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>;
5956 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>;
5959 intc: interrupt-controller@17a00000 {
5960 compatible = "arm,gic-v3";
5964 #interrupt-cells = <3>;
5965 interrupt-controller;
5966 #address-cells = <2>;
5967 #size-cells = <2>;
5970 msi-controller@17a40000 {
5971 compatible = "arm,gic-v3-its";
5973 msi-controller;
5974 #msi-cells = <1>;
5980 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5988 #address-cells = <1>;
5989 #size-cells = <1>;
5991 compatible = "arm,armv7-timer-mem";
5995 frame-number = <0>;
6003 frame-number = <1>;
6010 frame-number = <2>;
6017 frame-number = <3>;
6024 frame-number = <4>;
6031 frame-number = <5>;
6038 frame-number = <6>;
6046 compatible = "qcom,rpmh-rsc";
6050 reg-names = "drv-0", "drv-1", "drv-2";
6054 qcom,tcs-offset = <0xd00>;
6055 qcom,drv-id = <2>;
6056 qcom,tcs-config = <ACTIVE_TCS 2>,
6060 power-domains = <&CLUSTER_PD>;
6062 apps_bcm_voter: bcm-voter {
6063 compatible = "qcom,bcm-voter";
6066 rpmhpd: power-controller {
6067 compatible = "qcom,sc7280-rpmhpd";
6068 #power-domain-cells = <1>;
6069 operating-points-v2 = <&rpmhpd_opp_table>;
6071 rpmhpd_opp_table: opp-table {
6072 compatible = "operating-points-v2";
6075 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6079 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6083 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6087 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6091 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
6095 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6099 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6103 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6107 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6112 rpmhcc: clock-controller {
6113 compatible = "qcom,sc7280-rpmh-clk";
6115 clock-names = "xo";
6116 #clock-cells = <1>;
6121 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
6124 clock-names = "xo", "alternate";
6125 #interconnect-cells = <1>;
6129 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
6137 interrupt-names = "dcvsh-irq-0",
6138 "dcvsh-irq-1",
6139 "dcvsh-irq-2";
6142 clock-names = "xo", "alternate";
6143 #freq-domain-cells = <1>;
6144 #clock-cells = <1>;
6151 thermal_zones: thermal-zones {
6152 cpu0-thermal {
6153 polling-delay-passive = <250>;
6155 thermal-sensors = <&tsens0 1>;
6158 cpu0_alert0: trip-point0 {
6164 cpu0_alert1: trip-point1 {
6170 cpu0_crit: cpu-crit {
6177 cooling-maps {
6180 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6187 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6195 cpu1-thermal {
6196 polling-delay-passive = <250>;
6198 thermal-sensors = <&tsens0 2>;
6201 cpu1_alert0: trip-point0 {
6207 cpu1_alert1: trip-point1 {
6213 cpu1_crit: cpu-crit {
6220 cooling-maps {
6223 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6230 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6238 cpu2-thermal {
6239 polling-delay-passive = <250>;
6241 thermal-sensors = <&tsens0 3>;
6244 cpu2_alert0: trip-point0 {
6250 cpu2_alert1: trip-point1 {
6256 cpu2_crit: cpu-crit {
6263 cooling-maps {
6266 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6273 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6281 cpu3-thermal {
6282 polling-delay-passive = <250>;
6284 thermal-sensors = <&tsens0 4>;
6287 cpu3_alert0: trip-point0 {
6293 cpu3_alert1: trip-point1 {
6299 cpu3_crit: cpu-crit {
6306 cooling-maps {
6309 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6316 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6324 cpu4-thermal {
6325 polling-delay-passive = <250>;
6327 thermal-sensors = <&tsens0 7>;
6330 cpu4_alert0: trip-point0 {
6336 cpu4_alert1: trip-point1 {
6342 cpu4_crit: cpu-crit {
6349 cooling-maps {
6352 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6359 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6367 cpu5-thermal {
6368 polling-delay-passive = <250>;
6370 thermal-sensors = <&tsens0 8>;
6373 cpu5_alert0: trip-point0 {
6379 cpu5_alert1: trip-point1 {
6385 cpu5_crit: cpu-crit {
6392 cooling-maps {
6395 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6402 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6410 cpu6-thermal {
6411 polling-delay-passive = <250>;
6413 thermal-sensors = <&tsens0 9>;
6416 cpu6_alert0: trip-point0 {
6422 cpu6_alert1: trip-point1 {
6428 cpu6_crit: cpu-crit {
6435 cooling-maps {
6438 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6445 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6453 cpu7-thermal {
6454 polling-delay-passive = <250>;
6456 thermal-sensors = <&tsens0 10>;
6459 cpu7_alert0: trip-point0 {
6465 cpu7_alert1: trip-point1 {
6471 cpu7_crit: cpu-crit {
6478 cooling-maps {
6481 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6488 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6496 cpu8-thermal {
6497 polling-delay-passive = <250>;
6499 thermal-sensors = <&tsens0 11>;
6502 cpu8_alert0: trip-point0 {
6508 cpu8_alert1: trip-point1 {
6514 cpu8_crit: cpu-crit {
6521 cooling-maps {
6524 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6531 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6539 cpu9-thermal {
6540 polling-delay-passive = <250>;
6542 thermal-sensors = <&tsens0 12>;
6545 cpu9_alert0: trip-point0 {
6551 cpu9_alert1: trip-point1 {
6557 cpu9_crit: cpu-crit {
6564 cooling-maps {
6567 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6574 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6582 cpu10-thermal {
6583 polling-delay-passive = <250>;
6585 thermal-sensors = <&tsens0 13>;
6588 cpu10_alert0: trip-point0 {
6594 cpu10_alert1: trip-point1 {
6600 cpu10_crit: cpu-crit {
6607 cooling-maps {
6610 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6617 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6625 cpu11-thermal {
6626 polling-delay-passive = <250>;
6628 thermal-sensors = <&tsens0 14>;
6631 cpu11_alert0: trip-point0 {
6637 cpu11_alert1: trip-point1 {
6643 cpu11_crit: cpu-crit {
6650 cooling-maps {
6653 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6660 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6668 aoss0-thermal {
6669 polling-delay-passive = <0>;
6671 thermal-sensors = <&tsens0 0>;
6674 aoss0_alert0: trip-point0 {
6680 aoss0_crit: aoss0-crit {
6688 aoss1-thermal {
6689 polling-delay-passive = <0>;
6691 thermal-sensors = <&tsens1 0>;
6694 aoss1_alert0: trip-point0 {
6700 aoss1_crit: aoss1-crit {
6708 cpuss0-thermal {
6709 polling-delay-passive = <0>;
6711 thermal-sensors = <&tsens0 5>;
6714 cpuss0_alert0: trip-point0 {
6719 cpuss0_crit: cluster0-crit {
6727 cpuss1-thermal {
6728 polling-delay-passive = <0>;
6730 thermal-sensors = <&tsens0 6>;
6733 cpuss1_alert0: trip-point0 {
6738 cpuss1_crit: cluster0-crit {
6746 gpuss0-thermal {
6747 polling-delay-passive = <100>;
6749 thermal-sensors = <&tsens1 1>;
6752 gpuss0_alert0: trip-point0 {
6758 gpuss0_crit: gpuss0-crit {
6765 cooling-maps {
6768 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6773 gpuss1-thermal {
6774 polling-delay-passive = <100>;
6776 thermal-sensors = <&tsens1 2>;
6779 gpuss1_alert0: trip-point0 {
6785 gpuss1_crit: gpuss1-crit {
6792 cooling-maps {
6795 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6800 nspss0-thermal {
6801 thermal-sensors = <&tsens1 3>;
6804 nspss0_alert0: trip-point0 {
6810 nspss0_crit: nspss0-crit {
6818 nspss1-thermal {
6819 thermal-sensors = <&tsens1 4>;
6822 nspss1_alert0: trip-point0 {
6828 nspss1_crit: nspss1-crit {
6836 video-thermal {
6837 thermal-sensors = <&tsens1 5>;
6840 video_alert0: trip-point0 {
6846 video_crit: video-crit {
6854 ddr-thermal {
6855 thermal-sensors = <&tsens1 6>;
6858 ddr_alert0: trip-point0 {
6864 ddr_crit: ddr-crit {
6872 mdmss0-thermal {
6873 thermal-sensors = <&tsens1 7>;
6876 mdmss0_alert0: trip-point0 {
6882 mdmss0_crit: mdmss0-crit {
6890 mdmss1-thermal {
6891 thermal-sensors = <&tsens1 8>;
6894 mdmss1_alert0: trip-point0 {
6900 mdmss1_crit: mdmss1-crit {
6908 mdmss2-thermal {
6909 thermal-sensors = <&tsens1 9>;
6912 mdmss2_alert0: trip-point0 {
6918 mdmss2_crit: mdmss2-crit {
6926 mdmss3-thermal {
6927 thermal-sensors = <&tsens1 10>;
6930 mdmss3_alert0: trip-point0 {
6936 mdmss3_crit: mdmss3-crit {
6944 camera0-thermal {
6945 thermal-sensors = <&tsens1 11>;
6948 camera0_alert0: trip-point0 {
6954 camera0_crit: camera0-crit {
6964 compatible = "arm,armv8-timer";