Lines Matching +full:opp +full:- +full:v2 +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h>
14 interrupt-parent = <&intc>;
16 qcom,msm-id = <292 0x0>;
18 #address-cells = <2>;
19 #size-cells = <2>;
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
36 no-map;
41 no-map;
44 smem_mem: smem-mem@86000000 {
46 no-map;
51 no-map;
55 compatible = "qcom,rmtfs-mem";
57 no-map;
59 qcom,client-id = <1>;
65 no-map;
70 no-map;
75 no-map;
80 no-map;
85 no-map;
90 no-map;
95 no-map;
100 no-map;
105 no-map;
110 no-map;
113 mdata_mem: mpss-metadata {
114 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
116 no-map;
121 xo: xo-board {
122 compatible = "fixed-clock";
123 #clock-cells = <0>;
124 clock-frequency = <19200000>;
125 clock-output-names = "xo_board";
128 sleep_clk: sleep-clk {
129 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 clock-frequency = <32764>;
136 #address-cells = <2>;
137 #size-cells = <0>;
143 enable-method = "psci";
144 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L2_0>;
147 L2_0: l2-cache {
149 cache-level = <2>;
150 cache-unified;
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L2_0>;
168 enable-method = "psci";
169 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L2_0>;
178 enable-method = "psci";
179 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L2_0>;
188 enable-method = "psci";
189 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L2_1>;
192 L2_1: l2-cache {
194 cache-level = <2>;
195 cache-unified;
203 enable-method = "psci";
204 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L2_1>;
213 enable-method = "psci";
214 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L2_1>;
223 enable-method = "psci";
224 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L2_1>;
229 cpu-map {
267 idle-states {
268 entry-method = "psci";
270 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = "arm,idle-state";
272 idle-state-name = "little-retention";
274 arm,psci-suspend-param = <0x00000002>;
275 entry-latency-us = <81>;
276 exit-latency-us = <86>;
277 min-residency-us = <504>;
280 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = "arm,idle-state";
282 idle-state-name = "little-power-collapse";
284 arm,psci-suspend-param = <0x40000003>;
285 entry-latency-us = <814>;
286 exit-latency-us = <4562>;
287 min-residency-us = <9183>;
288 local-timer-stop;
291 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = "arm,idle-state";
293 idle-state-name = "big-retention";
295 arm,psci-suspend-param = <0x00000002>;
296 entry-latency-us = <79>;
297 exit-latency-us = <82>;
298 min-residency-us = <1302>;
301 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = "arm,idle-state";
303 idle-state-name = "big-power-collapse";
305 arm,psci-suspend-param = <0x40000003>;
306 entry-latency-us = <724>;
307 exit-latency-us = <2027>;
308 min-residency-us = <9419>;
309 local-timer-stop;
316 compatible = "qcom,scm-msm8998", "qcom,scm";
320 dsi_opp_table: opp-table-dsi {
321 compatible = "operating-points-v2";
323 opp-131250000 {
324 opp-hz = /bits/ 64 <131250000>;
325 required-opps = <&rpmpd_opp_low_svs>;
328 opp-210000000 {
329 opp-hz = /bits/ 64 <210000000>;
330 required-opps = <&rpmpd_opp_svs>;
333 opp-312500000 {
334 opp-hz = /bits/ 64 <312500000>;
335 required-opps = <&rpmpd_opp_nom>;
340 compatible = "arm,psci-1.0";
345 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
347 glink-edge {
348 compatible = "qcom,glink-rpm";
351 qcom,rpm-msg-ram = <&rpm_msg_ram>;
354 rpm_requests: rpm-requests {
355 compatible = "qcom,rpm-msm8998", "qcom,glink-smd-rpm";
356 qcom,glink-channels = "rpm_requests";
358 rpmcc: clock-controller {
359 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
361 clock-names = "xo";
362 #clock-cells = <1>;
365 rpmpd: power-controller {
366 compatible = "qcom,msm8998-rpmpd";
367 #power-domain-cells = <1>;
368 operating-points-v2 = <&rpmpd_opp_table>;
370 rpmpd_opp_table: opp-table {
371 compatible = "operating-points-v2";
374 opp-level = <RPM_SMD_LEVEL_RETENTION>;
378 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
382 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
386 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
390 opp-level = <RPM_SMD_LEVEL_SVS>;
394 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
398 opp-level = <RPM_SMD_LEVEL_NOM>;
402 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
406 opp-level = <RPM_SMD_LEVEL_TURBO>;
410 opp-level = <RPM_SMD_LEVEL_BINNING>;
420 memory-region = <&smem_mem>;
424 smp2p-lpass {
432 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>;
435 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells = <1>;
440 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "slave-kernel";
443 interrupt-controller;
444 #interrupt-cells = <2>;
448 smp2p-mpss {
453 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>;
456 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells = <1>;
461 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "slave-kernel";
463 interrupt-controller;
464 #interrupt-cells = <2>;
468 smp2p-slpi {
473 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>;
476 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells = <1>;
481 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "slave-kernel";
483 interrupt-controller;
484 #interrupt-cells = <2>;
488 thermal-zones {
489 cpu0-thermal {
490 polling-delay-passive = <250>;
492 thermal-sensors = <&tsens0 1>;
495 cpu0_alert0: trip-point0 {
501 cpu0_crit: cpu-crit {
509 cpu1-thermal {
510 polling-delay-passive = <250>;
512 thermal-sensors = <&tsens0 2>;
515 cpu1_alert0: trip-point0 {
521 cpu1_crit: cpu-crit {
529 cpu2-thermal {
530 polling-delay-passive = <250>;
532 thermal-sensors = <&tsens0 3>;
535 cpu2_alert0: trip-point0 {
541 cpu2_crit: cpu-crit {
549 cpu3-thermal {
550 polling-delay-passive = <250>;
552 thermal-sensors = <&tsens0 4>;
555 cpu3_alert0: trip-point0 {
561 cpu3_crit: cpu-crit {
569 cpu4-thermal {
570 polling-delay-passive = <250>;
572 thermal-sensors = <&tsens0 7>;
575 cpu4_alert0: trip-point0 {
581 cpu4_crit: cpu-crit {
589 cpu5-thermal {
590 polling-delay-passive = <250>;
592 thermal-sensors = <&tsens0 8>;
595 cpu5_alert0: trip-point0 {
601 cpu5_crit: cpu-crit {
609 cpu6-thermal {
610 polling-delay-passive = <250>;
612 thermal-sensors = <&tsens0 9>;
615 cpu6_alert0: trip-point0 {
621 cpu6_crit: cpu-crit {
629 cpu7-thermal {
630 polling-delay-passive = <250>;
632 thermal-sensors = <&tsens0 10>;
635 cpu7_alert0: trip-point0 {
641 cpu7_crit: cpu-crit {
649 gpu-bottom-thermal {
650 polling-delay-passive = <250>;
652 thermal-sensors = <&tsens0 12>;
655 gpu1_alert0: trip-point0 {
663 gpu-top-thermal {
664 polling-delay-passive = <250>;
666 thermal-sensors = <&tsens0 13>;
669 gpu2_alert0: trip-point0 {
677 clust0-mhm-thermal {
678 polling-delay-passive = <250>;
680 thermal-sensors = <&tsens0 5>;
683 cluster0_mhm_alert0: trip-point0 {
691 clust1-mhm-thermal {
692 polling-delay-passive = <250>;
694 thermal-sensors = <&tsens0 6>;
697 cluster1_mhm_alert0: trip-point0 {
705 cluster1-l2-thermal {
706 polling-delay-passive = <250>;
708 thermal-sensors = <&tsens0 11>;
711 cluster1_l2_alert0: trip-point0 {
719 modem-thermal {
720 polling-delay-passive = <250>;
722 thermal-sensors = <&tsens1 1>;
725 modem_alert0: trip-point0 {
733 mem-thermal {
734 polling-delay-passive = <250>;
736 thermal-sensors = <&tsens1 2>;
739 mem_alert0: trip-point0 {
747 wlan-thermal {
748 polling-delay-passive = <250>;
750 thermal-sensors = <&tsens1 3>;
753 wlan_alert0: trip-point0 {
761 q6-dsp-thermal {
762 polling-delay-passive = <250>;
764 thermal-sensors = <&tsens1 4>;
767 q6_dsp_alert0: trip-point0 {
775 camera-thermal {
776 polling-delay-passive = <250>;
778 thermal-sensors = <&tsens1 5>;
781 camera_alert0: trip-point0 {
789 multimedia-thermal {
790 polling-delay-passive = <250>;
792 thermal-sensors = <&tsens1 6>;
795 multimedia_alert0: trip-point0 {
805 compatible = "arm,armv8-timer";
813 #address-cells = <1>;
814 #size-cells = <1>;
816 compatible = "simple-bus";
818 gcc: clock-controller@100000 {
819 compatible = "qcom,gcc-msm8998";
820 #clock-cells = <1>;
821 #reset-cells = <1>;
822 #power-domain-cells = <1>;
825 clock-names = "xo", "sleep_clk";
830 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
832 * enabled but unused during boot-up), the device will most likely decide
835 * as protected. The board dts (or a user-supplied dts) can override the
839 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
845 compatible = "qcom,rpm-msg-ram";
850 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
852 #address-cells = <1>;
853 #size-cells = <1>;
855 qusb2_hstx_trim: hstx-trim@23a {
862 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
868 interrupt-names = "uplow", "critical";
869 #thermal-sensor-cells = <1>;
873 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
879 interrupt-names = "uplow", "critical";
880 #thermal-sensor-cells = <1>;
884 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
886 #iommu-cells = <1>;
888 #global-interrupts = <0>;
899 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
901 #iommu-cells = <1>;
903 #global-interrupts = <0>;
918 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
923 reg-names = "parf", "dbi", "elbi", "config";
925 linux,pci-domain = <0>;
926 bus-range = <0x00 0xff>;
927 #address-cells = <3>;
928 #size-cells = <2>;
929 num-lanes = <1>;
931 phy-names = "pciephy";
937 #interrupt-cells = <1>;
939 interrupt-names = "msi";
940 interrupt-map-mask = <0 0 0 0x7>;
941 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
951 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
953 power-domains = <&gcc PCIE_0_GDSC>;
954 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
960 bus-range = <0x01 0xff>;
962 #address-cells = <3>;
963 #size-cells = <2>;
969 compatible = "qcom,msm8998-qmp-pcie-phy";
977 clock-names = "aux",
982 clock-output-names = "pcie_0_pipe_clk_src";
983 #clock-cells = <0>;
985 #phy-cells = <0>;
988 reset-names = "phy", "common";
990 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vreg_l2a_1p2>;
995 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
999 phy-names = "ufsphy";
1000 lanes-per-direction = <2>;
1001 power-domains = <&gcc UFS_GDSC>;
1003 #reset-cells = <1>;
1005 clock-names =
1023 freq-table-hz =
1034 reset-names = "rst";
1038 compatible = "qcom,msm8998-qmp-ufs-phy";
1044 clock-names = "ref",
1048 reset-names = "ufsphy";
1051 #phy-cells = <0>;
1056 compatible = "qcom,tcsr-mutex";
1058 #hwlock-cells = <1>;
1062 compatible = "qcom,msm8998-tcsr", "syscon";
1067 compatible = "qcom,msm8998-tcsr", "syscon";
1072 compatible = "qcom,msm8998-pinctrl";
1075 gpio-ranges = <&tlmm 0 0 150>;
1076 gpio-controller;
1077 #gpio-cells = <2>;
1078 interrupt-controller;
1079 #interrupt-cells = <2>;
1081 sdc2_on: sdc2-on-state {
1082 clk-pins {
1084 drive-strength = <16>;
1085 bias-disable;
1088 cmd-pins {
1090 drive-strength = <10>;
1091 bias-pull-up;
1094 data-pins {
1096 drive-strength = <10>;
1097 bias-pull-up;
1101 sdc2_off: sdc2-off-state {
1102 clk-pins {
1104 drive-strength = <2>;
1105 bias-disable;
1108 cmd-pins {
1110 drive-strength = <2>;
1111 bias-pull-up;
1114 data-pins {
1116 drive-strength = <2>;
1117 bias-pull-up;
1121 sdc2_cd: sdc2-cd-state {
1124 bias-pull-up;
1125 drive-strength = <2>;
1128 blsp1_uart3_on: blsp1-uart3-on-state {
1129 tx-pins {
1132 drive-strength = <2>;
1133 bias-disable;
1136 rx-pins {
1139 drive-strength = <2>;
1140 bias-disable;
1143 cts-pins {
1146 drive-strength = <2>;
1147 bias-disable;
1150 rfr-pins {
1153 drive-strength = <2>;
1154 bias-disable;
1158 blsp1_i2c1_default: blsp1-i2c1-default-state {
1161 drive-strength = <2>;
1162 bias-disable;
1165 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1168 drive-strength = <2>;
1169 bias-pull-up;
1172 blsp1_i2c2_default: blsp1-i2c2-default-state {
1175 drive-strength = <2>;
1176 bias-disable;
1179 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1182 drive-strength = <2>;
1183 bias-pull-up;
1186 blsp1_i2c3_default: blsp1-i2c3-default-state {
1189 drive-strength = <2>;
1190 bias-disable;
1193 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1196 drive-strength = <2>;
1197 bias-pull-up;
1200 blsp1_i2c4_default: blsp1-i2c4-default-state {
1203 drive-strength = <2>;
1204 bias-disable;
1207 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1210 drive-strength = <2>;
1211 bias-pull-up;
1214 blsp1_i2c5_default: blsp1-i2c5-default-state {
1217 drive-strength = <2>;
1218 bias-disable;
1221 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1224 drive-strength = <2>;
1225 bias-pull-up;
1228 blsp1_i2c6_default: blsp1-i2c6-default-state {
1231 drive-strength = <2>;
1232 bias-disable;
1235 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1238 drive-strength = <2>;
1239 bias-pull-up;
1242 blsp1_spi_b_default: blsp1-spi-b-default-state {
1245 drive-strength = <6>;
1246 bias-disable;
1249 blsp1_spi1_default: blsp1-spi1-default-state {
1252 drive-strength = <6>;
1253 bias-disable;
1256 blsp1_spi2_default: blsp1-spi2-default-state {
1259 drive-strength = <6>;
1260 bias-disable;
1263 blsp1_spi3_default: blsp1-spi3-default-state {
1266 drive-strength = <6>;
1267 bias-disable;
1270 blsp1_spi4_default: blsp1-spi4-default-state {
1273 drive-strength = <6>;
1274 bias-disable;
1277 blsp1_spi5_default: blsp1-spi5-default-state {
1280 drive-strength = <6>;
1281 bias-disable;
1284 blsp1_spi6_default: blsp1-spi6-default-state {
1287 drive-strength = <6>;
1288 bias-disable;
1293 blsp2_i2c1_default: blsp2-i2c1-default-state {
1296 drive-strength = <2>;
1297 bias-disable;
1300 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1303 drive-strength = <2>;
1304 bias-pull-up;
1307 blsp2_i2c2_default: blsp2-i2c2-default-state {
1310 drive-strength = <2>;
1311 bias-disable;
1314 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1317 drive-strength = <2>;
1318 bias-pull-up;
1321 blsp2_i2c3_default: blsp2-i2c3-default-state {
1324 drive-strength = <2>;
1325 bias-disable;
1328 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1331 drive-strength = <2>;
1332 bias-pull-up;
1335 blsp2_i2c4_default: blsp2-i2c4-default-state {
1338 drive-strength = <2>;
1339 bias-disable;
1342 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1345 drive-strength = <2>;
1346 bias-pull-up;
1349 blsp2_i2c5_default: blsp2-i2c5-default-state {
1352 drive-strength = <2>;
1353 bias-disable;
1356 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1359 drive-strength = <2>;
1360 bias-pull-up;
1363 blsp2_i2c6_default: blsp2-i2c6-default-state {
1366 drive-strength = <2>;
1367 bias-disable;
1370 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1373 drive-strength = <2>;
1374 bias-pull-up;
1377 blsp2_spi1_default: blsp2-spi1-default-state {
1380 drive-strength = <6>;
1381 bias-disable;
1384 blsp2_spi2_default: blsp2-spi2-default-state {
1387 drive-strength = <6>;
1388 bias-disable;
1391 blsp2_spi3_default: blsp2-spi3-default-state {
1394 drive-strength = <6>;
1395 bias-disable;
1398 blsp2_spi4_default: blsp2-spi4-default-state {
1401 drive-strength = <6>;
1402 bias-disable;
1405 blsp2_spi5_default: blsp2-spi5-default-state {
1408 drive-strength = <6>;
1409 bias-disable;
1412 blsp2_spi6_default: blsp2-spi6-default-state {
1415 drive-strength = <6>;
1416 bias-disable;
1421 compatible = "qcom,msm8998-mss-pil";
1423 reg-names = "qdsp6", "rmb";
1425 interrupts-extended =
1432 interrupt-names = "wdog", "fatal", "ready",
1433 "handover", "stop-ack",
1434 "shutdown-ack";
1444 clock-names = "iface", "bus", "mem", "gpll0_mss",
1447 qcom,smem-states = <&modem_smp2p_out 0>;
1448 qcom,smem-state-names = "stop";
1451 reset-names = "mss_restart";
1453 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1455 power-domains = <&rpmpd MSM8998_VDDCX>,
1457 power-domain-names = "cx", "mx";
1462 memory-region = <&mba_mem>;
1466 memory-region = <&mpss_mem>;
1470 memory-region = <&mdata_mem>;
1473 glink-edge {
1476 qcom,remote-pid = <1>;
1482 compatible = "qcom,adreno-540.1", "qcom,adreno";
1484 reg-names = "kgsl_3d0_reg_memory";
1492 clock-names = "iface",
1501 operating-points-v2 = <&gpu_opp_table>;
1502 power-domains = <&rpmpd MSM8998_VDDMX>;
1505 gpu_opp_table: opp-table {
1506 compatible = "operating-points-v2";
1507 opp-710000097 {
1508 opp-hz = /bits/ 64 <710000097>;
1509 opp-level = <RPM_SMD_LEVEL_TURBO>;
1510 opp-supported-hw = <0xff>;
1513 opp-670000048 {
1514 opp-hz = /bits/ 64 <670000048>;
1515 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1516 opp-supported-hw = <0xff>;
1519 opp-596000097 {
1520 opp-hz = /bits/ 64 <596000097>;
1521 opp-level = <RPM_SMD_LEVEL_NOM>;
1522 opp-supported-hw = <0xff>;
1525 opp-515000097 {
1526 opp-hz = /bits/ 64 <515000097>;
1527 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1528 opp-supported-hw = <0xff>;
1531 opp-414000000 {
1532 opp-hz = /bits/ 64 <414000000>;
1533 opp-level = <RPM_SMD_LEVEL_SVS>;
1534 opp-supported-hw = <0xff>;
1537 opp-342000000 {
1538 opp-hz = /bits/ 64 <342000000>;
1539 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1540 opp-supported-hw = <0xff>;
1543 opp-257000000 {
1544 opp-hz = /bits/ 64 <257000000>;
1545 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1546 opp-supported-hw = <0xff>;
1552 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1557 clock-names = "iface", "mem", "mem_iface";
1559 #global-interrupts = <0>;
1560 #iommu-cells = <1>;
1566 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1567 * GPU-CX for SMMU but we need both of them up for Adreno.
1573 power-domains = <&gpucc GPU_GX_GDSC>;
1576 gpucc: clock-controller@5065000 {
1577 compatible = "qcom,msm8998-gpucc";
1578 #clock-cells = <1>;
1579 #reset-cells = <1>;
1580 #power-domain-cells = <1>;
1585 clock-names = "xo",
1590 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1593 clock-names = "bus";
1595 #global-interrupts = <0>;
1596 #iommu-cells = <1>;
1612 power-domains = <&gcc LPASS_ADSP_GDSC>;
1617 compatible = "qcom,msm8998-slpi-pas";
1620 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1625 interrupt-names = "wdog", "fatal", "ready",
1626 "handover", "stop-ack";
1628 px-supply = <&vreg_lvs2a_1p8>;
1631 clock-names = "xo";
1633 memory-region = <&slpi_mem>;
1635 qcom,smem-states = <&slpi_smp2p_out 0>;
1636 qcom,smem-state-names = "stop";
1638 power-domains = <&rpmpd MSM8998_SSCCX>;
1639 power-domain-names = "ssc_cx";
1643 glink-edge {
1646 qcom,remote-pid = <3>;
1652 compatible = "arm,coresight-stm", "arm,primecell";
1655 reg-names = "stm-base", "stm-stimulus-base";
1659 clock-names = "apb_pclk", "atclk";
1661 out-ports {
1664 remote-endpoint = <&funnel0_in7>;
1671 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1676 clock-names = "apb_pclk", "atclk";
1678 out-ports {
1681 remote-endpoint =
1687 in-ports {
1688 #address-cells = <1>;
1689 #size-cells = <0>;
1694 remote-endpoint = <&stm_out>;
1701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1706 clock-names = "apb_pclk", "atclk";
1708 out-ports {
1711 remote-endpoint =
1717 in-ports {
1718 #address-cells = <1>;
1719 #size-cells = <0>;
1724 remote-endpoint =
1732 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1737 clock-names = "apb_pclk", "atclk";
1739 out-ports {
1742 remote-endpoint =
1748 in-ports {
1749 #address-cells = <1>;
1750 #size-cells = <0>;
1755 remote-endpoint =
1763 remote-endpoint =
1771 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1776 clock-names = "apb_pclk", "atclk";
1778 out-ports {
1781 remote-endpoint = <&etr_in>;
1786 in-ports {
1789 remote-endpoint = <&etf_out>;
1796 compatible = "arm,coresight-tmc", "arm,primecell";
1801 clock-names = "apb_pclk", "atclk";
1803 out-ports {
1806 remote-endpoint =
1812 in-ports {
1815 remote-endpoint =
1823 compatible = "arm,coresight-tmc", "arm,primecell";
1828 clock-names = "apb_pclk", "atclk";
1829 arm,scatter-gather;
1831 in-ports {
1834 remote-endpoint =
1842 compatible = "arm,coresight-etm4x", "arm,primecell";
1847 clock-names = "apb_pclk", "atclk";
1851 out-ports {
1854 remote-endpoint =
1862 compatible = "arm,coresight-etm4x", "arm,primecell";
1867 clock-names = "apb_pclk", "atclk";
1871 out-ports {
1874 remote-endpoint =
1882 compatible = "arm,coresight-etm4x", "arm,primecell";
1887 clock-names = "apb_pclk", "atclk";
1891 out-ports {
1894 remote-endpoint =
1902 compatible = "arm,coresight-etm4x", "arm,primecell";
1907 clock-names = "apb_pclk", "atclk";
1911 out-ports {
1914 remote-endpoint =
1922 compatible = "arm,coresight-etm4x", "arm,primecell";
1927 clock-names = "apb_pclk", "atclk";
1929 out-ports {
1932 remote-endpoint =
1938 in-ports {
1939 #address-cells = <1>;
1940 #size-cells = <0>;
1945 remote-endpoint =
1953 remote-endpoint =
1961 remote-endpoint =
1969 remote-endpoint =
1977 remote-endpoint =
1985 remote-endpoint =
1993 remote-endpoint =
2001 remote-endpoint =
2009 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2014 clock-names = "apb_pclk", "atclk";
2016 out-ports {
2019 remote-endpoint =
2025 in-ports {
2028 remote-endpoint =
2036 compatible = "arm,coresight-etm4x", "arm,primecell";
2041 clock-names = "apb_pclk", "atclk";
2045 out-ports {
2048 remote-endpoint = <&apss_funnel_in4>;
2055 compatible = "arm,coresight-etm4x", "arm,primecell";
2060 clock-names = "apb_pclk", "atclk";
2064 out-ports {
2067 remote-endpoint = <&apss_funnel_in5>;
2074 compatible = "arm,coresight-etm4x", "arm,primecell";
2079 clock-names = "apb_pclk", "atclk";
2083 out-ports {
2086 remote-endpoint = <&apss_funnel_in6>;
2093 compatible = "arm,coresight-etm4x", "arm,primecell";
2098 clock-names = "apb_pclk", "atclk";
2102 out-ports {
2105 remote-endpoint = <&apss_funnel_in7>;
2112 compatible = "qcom,rpm-stats";
2117 compatible = "qcom,spmi-pmic-arb";
2123 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124 interrupt-names = "periph_irq";
2128 #address-cells = <2>;
2129 #size-cells = <0>;
2130 interrupt-controller;
2131 #interrupt-cells = <4>;
2135 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2138 #address-cells = <1>;
2139 #size-cells = <1>;
2147 clock-names = "cfg_noc",
2153 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2155 assigned-clock-rates = <19200000>, <120000000>;
2160 interrupt-names = "pwr_event",
2164 power-domains = <&gcc USB_30_GDSC>;
2174 snps,parkmode-disable-ss-quirk;
2176 phy-names = "usb2-phy", "usb3-phy";
2177 snps,has-lpm-erratum;
2178 snps,hird-threshold = /bits/ 8 <0x10>;
2183 compatible = "qcom,msm8998-qmp-usb3-phy";
2190 clock-names = "aux",
2194 clock-output-names = "usb3_phy_pipe_clk_src";
2195 #clock-cells = <0>;
2196 #phy-cells = <0>;
2200 reset-names = "phy",
2203 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
2209 compatible = "qcom,msm8998-qusb2-phy";
2212 #phy-cells = <0>;
2216 clock-names = "cfg_ahb", "ref";
2220 nvmem-cells = <&qusb2_hstx_trim>;
2224 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2226 reg-names = "hc", "core";
2230 interrupt-names = "hc_irq", "pwr_irq";
2232 clock-names = "iface", "core", "xo";
2236 bus-width = <4>;
2240 blsp1_dma: dma-controller@c144000 {
2241 compatible = "qcom,bam-v1.7.0";
2245 clock-names = "bam_clk";
2246 #dma-cells = <1>;
2248 qcom,controlled-remotely;
2249 num-channels = <18>;
2250 qcom,num-ees = <4>;
2254 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2259 clock-names = "core", "iface";
2261 dma-names = "tx", "rx";
2262 pinctrl-names = "default";
2263 pinctrl-0 = <&blsp1_uart3_on>;
2268 compatible = "qcom,i2c-qup-v2.2.1";
2274 clock-names = "core", "iface";
2276 dma-names = "tx", "rx";
2277 pinctrl-names = "default", "sleep";
2278 pinctrl-0 = <&blsp1_i2c1_default>;
2279 pinctrl-1 = <&blsp1_i2c1_sleep>;
2280 clock-frequency = <400000>;
2283 #address-cells = <1>;
2284 #size-cells = <0>;
2288 compatible = "qcom,i2c-qup-v2.2.1";
2294 clock-names = "core", "iface";
2296 dma-names = "tx", "rx";
2297 pinctrl-names = "default", "sleep";
2298 pinctrl-0 = <&blsp1_i2c2_default>;
2299 pinctrl-1 = <&blsp1_i2c2_sleep>;
2300 clock-frequency = <400000>;
2303 #address-cells = <1>;
2304 #size-cells = <0>;
2308 compatible = "qcom,i2c-qup-v2.2.1";
2314 clock-names = "core", "iface";
2316 dma-names = "tx", "rx";
2317 pinctrl-names = "default", "sleep";
2318 pinctrl-0 = <&blsp1_i2c3_default>;
2319 pinctrl-1 = <&blsp1_i2c3_sleep>;
2320 clock-frequency = <400000>;
2323 #address-cells = <1>;
2324 #size-cells = <0>;
2328 compatible = "qcom,i2c-qup-v2.2.1";
2334 clock-names = "core", "iface";
2336 dma-names = "tx", "rx";
2337 pinctrl-names = "default", "sleep";
2338 pinctrl-0 = <&blsp1_i2c4_default>;
2339 pinctrl-1 = <&blsp1_i2c4_sleep>;
2340 clock-frequency = <400000>;
2343 #address-cells = <1>;
2344 #size-cells = <0>;
2348 compatible = "qcom,i2c-qup-v2.2.1";
2354 clock-names = "core", "iface";
2356 dma-names = "tx", "rx";
2357 pinctrl-names = "default", "sleep";
2358 pinctrl-0 = <&blsp1_i2c5_default>;
2359 pinctrl-1 = <&blsp1_i2c5_sleep>;
2360 clock-frequency = <400000>;
2363 #address-cells = <1>;
2364 #size-cells = <0>;
2368 compatible = "qcom,i2c-qup-v2.2.1";
2374 clock-names = "core", "iface";
2376 dma-names = "tx", "rx";
2377 pinctrl-names = "default", "sleep";
2378 pinctrl-0 = <&blsp1_i2c6_default>;
2379 pinctrl-1 = <&blsp1_i2c6_sleep>;
2380 clock-frequency = <400000>;
2383 #address-cells = <1>;
2384 #size-cells = <0>;
2388 compatible = "qcom,spi-qup-v2.2.1";
2394 clock-names = "core", "iface";
2396 dma-names = "tx", "rx";
2397 pinctrl-names = "default";
2398 pinctrl-0 = <&blsp1_spi1_default>;
2401 #address-cells = <1>;
2402 #size-cells = <0>;
2406 compatible = "qcom,spi-qup-v2.2.1";
2412 clock-names = "core", "iface";
2414 dma-names = "tx", "rx";
2415 pinctrl-names = "default";
2416 pinctrl-0 = <&blsp1_spi2_default>;
2419 #address-cells = <1>;
2420 #size-cells = <0>;
2424 compatible = "qcom,spi-qup-v2.2.1";
2430 clock-names = "core", "iface";
2432 dma-names = "tx", "rx";
2433 pinctrl-names = "default";
2434 pinctrl-0 = <&blsp1_spi3_default>;
2437 #address-cells = <1>;
2438 #size-cells = <0>;
2442 compatible = "qcom,spi-qup-v2.2.1";
2448 clock-names = "core", "iface";
2450 dma-names = "tx", "rx";
2451 pinctrl-names = "default";
2452 pinctrl-0 = <&blsp1_spi4_default>;
2455 #address-cells = <1>;
2456 #size-cells = <0>;
2460 compatible = "qcom,spi-qup-v2.2.1";
2466 clock-names = "core", "iface";
2468 dma-names = "tx", "rx";
2469 pinctrl-names = "default";
2470 pinctrl-0 = <&blsp1_spi5_default>;
2473 #address-cells = <1>;
2474 #size-cells = <0>;
2478 compatible = "qcom,spi-qup-v2.2.1";
2484 clock-names = "core", "iface";
2486 dma-names = "tx", "rx";
2487 pinctrl-names = "default";
2488 pinctrl-0 = <&blsp1_spi6_default>;
2491 #address-cells = <1>;
2492 #size-cells = <0>;
2495 blsp2_dma: dma-controller@c184000 {
2496 compatible = "qcom,bam-v1.7.0";
2500 clock-names = "bam_clk";
2501 #dma-cells = <1>;
2503 qcom,controlled-remotely;
2504 num-channels = <18>;
2505 qcom,num-ees = <4>;
2509 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2514 clock-names = "core", "iface";
2519 compatible = "qcom,i2c-qup-v2.2.1";
2525 clock-names = "core", "iface";
2527 dma-names = "tx", "rx";
2528 pinctrl-names = "default", "sleep";
2529 pinctrl-0 = <&blsp2_i2c1_default>;
2530 pinctrl-1 = <&blsp2_i2c1_sleep>;
2531 clock-frequency = <400000>;
2534 #address-cells = <1>;
2535 #size-cells = <0>;
2539 compatible = "qcom,i2c-qup-v2.2.1";
2545 clock-names = "core", "iface";
2547 dma-names = "tx", "rx";
2548 pinctrl-names = "default", "sleep";
2549 pinctrl-0 = <&blsp2_i2c2_default>;
2550 pinctrl-1 = <&blsp2_i2c2_sleep>;
2551 clock-frequency = <400000>;
2554 #address-cells = <1>;
2555 #size-cells = <0>;
2559 compatible = "qcom,i2c-qup-v2.2.1";
2565 clock-names = "core", "iface";
2567 dma-names = "tx", "rx";
2568 pinctrl-names = "default", "sleep";
2569 pinctrl-0 = <&blsp2_i2c3_default>;
2570 pinctrl-1 = <&blsp2_i2c3_sleep>;
2571 clock-frequency = <400000>;
2574 #address-cells = <1>;
2575 #size-cells = <0>;
2579 compatible = "qcom,i2c-qup-v2.2.1";
2585 clock-names = "core", "iface";
2587 dma-names = "tx", "rx";
2588 pinctrl-names = "default", "sleep";
2589 pinctrl-0 = <&blsp2_i2c4_default>;
2590 pinctrl-1 = <&blsp2_i2c4_sleep>;
2591 clock-frequency = <400000>;
2594 #address-cells = <1>;
2595 #size-cells = <0>;
2599 compatible = "qcom,i2c-qup-v2.2.1";
2605 clock-names = "core", "iface";
2607 dma-names = "tx", "rx";
2608 pinctrl-names = "default", "sleep";
2609 pinctrl-0 = <&blsp2_i2c5_default>;
2610 pinctrl-1 = <&blsp2_i2c5_sleep>;
2611 clock-frequency = <400000>;
2614 #address-cells = <1>;
2615 #size-cells = <0>;
2619 compatible = "qcom,i2c-qup-v2.2.1";
2625 clock-names = "core", "iface";
2627 dma-names = "tx", "rx";
2628 pinctrl-names = "default", "sleep";
2629 pinctrl-0 = <&blsp2_i2c6_default>;
2630 pinctrl-1 = <&blsp2_i2c6_sleep>;
2631 clock-frequency = <400000>;
2634 #address-cells = <1>;
2635 #size-cells = <0>;
2639 compatible = "qcom,spi-qup-v2.2.1";
2645 clock-names = "core", "iface";
2647 dma-names = "tx", "rx";
2648 pinctrl-names = "default";
2649 pinctrl-0 = <&blsp2_spi1_default>;
2652 #address-cells = <1>;
2653 #size-cells = <0>;
2657 compatible = "qcom,spi-qup-v2.2.1";
2663 clock-names = "core", "iface";
2665 dma-names = "tx", "rx";
2666 pinctrl-names = "default";
2667 pinctrl-0 = <&blsp2_spi2_default>;
2670 #address-cells = <1>;
2671 #size-cells = <0>;
2675 compatible = "qcom,spi-qup-v2.2.1";
2681 clock-names = "core", "iface";
2683 dma-names = "tx", "rx";
2684 pinctrl-names = "default";
2685 pinctrl-0 = <&blsp2_spi3_default>;
2688 #address-cells = <1>;
2689 #size-cells = <0>;
2693 compatible = "qcom,spi-qup-v2.2.1";
2699 clock-names = "core", "iface";
2701 dma-names = "tx", "rx";
2702 pinctrl-names = "default";
2703 pinctrl-0 = <&blsp2_spi4_default>;
2706 #address-cells = <1>;
2707 #size-cells = <0>;
2711 compatible = "qcom,spi-qup-v2.2.1";
2717 clock-names = "core", "iface";
2719 dma-names = "tx", "rx";
2720 pinctrl-names = "default";
2721 pinctrl-0 = <&blsp2_spi5_default>;
2724 #address-cells = <1>;
2725 #size-cells = <0>;
2729 compatible = "qcom,spi-qup-v2.2.1";
2735 clock-names = "core", "iface";
2737 dma-names = "tx", "rx";
2738 pinctrl-names = "default";
2739 pinctrl-0 = <&blsp2_spi6_default>;
2742 #address-cells = <1>;
2743 #size-cells = <0>;
2746 mmcc: clock-controller@c8c0000 {
2747 compatible = "qcom,mmcc-msm8998";
2748 #clock-cells = <1>;
2749 #reset-cells = <1>;
2750 #power-domain-cells = <1>;
2753 clock-names = "xo",
2775 mdss: display-subsystem@c900000 {
2776 compatible = "qcom,msm8998-mdss";
2778 reg-names = "mdss";
2781 interrupt-controller;
2782 #interrupt-cells = <1>;
2787 clock-names = "iface",
2791 power-domains = <&mmcc MDSS_GDSC>;
2794 #address-cells = <1>;
2795 #size-cells = <1>;
2800 mdss_mdp: display-controller@c901000 {
2801 compatible = "qcom,msm8998-dpu";
2806 reg-names = "mdp",
2811 interrupt-parent = <&mdss>;
2819 clock-names = "iface",
2825 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2826 assigned-clock-rates = <19200000>;
2828 operating-points-v2 = <&mdp_opp_table>;
2829 power-domains = <&rpmpd MSM8998_VDDMX>;
2831 mdp_opp_table: opp-table {
2832 compatible = "operating-points-v2";
2834 opp-171430000 {
2835 opp-hz = /bits/ 64 <171430000>;
2836 required-opps = <&rpmpd_opp_low_svs>;
2839 opp-275000000 {
2840 opp-hz = /bits/ 64 <275000000>;
2841 required-opps = <&rpmpd_opp_svs>;
2844 opp-330000000 {
2845 opp-hz = /bits/ 64 <330000000>;
2846 required-opps = <&rpmpd_opp_nom>;
2849 opp-412500000 {
2850 opp-hz = /bits/ 64 <412500000>;
2851 required-opps = <&rpmpd_opp_turbo>;
2856 #address-cells = <1>;
2857 #size-cells = <0>;
2863 remote-endpoint = <&mdss_dsi0_in>;
2871 remote-endpoint = <&mdss_dsi1_in>;
2878 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2880 reg-names = "dsi_ctrl";
2882 interrupt-parent = <&mdss>;
2891 clock-names = "byte",
2897 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2899 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2902 operating-points-v2 = <&dsi_opp_table>;
2903 power-domains = <&rpmpd MSM8998_VDDCX>;
2906 phy-names = "dsi";
2908 #address-cells = <1>;
2909 #size-cells = <0>;
2914 #address-cells = <1>;
2915 #size-cells = <0>;
2921 remote-endpoint = <&dpu_intf1_out>;
2935 compatible = "qcom,dsi-phy-10nm-8998";
2939 reg-names = "dsi_phy",
2945 clock-names = "iface", "ref";
2947 #clock-cells = <1>;
2948 #phy-cells = <0>;
2954 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2956 reg-names = "dsi_ctrl";
2958 interrupt-parent = <&mdss>;
2967 clock-names = "byte",
2973 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2975 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2978 operating-points-v2 = <&dsi_opp_table>;
2979 power-domains = <&rpmpd MSM8998_VDDCX>;
2982 phy-names = "dsi";
2984 #address-cells = <1>;
2985 #size-cells = <0>;
2990 #address-cells = <1>;
2991 #size-cells = <0>;
2997 remote-endpoint = <&dpu_intf2_out>;
3011 compatible = "qcom,dsi-phy-10nm-8998";
3015 reg-names = "dsi_phy",
3021 clock-names = "iface",
3024 #clock-cells = <1>;
3025 #phy-cells = <0>;
3031 venus: video-codec@cc00000 {
3032 compatible = "qcom,msm8998-venus";
3035 power-domains = <&mmcc VIDEO_TOP_GDSC>;
3040 clock-names = "core", "iface", "bus", "mbus";
3061 memory-region = <&venus_mem>;
3064 video-decoder {
3065 compatible = "venus-decoder";
3067 clock-names = "core";
3068 power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>;
3071 video-encoder {
3072 compatible = "venus-encoder";
3074 clock-names = "core";
3075 power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>;
3080 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3082 #iommu-cells = <1>;
3087 clock-names = "iface-mm",
3088 "iface-smmu",
3089 "bus-smmu";
3091 #global-interrupts = <0>;
3114 power-domains = <&mmcc BIMC_SMMU_GDSC>;
3118 compatible = "qcom,msm8998-adsp-pas";
3121 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3126 interrupt-names = "wdog", "fatal", "ready",
3127 "handover", "stop-ack";
3130 clock-names = "xo";
3132 memory-region = <&adsp_mem>;
3134 qcom,smem-states = <&adsp_smp2p_out 0>;
3135 qcom,smem-state-names = "stop";
3137 power-domains = <&rpmpd MSM8998_VDDCX>;
3138 power-domain-names = "cx";
3142 glink-edge {
3145 qcom,remote-pid = <2>;
3151 compatible = "qcom,msm8998-apcs-hmss-global",
3152 "qcom,msm8994-apcs-kpss-global";
3155 #mbox-cells = <1>;
3159 #address-cells = <1>;
3160 #size-cells = <1>;
3162 compatible = "arm,armv7-timer-mem";
3166 frame-number = <0>;
3174 frame-number = <1>;
3181 frame-number = <2>;
3188 frame-number = <3>;
3195 frame-number = <4>;
3202 frame-number = <5>;
3209 frame-number = <6>;
3216 intc: interrupt-controller@17a00000 {
3217 compatible = "arm,gic-v3";
3220 #interrupt-cells = <3>;
3221 #address-cells = <1>;
3222 #size-cells = <1>;
3224 interrupt-controller;
3225 #redistributor-regions = <1>;
3226 redistributor-stride = <0x0 0x20000>;
3231 compatible = "qcom,wcn3990-wifi";
3234 reg-names = "membase";
3235 memory-region = <&wlan_msa_mem>;
3237 clock-names = "cxo_ref_clk_pin";
3253 qcom,snoc-host-cap-8bit-quirk;
3254 qcom,no-msa-ready-indicator;