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/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-qcom-level.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm OPP
10 - Niklas Cassel <nks@flawful.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2-qcom-level
20 '^opp-?[0-9]+$':
25 opp-level: true
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H A Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points) Common Properties
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
25 pattern: '^opp-table(-[a-z0-9]+)?$'
27 opp-shared:
29 Indicates that device nodes using this OPP Table Node's phandle switch
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H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. NVMEM OPP
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
23 the OPP framework with required information (existing HW bitmap).
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/linux/arch/arm64/boot/dts/apple/
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
67 enable-method = "spin-table";
68 cpu-release-addr = <0 0>; /* To be filled by loader */
69 next-level-cache = <&l2_cache_0>;
70 i-cache-size = <0x20000>;
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H A Ds8000.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include "s800-0-3.dtsi"
13 twister_opp: opp-table {
14 compatible = "operating-points-v2";
17 opp-hz = /bits/ 64 <300000000>;
18 opp-level = <1>;
19 clock-latency-ns = <650>;
22 opp-hz = /bits/ 64 <396000000>;
23 opp-level = <2>;
24 clock-latency-ns = <75000>;
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H A Ds8003.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include "s800-0-3.dtsi"
13 twister_opp: opp-table {
14 compatible = "operating-points-v2";
17 opp-hz = /bits/ 64 <300000000>;
18 opp-level = <1>;
19 clock-latency-ns = <500>;
22 opp-hz = /bits/ 64 <396000000>;
23 opp-level = <2>;
24 clock-latency-ns = <45000>;
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H A Ds5l8965x-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 * target-type: J71, J72, J73
11 cyclone_opp: opp-table {
12 compatible = "operating-points-v2";
15 opp-hz = /bits/ 64 <300000000>;
16 opp-level = <1>;
17 clock-latency-ns = <10000>;
20 opp-hz = /bits/ 64 <600000000>;
21 opp-level = <2>;
22 clock-latency-ns = <49000>;
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H A Ds5l8960x-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 * target-type: N51, N53, J85, J86. J87, J85m, J86m, J87m
11 cyclone_opp: opp-table {
12 compatible = "operating-points-v2";
15 opp-hz = /bits/ 64 <300000000>;
16 opp-level = <1>;
17 clock-latency-ns = <15500>;
20 opp-hz = /bits/ 64 <396000000>;
21 opp-level = <2>;
22 clock-latency-ns = <43000>;
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/linux/Documentation/devicetree/bindings/cpufreq/
H A Dqcom-cpufreq-nvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
18 according to the required OPPs defined in the CPU OPP tables.
20 For old implementation efuses are parsed to select the correct opp table and
28 - qcom,apq8064
29 - qcom,apq8096
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/linux/arch/powerpc/kvm/
H A Dmpic.c63 #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000))
116 struct kvm_vcpu *vcpu = current->thread.kvm_vcpu; in get_current_cpu()
117 return vcpu ? vcpu->arch.irq_cpu_id : -1; in get_current_cpu()
120 return -1; in get_current_cpu()
128 static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
133 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
151 int output; /* IRQ level, e.g. ILR_INTTGT_INT */
154 bool level:1; /* level-triggered */ member
171 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) argument
184 /* Count of IRQ sources asserting on non-INT outputs */
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am625.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 i-cache-size = <0x8000>;
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H A Dk3-am62a7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62a.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 i-cache-size = <0x8000>;
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/linux/arch/arm64/boot/dts/qcom/
H A Deliza.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,eliza-dispcc.h>
8 #include <dt-binding
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H A Dglymur.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,glymur-dispcc.h>
7 #include <dt-bindings/clock/qcom,glymur-gcc.h>
8 #include <dt-bindings/clock/qcom,glymur-gpuc
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H A Dhamoa.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
9 #include <dt-binding
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H A Dmonaco.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
8 #include <dt-binding
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/linux/Documentation/devicetree/bindings/power/avs/
H A Dqcom,cpr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <nks@flawful.org>
14 or other device. Each OPP of a device corresponds to a "corner" that has
23 - enum:
24 - qcom,qcs404-cpr
25 - const: qcom,cpr
36 - description: Reference clock.
38 clock-names:
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/linux/rust/kernel/
H A Dopp.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! This module provides rust abstractions for interacting with the OPP subsystem.
9 //! Reference: <https://docs.kernel.org/power/opp.html>
30 /// OPP frequency table.
40 pub(crate) fn new(table: &Table) -> Result<Self> { in new()
57 fn table(&self) -> &cpufreq::Table { in table()
67 fn deref(&self) -> &Self::Target { in deref()
90 /// Creates a null-terminate
296 config_clks(_dev: &Device, _table: &Table, _opp: &OPP, _scaling_down: bool) -> Result config_clks() argument
304 config_regulators( _dev: &Device, _opp_old: &OPP, _opp_new: &OPP, _data: *mut *mut bindings::regulator, _count: u32, ) -> Result config_regulators() argument
305 config_regulators( _dev: &Device, _opp_old: &OPP, _opp_new: &OPP, _data: *mut *mut bindings::regulator, _count: u32, ) -> Result config_regulators() argument
849 opp_from_freq( &self, freq: Hertz, available: Option<bool>, index: Option<u32>, stype: SearchType, ) -> Result<ARef<OPP>> opp_from_freq() argument
888 opp_from_level(&self, mut level: u32, stype: SearchType) -> Result<ARef<OPP>> opp_from_level() argument
914 opp_from_bw(&self, mut bw: u32, index: i32, stype: SearchType) -> Result<ARef<OPP>> opp_from_bw() argument
1034 pub struct OPP(Opaque<bindings::dev_pm_opp>); global() struct
1037 unsafe impl Send for OPP {} global() implementation
1041 unsafe impl Sync for OPP {} global() implementation
1044 unsafe impl AlwaysRefCounted for OPP { global() implementation
1056 impl OPP { global() implementation
1116 pub fn level(&self) -> u32 { level() method
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 core_opp_table: opp-table-core {
5 compatible = "operating-points-v2";
6 opp-shared;
8 core_opp_950: opp-950000 {
9 opp-microvolt = <950000 950000 1300000>;
10 opp-level = <950000>;
13 core_opp_1000: opp-1000000 {
14 opp-microvolt = <1000000 1000000 1300000>;
15 opp-level = <1000000>;
[all …]
H A Dtegra30-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 core_opp_table: opp-table-core {
5 compatible = "operating-points-v2";
6 opp-shared;
8 core_opp_950: opp-950000 {
9 opp-microvolt = <950000 950000 1350000>;
10 opp-level = <950000>;
13 core_opp_1000: opp-1000000 {
14 opp-microvolt = <1000000 1000000 1350000>;
15 opp-level = <1000000>;
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/linux/drivers/opp/
H A Dopp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Generic OPP Interface
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
26 /* Lock to allow exclusive modification to the device and opp lists */
31 /* OPP Config flags */
40 * struct opp_config_data - data for set config operations
41 * @opp_table: OPP table
42 * @flags: OPP config flags
45 * This structure stores the OPP config information for each OPP table
55 * struct dev_pm_opp_icc_bw - Interconnect bandwidth values
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H A Dof.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic OPP OF helpers
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
22 #include "opp.h"
24 /* OPP tables with uninitialized required OPPs, protected by opp_table_lock */
28 * Returns opp descriptor node for a device node, caller must
34 /* "operating-point in _opp_of_get_opp_desc_node()
78 struct dev_pm_opp *opp; _find_opp_of_np() local
251 _of_opp_free_required_opps(struct opp_table * opp_table,struct dev_pm_opp * opp) _of_opp_free_required_opps() argument
271 _of_clear_opp(struct opp_table * opp_table,struct dev_pm_opp * opp) _of_clear_opp() argument
277 _link_required_opps(struct dev_pm_opp * opp,struct opp_table * required_table,int index) _link_required_opps() argument
298 _of_opp_alloc_required_opps(struct opp_table * opp_table,struct dev_pm_opp * opp) _of_opp_alloc_required_opps() argument
334 struct dev_pm_opp *opp; lazy_link_required_opps() local
350 struct dev_pm_opp *opp; lazy_link_required_opp_table() local
556 _parse_named_prop(struct dev_pm_opp * opp,struct device * dev,struct opp_table * opp_table,const char * prop_type,bool * triplet) _parse_named_prop() argument
619 opp_parse_microvolt(struct dev_pm_opp * opp,struct device * dev,struct opp_table * opp_table,bool * triplet) opp_parse_microvolt() argument
647 opp_parse_supplies(struct dev_pm_opp * opp,struct device * dev,struct opp_table * opp_table) opp_parse_supplies() argument
960 struct dev_pm_opp *opp; _of_add_opp_table_v2() local
1415 dev_pm_opp_get_of_node(struct dev_pm_opp * opp) dev_pm_opp_get_of_node() argument
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx65.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
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/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
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/linux/arch/arm/boot/dts/socionext/
H A Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
24 enable-method = "psci";
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