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/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-qcom-level.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm OPP
10 - Niklas Cassel <nks@flawful.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2-qcom-level
20 '^opp-?[0-9]+$':
25 opp-level: true
[all …]
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points)
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
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H A Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points) Common Properties
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
25 pattern: '^opp-table(-[a-z0-9]+)?$'
27 opp-shared:
29 Indicates that device nodes using this OPP Table Node's phandle switch
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H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. NVMEM OPP
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
23 the OPP framework with required information (existing HW bitmap).
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/linux/Documentation/devicetree/bindings/power/
H A Dqcom,rpmpd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
19 - enum:
20 - qcom,glymur-rpmhpd
21 - qcom,mdm9607-rpmpd
22 - qcom,milos-rpmhpd
23 - qcom,msm8226-rpmpd
24 - qcom,msm8909-rpmpd
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/linux/arch/arm64/boot/dts/apple/
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
67 enable-method = "spin-table";
68 cpu-release-addr = <0 0>; /* To be filled by loader */
69 next-level-cache = <&l2_cache_0>;
70 i-cache-size = <0x20000>;
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H A Ds8000.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include "s800-0-3.dtsi"
13 twister_opp: opp-table {
14 compatible = "operating-points-v2";
17 opp-hz = /bits/ 64 <300000000>;
18 opp-level = <1>;
19 clock-latency-ns = <650>;
22 opp-hz = /bits/ 64 <396000000>;
23 opp-level = <2>;
24 clock-latency-ns = <75000>;
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H A Ds8003.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include "s800-0-3.dtsi"
13 twister_opp: opp-table {
14 compatible = "operating-points-v2";
17 opp-hz = /bits/ 64 <300000000>;
18 opp-level = <1>;
19 clock-latency-ns = <500>;
22 opp-hz = /bits/ 64 <396000000>;
23 opp-level = <2>;
24 clock-latency-ns = <45000>;
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H A Ds5l8965x-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 * target-type: J71, J72, J73
11 cyclone_opp: opp-table {
12 compatible = "operating-points-v2";
15 opp-hz = /bits/ 64 <300000000>;
16 opp-level = <1>;
17 clock-latency-ns = <10000>;
20 opp-hz = /bits/ 64 <600000000>;
21 opp-level = <2>;
22 clock-latency-ns = <49000>;
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H A Ds5l8960x-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 * target-type: N51, N53, J85, J86. J87, J85m, J86m, J87m
11 cyclone_opp: opp-table {
12 compatible = "operating-points-v2";
15 opp-hz = /bits/ 64 <300000000>;
16 opp-level = <1>;
17 clock-latency-ns = <15500>;
20 opp-hz = /bits/ 64 <396000000>;
21 opp-level = <2>;
22 clock-latency-ns = <43000>;
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/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996-v3.0.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 qcom,msm-id = <246 0x30000>;
22 gpu_opp_table_3_0: opp-table-gpu30 {
23 compatible = "operating-points-v2";
25 opp-624000000 {
26 opp-hz = /bits/ 64 <624000000>;
27 opp-level = <7>;
30 opp-560000000 {
31 opp-hz = /bits/ 64 <560000000>;
32 opp-level = <6>;
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H A Dsdm660.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
13 compatible = "qcom,adreno-512.0", "qcom,adreno";
14 operating-points-v2 = <&gpu_sdm660_opp_table>;
16 gpu_sdm660_opp_table: opp-table {
17 compatible = "operating-points-v2";
23 * at the same opp-level
25 opp-750000000 {
26 opp-hz = /bits/ 64 <750000000>;
27 opp-level = <RPM_SMD_LEVEL_TURBO>;
28 opp-peak-kBps = <5412000>;
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H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
12 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
13 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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H A Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom,rpmhpd.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
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H A Dsdm630.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
9 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
10 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/interconnect/qcom,sdm660.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/gpio/gpio.h>
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/linux/Documentation/devicetree/bindings/cpufreq/
H A Dqcom-cpufreq-nvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
18 according to the required OPPs defined in the CPU OPP tables.
20 For old implementation efuses are parsed to select the correct opp table and
28 - qcom,apq8064
29 - qcom,apq8096
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/linux/drivers/firmware/arm_scmi/
H A Dperf.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2023 ARM Ltd.
8 #define pr_fmt(fmt) "SCMI Notifications PERF - " fmt
103 __le32 level; member
132 } opp[]; member
145 } opp[]; member
161 struct scmi_opp opp[MAX_OPPS]; member
175 if (_opp->indicative_freq == f_) \
203 ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES, 0, in scmi_perf_attributes_get()
208 attr = t->rx.buf; in scmi_perf_attributes_get()
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/linux/include/linux/
H A Dpm_opp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Generic OPP Interface
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
32 * struct dev_pm_opp_supply - Power supply voltage/current values
33 * @u_volt: Target voltage in microvolts corresponding to this OPP
34 * @u_volt_min: Minimum voltage in microvolts corresponding to this OPP
35 * @u_volt_max: Maximum voltage in microvolts corresponding to this OPP
96 unsigned int level; global() member
219 dev_pm_opp_get_bw(struct dev_pm_opp * opp,bool peak,int index) dev_pm_opp_get_bw() argument
224 dev_pm_opp_get_voltage(struct dev_pm_opp * opp) dev_pm_opp_get_voltage() argument
229 dev_pm_opp_get_supplies(struct dev_pm_opp * opp,struct dev_pm_opp_supply * supplies) dev_pm_opp_get_supplies() argument
234 dev_pm_opp_get_power(struct dev_pm_opp * opp) dev_pm_opp_get_power() argument
239 dev_pm_opp_get_freq_indexed(struct dev_pm_opp * opp,u32 index) dev_pm_opp_get_freq_indexed() argument
244 dev_pm_opp_get_level(struct dev_pm_opp * opp) dev_pm_opp_get_level() argument
250 dev_pm_opp_get_required_pstate(struct dev_pm_opp * opp,unsigned int index) dev_pm_opp_get_required_pstate() argument
256 dev_pm_opp_is_turbo(struct dev_pm_opp * opp) dev_pm_opp_is_turbo() argument
324 dev_pm_opp_find_level_exact(struct device * dev,unsigned int level) dev_pm_opp_find_level_exact() argument
330 dev_pm_opp_find_level_ceil(struct device * dev,unsigned int * level) dev_pm_opp_find_level_ceil() argument
336 dev_pm_opp_find_level_floor(struct device * dev,unsigned int * level) dev_pm_opp_find_level_floor() argument
353 dev_pm_opp_get(struct dev_pm_opp * opp) dev_pm_opp_get() argument
358 dev_pm_opp_put(struct dev_pm_opp * opp) dev_pm_opp_put() argument
361 dev_pm_opp_add_dynamic(struct device * dev,struct dev_pm_opp_data * opp) dev_pm_opp_add_dynamic() argument
415 dev_pm_opp_config_clks_simple(struct device * dev,struct opp_table * opp_table,struct dev_pm_opp * opp,void * data,bool scaling_down) dev_pm_opp_config_clks_simple() argument
437 dev_pm_opp_set_opp(struct device * dev,struct dev_pm_opp * opp) dev_pm_opp_set_opp() argument
547 dev_pm_opp_get_of_node(struct dev_pm_opp * opp) dev_pm_opp_get_of_node() argument
716 dev_pm_opp_get_freq(struct dev_pm_opp * opp) dev_pm_opp_get_freq() argument
721 dev_pm_opp_set_level(struct device * dev,unsigned int level) dev_pm_opp_set_level() argument
[all...]
/linux/arch/powerpc/kvm/
H A Dmpic.c63 #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000))
116 struct kvm_vcpu *vcpu = current->thread.kvm_vcpu; in get_current_cpu()
117 return vcpu ? vcpu->arch.irq_cpu_id : -1; in get_current_cpu()
120 return -1; in get_current_cpu()
128 static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
133 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
151 int output; /* IRQ level, e.g. ILR_INTTGT_INT */
154 bool level:1; /* level-triggered */ member
171 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) argument
184 /* Count of IRQ sources asserting on non-INT outputs */
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am625.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 i-cache-size = <0x8000>;
[all …]
H A Dk3-am62a7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62a.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 i-cache-size = <0x8000>;
[all …]
/linux/Documentation/devicetree/bindings/power/avs/
H A Dqcom,cpr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <nks@flawful.org>
14 or other device. Each OPP of a device corresponds to a "corner" that has
23 - enum:
24 - qcom,qcs404-cpr
25 - const: qcom,cpr
36 - description: Reference clock.
38 clock-names:
[all …]
/linux/rust/kernel/
H A Dopp.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! This module provides rust abstractions for interacting with the OPP subsystem.
9 //! Reference: <https://docs.kernel.org/power/opp.html>
30 /// OPP frequency table.
40 pub(crate) fn new(table: &Table) -> Result<Self> { in new()
57 fn table(&self) -> &cpufreq::Table { in table()
67 fn deref(&self) -> &Self::Target { in deref()
90 /// Creates a null-terminate
295 config_clks(_dev: &Device, _table: &Table, _opp: &OPP, _scaling_down: bool) -> Result config_clks() argument
303 config_regulators( _dev: &Device, _opp_old: &OPP, _opp_new: &OPP, _data: *mut *mut bindings::regulator, _count: u32, ) -> Result config_regulators() argument
304 config_regulators( _dev: &Device, _opp_old: &OPP, _opp_new: &OPP, _data: *mut *mut bindings::regulator, _count: u32, ) -> Result config_regulators() argument
850 opp_from_freq( &self, freq: Hertz, available: Option<bool>, index: Option<u32>, stype: SearchType, ) -> Result<ARef<OPP>> opp_from_freq() argument
889 opp_from_level(&self, mut level: u32, stype: SearchType) -> Result<ARef<OPP>> opp_from_level() argument
915 opp_from_bw(&self, mut bw: u32, index: i32, stype: SearchType) -> Result<ARef<OPP>> opp_from_bw() argument
1035 pub struct OPP(Opaque<bindings::dev_pm_opp>); global() struct
1038 unsafe impl Send for OPP {} global() implementation
1042 unsafe impl Sync for OPP {} global() implementation
1045 unsafe impl AlwaysRefCounted for OPP { global() implementation
1057 impl OPP { global() implementation
1117 pub fn level(&self) -> u32 { level() method
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 core_opp_table: opp-table-core {
5 compatible = "operating-points-v2";
6 opp-shared;
8 core_opp_950: opp-950000 {
9 opp-microvolt = <950000 950000 1300000>;
10 opp-level = <950000>;
13 core_opp_1000: opp-1000000 {
14 opp-microvolt = <1000000 1000000 1300000>;
15 opp-level = <1000000>;
[all …]
/linux/drivers/opp/
H A Dopp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Generic OPP Interface
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
26 /* Lock to allow exclusive modification to the device and opp lists */
31 /* OPP Config flags */
40 * struct opp_config_data - data for set config operations
41 * @opp_table: OPP table
42 * @flags: OPP config flags
45 * This structure stores the OPP config information for each OPP table
55 * struct dev_pm_opp_icc_bw - Interconnect bandwidth values
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