Lines Matching +full:opp +full:- +full:level
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
29 WAKE - Triggered by F/W
30 CONTROL - Triggered by F/W
31 See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
47 const: qcom,rpmh-rsc
61 qcom,drv-id:
66 qcom,tcs-config:
67 $ref: /schemas/types.yaml#/definitions/uint32-matrix
72 - description: |
74 - ACTIVE_TCS
75 - SLEEP_TCS
76 - WAKE_TCS
77 - CONTROL_TCS
79 - description: Number of TCS
85 qcom,tcs-offset:
94 reg-names:
97 - const: drv-0
98 - const: drv-1
99 - const: drv-2
100 - const: drv-3
102 power-domains:
105 bcm-voter:
106 $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
108 clock-controller:
111 power-controller:
115 '^regulators(-[0-9])?$':
116 $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
120 - compatible
121 - interrupts
122 - qcom,drv-id
123 - qcom,tcs-config
124 - qcom,tcs-offset
125 - reg
126 - reg-names
127 - power-domains
132 - |
139 // TCS-OFFSET: 0xD00
140 #include <dt-bindings/interrupt-controller/arm-gic.h>
141 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
144 compatible = "qcom,rpmh-rsc";
148 reg-names = "drv-0", "drv-1", "drv-2";
153 qcom,tcs-offset = <0xd00>;
154 qcom,drv-id = <2>;
155 qcom,tcs-config = <ACTIVE_TCS 2>,
159 power-domains = <&CLUSTER_PD>;
162 - |
167 // TCS-OFFSET: 0x1C00
168 #include <dt-bindings/interrupt-controller/arm-gic.h>
169 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
172 compatible = "qcom,rpmh-rsc";
174 reg-names = "drv-0";
177 qcom,tcs-offset = <0x1c00>;
178 qcom,drv-id = <0>;
179 qcom,tcs-config = <ACTIVE_TCS 0>,
183 power-domains = <&CLUSTER_PD>;
186 - |
187 #include <dt-bindings/interrupt-controller/arm-gic.h>
188 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
189 #include <dt-bindings/power/qcom-rpmpd.h>
192 compatible = "qcom,rpmh-rsc";
196 reg-names = "drv-0", "drv-1", "drv-2";
201 qcom,tcs-offset = <0xd00>;
202 qcom,drv-id = <2>;
203 qcom,tcs-config = <ACTIVE_TCS 2>,
207 power-domains = <&CLUSTER_PD>;
209 clock-controller {
210 compatible = "qcom,sm8350-rpmh-clk";
211 #clock-cells = <1>;
212 clock-names = "xo";
216 power-controller {
217 compatible = "qcom,sm8350-rpmhpd";
218 #power-domain-cells = <1>;
219 operating-points-v2 = <&rpmhpd_opp_table>;
221 rpmhpd_opp_table: opp-table {
222 compatible = "operating-points-v2";
225 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
229 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
233 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
237 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
241 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
245 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
249 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
253 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
257 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
261 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
266 bcm-voter {
267 compatible = "qcom,bcm-voter";