Lines Matching +full:opp +full:- +full:level
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points)
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
29 #size-cells = <0>;
32 compatible = "arm,cortex-a9";
35 next-level-cache = <&L2>;
37 clock-names = "cpu";
38 cpu-supply = <&cpu_supply0>;
39 operating-points-v2 = <&cpu0_opp_table0>;
43 compatible = "arm,cortex-a9";
46 next-level-cache = <&L2>;
48 clock-names = "cpu";
49 cpu-supply = <&cpu_supply0>;
50 operating-points-v2 = <&cpu0_opp_table0>;
54 cpu0_opp_table0: opp-table {
55 compatible = "operating-points-v2";
56 opp-shared;
58 opp-1000000000 {
59 opp-hz = /bits/ 64 <1000000000>;
60 opp-microvolt = <975000 970000 985000>;
61 opp-microamp = <70000>;
62 clock-latency-ns = <300000>;
63 opp-suspend;
65 opp-1100000000 {
66 opp-hz = /bits/ 64 <1100000000>;
67 opp-microvolt = <1000000 980000 1010000>;
68 opp-microamp = <80000>;
69 clock-latency-ns = <310000>;
71 opp-1200000000 {
72 opp-hz = /bits/ 64 <1200000000>;
73 opp-microvolt = <1025000>;
74 clock-latency-ns = <290000>;
75 turbo-mode;
79 - |
81 * Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states
85 #address-cells = <1>;
86 #size-cells = <0>;
92 next-level-cache = <&L2>;
94 clock-names = "cpu";
95 cpu-supply = <&cpu_supply0>;
96 operating-points-v2 = <&cpu_opp_table>;
103 next-level-cache = <&L2>;
105 clock-names = "cpu";
106 cpu-supply = <&cpu_supply1>;
107 operating-points-v2 = <&cpu_opp_table>;
114 next-level-cache = <&L2>;
116 clock-names = "cpu";
117 cpu-supply = <&cpu_supply2>;
118 operating-points-v2 = <&cpu_opp_table>;
125 next-level-cache = <&L2>;
127 clock-names = "cpu";
128 cpu-supply = <&cpu_supply3>;
129 operating-points-v2 = <&cpu_opp_table>;
133 cpu_opp_table: opp-table {
134 compatible = "operating-points-v2";
137 * Missing opp-shared property means CPUs switch DVFS states
141 opp-1000000000 {
142 opp-hz = /bits/ 64 <1000000000>;
143 opp-microvolt = <975000 970000 985000>;
144 opp-microamp = <70000>;
145 clock-latency-ns = <300000>;
146 opp-suspend;
148 opp-1100000000 {
149 opp-hz = /bits/ 64 <1100000000>;
150 opp-microvolt = <1000000 980000 1010000>;
151 opp-microamp = <80000>;
152 clock-latency-ns = <310000>;
154 opp-1200000000 {
155 opp-hz = /bits/ 64 <1200000000>;
156 opp-microvolt = <1025000>;
157 opp-microamp = <90000>;
158 clock-latency-ns = <290000>;
159 turbo-mode;
163 - |
165 * Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch
169 #address-cells = <1>;
170 #size-cells = <0>;
173 compatible = "arm,cortex-a7";
176 next-level-cache = <&L2>;
178 clock-names = "cpu";
179 cpu-supply = <&cpu_supply0>;
180 operating-points-v2 = <&cluster0_opp>;
184 compatible = "arm,cortex-a7";
187 next-level-cache = <&L2>;
189 clock-names = "cpu";
190 cpu-supply = <&cpu_supply0>;
191 operating-points-v2 = <&cluster0_opp>;
195 compatible = "arm,cortex-a15";
198 next-level-cache = <&L2>;
200 clock-names = "cpu";
201 cpu-supply = <&cpu_supply1>;
202 operating-points-v2 = <&cluster1_opp>;
206 compatible = "arm,cortex-a15";
209 next-level-cache = <&L2>;
211 clock-names = "cpu";
212 cpu-supply = <&cpu_supply1>;
213 operating-points-v2 = <&cluster1_opp>;
217 cluster0_opp: opp-table-0 {
218 compatible = "operating-points-v2";
219 opp-shared;
221 opp-1000000000 {
222 opp-hz = /bits/ 64 <1000000000>;
223 opp-microvolt = <975000 970000 985000>;
224 opp-microamp = <70000>;
225 clock-latency-ns = <300000>;
226 opp-suspend;
228 opp-1100000000 {
229 opp-hz = /bits/ 64 <1100000000>;
230 opp-microvolt = <1000000 980000 1010000>;
231 opp-microamp = <80000>;
232 clock-latency-ns = <310000>;
234 opp-1200000000 {
235 opp-hz = /bits/ 64 <1200000000>;
236 opp-microvolt = <1025000>;
237 opp-microamp = <90000>;
238 clock-latency-ns = <290000>;
239 turbo-mode;
243 cluster1_opp: opp-table-1 {
244 compatible = "operating-points-v2";
245 opp-shared;
247 opp-1300000000 {
248 opp-hz = /bits/ 64 <1300000000>;
249 opp-microvolt = <1050000 1045000 1055000>;
250 opp-microamp = <95000>;
251 clock-latency-ns = <400000>;
252 opp-suspend;
254 opp-1400000000 {
255 opp-hz = /bits/ 64 <1400000000>;
256 opp-microvolt = <1075000>;
257 opp-microamp = <100000>;
258 clock-latency-ns = <400000>;
260 opp-1500000000 {
261 opp-hz = /bits/ 64 <1500000000>;
262 opp-microvolt = <1100000 1010000 1110000>;
263 opp-microamp = <95000>;
264 clock-latency-ns = <400000>;
265 turbo-mode;
269 - |
272 #address-cells = <1>;
273 #size-cells = <0>;
276 compatible = "foo,cpu-type";
280 vcc0-supply = <&cpu_supply0>;
281 vcc1-supply = <&cpu_supply1>;
282 vcc2-supply = <&cpu_supply2>;
283 operating-points-v2 = <&cpu0_opp_table4>;
287 cpu0_opp_table4: opp-table-0 {
288 compatible = "operating-points-v2";
289 opp-shared;
291 opp-1000000000 {
292 opp-hz = /bits/ 64 <1000000000>;
293 opp-microvolt = <970000>, /* Supply 0 */
296 opp-microamp = <70000>, /* Supply 0 */
299 clock-latency-ns = <300000>;
304 opp-1000000001 {
305 opp-hz = /bits/ 64 <1000000001>;
306 opp-microvolt = <975000 970000 985000>, /* Supply 0 */
309 opp-microamp = <70000>, /* Supply 0 */
312 clock-latency-ns = <300000>;
317 opp-1000000002 {
318 opp-hz = /bits/ 64 <1000000002>;
319 opp-microvolt = <975000 970000 985000>, /* Supply 0 */
322 opp-microamp = <70000>, /* Supply 0 */
325 clock-latency-ns = <300000>;
329 - |
331 * Example 5: opp-supported-hw
332 * (example: three level hierarchy of versions: cuts, substrate and process)
335 #address-cells = <1>;
336 #size-cells = <0>;
339 compatible = "arm,cortex-a7";
342 cpu-supply = <&cpu_supply>;
343 operating-points-v2 = <&cpu0_opp_table_slow>;
347 cpu0_opp_table_slow: opp-table {
348 compatible = "operating-points-v2";
349 opp-shared;
351 opp-600000000 {
356 opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF>;
357 opp-hz = /bits/ 64 <600000000>;
360 opp-800000000 {
363 * - cuts: only one, 6th cut (represented by 6th bit).
364 * - substrate: supports 16 different substrate versions
365 * - process: supports 9 different process versions
367 opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0>;
368 opp-hz = /bits/ 64 <800000000>;
371 opp-900000000 {
374 * - All cuts and substrate where process version is 0x2.
375 * - All cuts and process where substrate version is 0x2.
377 opp-supported-hw = <0xFFFFFFFF 0xFFFFFFFF 0x02>,
379 opp-hz = /bits/ 64 <900000000>;
383 - |
385 * Example 6: opp-microvolt-<name>, opp-microamp-<name>:
389 #address-cells = <1>;
390 #size-cells = <0>;
393 compatible = "arm,cortex-a7";
396 operating-points-v2 = <&cpu0_opp_table6>;
400 cpu0_opp_table6: opp-table-0 {
401 compatible = "operating-points-v2";
402 opp-shared;
404 opp-1000000000 {
405 opp-hz = /bits/ 64 <1000000000>;
406 opp-microvolt-slow = <915000 900000 925000>;
407 opp-microvolt-fast = <975000 970000 985000>;
408 opp-microamp-slow = <70000>;
409 opp-microamp-fast = <71000>;
412 opp-1200000000 {
413 opp-hz = /bits/ 64 <1200000000>;
414 opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */
416 opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */
418 opp-microamp = <70000>; /* Will be used for both slow/fast */
422 - |
424 * Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware,
428 #address-cells = <2>;
429 #size-cells = <0>;
432 compatible = "arm,cortex-a53";
435 next-level-cache = <&A53_L2>;
437 operating-points-v2 = <&cpu_opp0_table>;
440 compatible = "arm,cortex-a53";
443 next-level-cache = <&A53_L2>;
445 operating-points-v2 = <&cpu_opp0_table>;
448 compatible = "arm,cortex-a53";
451 next-level-cache = <&A53_L2>;
453 operating-points-v2 = <&cpu_opp1_table>;
456 compatible = "arm,cortex-a53";
459 next-level-cache = <&A53_L2>;
461 operating-points-v2 = <&cpu_opp1_table>;
466 cpu_opp0_table: opp-table-0 {
467 compatible = "operating-points-v2";
468 opp-shared;
471 cpu_opp1_table: opp-table-1 {
472 compatible = "operating-points-v2";
473 opp-shared;