Lines Matching +full:opp +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
25 cpu-map {
61 enable-method = "spin-table";
62 cpu-release-addr = <0 0>; /* To be filled by loader */
63 operating-points-v2 = <&ecluster_opp>;
64 capacity-dmips-mhz = <714>;
65 performance-domains = <&cpufreq_e>;
66 next-level-cache = <&l2_cache_0>;
67 i-cache-size = <0x20000>;
68 d-cache-size = <0x10000>;
75 enable-method = "spin-table";
76 cpu-release-addr = <0 0>; /* To be filled by loader */
77 operating-points-v2 = <&ecluster_opp>;
78 capacity-dmips-mhz = <714>;
79 performance-domains = <&cpufreq_e>;
80 next-level-cache = <&l2_cache_0>;
81 i-cache-size = <0x20000>;
82 d-cache-size = <0x10000>;
89 enable-method = "spin-table";
90 cpu-release-addr = <0 0>; /* To be filled by loader */
91 operating-points-v2 = <&ecluster_opp>;
92 capacity-dmips-mhz = <714>;
93 performance-domains = <&cpufreq_e>;
94 next-level-cache = <&l2_cache_0>;
95 i-cache-size = <0x20000>;
96 d-cache-size = <0x10000>;
103 enable-method = "spin-table";
104 cpu-release-addr = <0 0>; /* To be filled by loader */
105 operating-points-v2 = <&ecluster_opp>;
106 capacity-dmips-mhz = <714>;
107 performance-domains = <&cpufreq_e>;
108 next-level-cache = <&l2_cache_0>;
109 i-cache-size = <0x20000>;
110 d-cache-size = <0x10000>;
117 enable-method = "spin-table";
118 cpu-release-addr = <0 0>; /* To be filled by loader */
119 operating-points-v2 = <&pcluster_opp>;
120 capacity-dmips-mhz = <1024>;
121 performance-domains = <&cpufreq_p>;
122 next-level-cache = <&l2_cache_1>;
123 i-cache-size = <0x30000>;
124 d-cache-size = <0x20000>;
131 enable-method = "spin-table";
132 cpu-release-addr = <0 0>; /* To be filled by loader */
133 operating-points-v2 = <&pcluster_opp>;
134 capacity-dmips-mhz = <1024>;
135 performance-domains = <&cpufreq_p>;
136 next-level-cache = <&l2_cache_1>;
137 i-cache-size = <0x30000>;
138 d-cache-size = <0x20000>;
145 enable-method = "spin-table";
146 cpu-release-addr = <0 0>; /* To be filled by loader */
147 operating-points-v2 = <&pcluster_opp>;
148 capacity-dmips-mhz = <1024>;
149 performance-domains = <&cpufreq_p>;
150 next-level-cache = <&l2_cache_1>;
151 i-cache-size = <0x30000>;
152 d-cache-size = <0x20000>;
159 enable-method = "spin-table";
160 cpu-release-addr = <0 0>; /* To be filled by loader */
161 operating-points-v2 = <&pcluster_opp>;
162 capacity-dmips-mhz = <1024>;
163 performance-domains = <&cpufreq_p>;
164 next-level-cache = <&l2_cache_1>;
165 i-cache-size = <0x30000>;
166 d-cache-size = <0x20000>;
169 l2_cache_0: l2-cache-0 {
171 cache-level = <2>;
172 cache-unified;
173 cache-size = <0x400000>;
176 l2_cache_1: l2-cache-1 {
178 cache-level = <2>;
179 cache-unified;
180 cache-size = <0xc00000>;
184 ecluster_opp: opp-table-0 {
185 compatible = "operating-points-v2";
188 opp-hz = /bits/ 64 <600000000>;
189 opp-level = <1>;
190 clock-latency-ns = <7500>;
193 opp-hz = /bits/ 64 <972000000>;
194 opp-level = <2>;
195 clock-latency-ns = <22000>;
198 opp-hz = /bits/ 64 <1332000000>;
199 opp-level = <3>;
200 clock-latency-ns = <27000>;
203 opp-hz = /bits/ 64 <1704000000>;
204 opp-level = <4>;
205 clock-latency-ns = <33000>;
208 opp-hz = /bits/ 64 <2064000000>;
209 opp-level = <5>;
210 clock-latency-ns = <50000>;
214 pcluster_opp: opp-table-1 {
215 compatible = "operating-points-v2";
218 opp-hz = /bits/ 64 <600000000>;
219 opp-level = <1>;
220 clock-latency-ns = <8000>;
223 opp-hz = /bits/ 64 <828000000>;
224 opp-level = <2>;
225 clock-latency-ns = <19000>;
228 opp-hz = /bits/ 64 <1056000000>;
229 opp-level = <3>;
230 clock-latency-ns = <21000>;
233 opp-hz = /bits/ 64 <1284000000>;
234 opp-level = <4>;
235 clock-latency-ns = <23000>;
238 opp-hz = /bits/ 64 <1500000000>;
239 opp-level = <5>;
240 clock-latency-ns = <24000>;
243 opp-hz = /bits/ 64 <1728000000>;
244 opp-level = <6>;
245 clock-latency-ns = <29000>;
248 opp-hz = /bits/ 64 <1956000000>;
249 opp-level = <7>;
250 clock-latency-ns = <31000>;
253 opp-hz = /bits/ 64 <2184000000>;
254 opp-level = <8>;
255 clock-latency-ns = <34000>;
258 opp-hz = /bits/ 64 <2388000000>;
259 opp-level = <9>;
260 clock-latency-ns = <36000>;
263 opp-hz = /bits/ 64 <2592000000>;
264 opp-level = <10>;
265 clock-latency-ns = <51000>;
268 opp-hz = /bits/ 64 <2772000000>;
269 opp-level = <11>;
270 clock-latency-ns = <54000>;
273 opp-hz = /bits/ 64 <2988000000>;
274 opp-level = <12>;
275 clock-latency-ns = <55000>;
280 opp-hz = /bits/ 64 <3096000000>;
281 opp-level = <13>;
282 clock-latency-ns = <55000>;
283 turbo-mode;
286 opp-hz = /bits/ 64 <3144000000>;
287 opp-level = <14>;
288 clock-latency-ns = <56000>;
289 turbo-mode;
292 opp-hz = /bits/ 64 <3204000000>;
293 opp-level = <15>;
294 clock-latency-ns = <56000>;
295 turbo-mode;
301 compatible = "arm,armv8-timer";
302 interrupt-parent = <&aic>;
303 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
310 pmu-e {
311 compatible = "apple,icestorm-pmu";
312 interrupt-parent = <&aic>;
316 pmu-p {
317 compatible = "apple,firestorm-pmu";
318 interrupt-parent = <&aic>;
322 clkref: clock-ref {
323 compatible = "fixed-clock";
324 #clock-cells = <0>;
325 clock-frequency = <24000000>;
326 clock-output-names = "clkref";
333 nco_clkref: clock-ref-nco {
334 compatible = "fixed-clock";
335 #clock-cells = <0>;
336 clock-output-names = "nco_ref";
340 compatible = "simple-bus";
341 #address-cells = <2>;
342 #size-cells = <2>;
345 nonposted-mmio;
347 cpufreq_e: performance-controller@210e20000 {
348 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
350 #performance-domain-cells = <0>;
353 cpufreq_p: performance-controller@211e20000 {
354 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
356 #performance-domain-cells = <0>;
360 compatible = "apple,t8103-dart";
362 interrupt-parent = <&aic>;
364 #iommu-cells = <1>;
365 power-domains = <&ps_sio_cpu>;
369 compatible = "apple,t8103-i2c", "apple,i2c";
372 interrupt-parent = <&aic>;
374 pinctrl-0 = <&i2c0_pins>;
375 pinctrl-names = "default";
376 #address-cells = <0x1>;
377 #size-cells = <0x0>;
378 power-domains = <&ps_i2c0>;
382 compatible = "apple,t8103-i2c", "apple,i2c";
385 interrupt-parent = <&aic>;
387 pinctrl-0 = <&i2c1_pins>;
388 pinctrl-names = "default";
389 #address-cells = <0x1>;
390 #size-cells = <0x0>;
391 power-domains = <&ps_i2c1>;
395 compatible = "apple,t8103-i2c", "apple,i2c";
398 interrupt-parent = <&aic>;
400 pinctrl-0 = <&i2c2_pins>;
401 pinctrl-names = "default";
402 #address-cells = <0x1>;
403 #size-cells = <0x0>;
405 power-domains = <&ps_i2c2>;
409 compatible = "apple,t8103-i2c", "apple,i2c";
412 interrupt-parent = <&aic>;
414 pinctrl-0 = <&i2c3_pins>;
415 pinctrl-names = "default";
416 #address-cells = <0x1>;
417 #size-cells = <0x0>;
418 power-domains = <&ps_i2c3>;
422 compatible = "apple,t8103-i2c", "apple,i2c";
425 interrupt-parent = <&aic>;
427 pinctrl-0 = <&i2c4_pins>;
428 pinctrl-names = "default";
429 #address-cells = <0x1>;
430 #size-cells = <0x0>;
431 power-domains = <&ps_i2c4>;
436 compatible = "apple,t8103-fpwm", "apple,s5l-fpwm";
438 power-domains = <&ps_fpwm1>;
440 #pwm-cells = <2>;
445 compatible = "apple,s5l-uart";
447 reg-io-width = <4>;
448 interrupt-parent = <&aic>;
455 clock-names = "uart", "clk_uart_baud0";
456 power-domains = <&ps_uart0>;
461 compatible = "apple,s5l-uart";
463 reg-io-width = <4>;
464 interrupt-parent = <&aic>;
467 clock-names = "uart", "clk_uart_baud0";
468 power-domains = <&ps_uart2>;
472 admac: dma-controller@238200000 {
473 compatible = "apple,t8103-admac", "apple,admac";
475 dma-channels = <24>;
476 interrupts-extended = <0>,
480 #dma-cells = <1>;
482 power-domains = <&ps_sio_adma>;
487 compatible = "apple,t8103-mca", "apple,mca";
491 interrupt-parent = <&aic>;
502 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
510 dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
517 #sound-dai-cells = <1>;
520 nco: clock-controller@23b044000 {
521 compatible = "apple,t8103-nco", "apple,nco";
524 #clock-cells = <1>;
527 aic: interrupt-controller@23b100000 {
528 compatible = "apple,t8103-aic", "apple,aic";
529 #interrupt-cells = <3>;
530 interrupt-controller;
532 power-domains = <&ps_aic>;
535 e-core-pmu-affinity {
536 apple,fiq-index = <AIC_CPU_PMU_E>;
540 p-core-pmu-affinity {
541 apple,fiq-index = <AIC_CPU_PMU_P>;
547 pmgr: power-management@23b700000 {
548 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
549 #address-cells = <1>;
550 #size-cells = <1>;
555 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
557 power-domains = <&ps_gpio>;
559 gpio-controller;
560 #gpio-cells = <2>;
561 gpio-ranges = <&pinctrl_ap 0 0 212>;
564 interrupt-controller;
565 #interrupt-cells = <2>;
566 interrupt-parent = <&aic>;
575 i2c0_pins: i2c0-pins {
580 i2c1_pins: i2c1-pins {
585 i2c2_pins: i2c2-pins {
590 i2c3_pins: i2c3-pins {
595 i2c4_pins: i2c4-pins {
600 pcie_pins: pcie-pins {
608 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
610 power-domains = <&ps_nub_gpio>;
612 gpio-controller;
613 #gpio-cells = <2>;
614 gpio-ranges = <&pinctrl_nub 0 0 23>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
619 interrupt-parent = <&aic>;
629 pmgr_mini: power-management@23d280000 {
630 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
631 #address-cells = <1>;
632 #size-cells = <1>;
637 compatible = "apple,t8103-wdt", "apple,wdt";
640 interrupt-parent = <&aic>;
645 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
648 gpio-controller;
649 #gpio-cells = <2>;
650 gpio-ranges = <&pinctrl_smc 0 0 16>;
653 interrupt-controller;
654 #interrupt-cells = <2>;
655 interrupt-parent = <&aic>;
666 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
669 gpio-controller;
670 #gpio-cells = <2>;
671 gpio-ranges = <&pinctrl_aop 0 0 42>;
674 interrupt-controller;
675 #interrupt-cells = <2>;
676 interrupt-parent = <&aic>;
687 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
689 interrupt-parent = <&aic>;
694 interrupt-names = "send-empty", "send-not-empty",
695 "recv-empty", "recv-not-empty";
696 #mbox-cells = <0>;
697 power-domains = <&ps_ans2>;
701 compatible = "apple,t8103-sart";
703 power-domains = <&ps_ans2>;
707 compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
710 reg-names = "nvme", "ans";
711 interrupt-parent = <&aic>;
715 power-domains = <&ps_ans2>, <&ps_apcie_st>;
716 power-domain-names = "ans", "apcie0";
721 compatible = "apple,t8103-dart";
723 #iommu-cells = <1>;
724 interrupt-parent = <&aic>;
726 power-domains = <&ps_apcie_gp>;
730 compatible = "apple,t8103-dart";
732 #iommu-cells = <1>;
733 interrupt-parent = <&aic>;
735 power-domains = <&ps_apcie_gp>;
740 compatible = "apple,t8103-dart";
742 #iommu-cells = <1>;
743 interrupt-parent = <&aic>;
745 power-domains = <&ps_apcie_gp>;
750 compatible = "apple,t8103-pcie", "apple,pcie";
758 reg-names = "config", "rc", "port0", "port1", "port2";
760 interrupt-parent = <&aic>;
765 msi-controller;
766 msi-parent = <&pcie0>;
767 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
770 iommu-map = <0x100 &pcie0_dart_0 1 1>,
773 iommu-map-mask = <0xff00>;
775 bus-range = <0 3>;
776 #address-cells = <3>;
777 #size-cells = <2>;
781 power-domains = <&ps_apcie_gp>;
782 pinctrl-0 = <&pcie_pins>;
783 pinctrl-names = "default";
788 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>;
790 #address-cells = <3>;
791 #size-cells = <2>;
794 interrupt-controller;
795 #interrupt-cells = <1>;
797 interrupt-map-mask = <0 0 0 7>;
798 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
807 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>;
809 #address-cells = <3>;
810 #size-cells = <2>;
813 interrupt-controller;
814 #interrupt-cells = <1>;
816 interrupt-map-mask = <0 0 0 7>;
817 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
827 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
829 #address-cells = <3>;
830 #size-cells = <2>;
833 interrupt-controller;
834 #interrupt-cells = <1>;
836 interrupt-map-mask = <0 0 0 7>;
837 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
847 #include "t8103-pmgr.dtsi"