1b823f98fSScott Wood /*
2b823f98fSScott Wood * OpenPIC emulation
3b823f98fSScott Wood *
4b823f98fSScott Wood * Copyright (c) 2004 Jocelyn Mayer
5b823f98fSScott Wood * 2011 Alexander Graf
6b823f98fSScott Wood *
7b823f98fSScott Wood * Permission is hereby granted, free of charge, to any person obtaining a copy
8b823f98fSScott Wood * of this software and associated documentation files (the "Software"), to deal
9b823f98fSScott Wood * in the Software without restriction, including without limitation the rights
10b823f98fSScott Wood * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11b823f98fSScott Wood * copies of the Software, and to permit persons to whom the Software is
12b823f98fSScott Wood * furnished to do so, subject to the following conditions:
13b823f98fSScott Wood *
14b823f98fSScott Wood * The above copyright notice and this permission notice shall be included in
15b823f98fSScott Wood * all copies or substantial portions of the Software.
16b823f98fSScott Wood *
17b823f98fSScott Wood * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18b823f98fSScott Wood * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19b823f98fSScott Wood * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20b823f98fSScott Wood * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21b823f98fSScott Wood * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22b823f98fSScott Wood * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23b823f98fSScott Wood * THE SOFTWARE.
24b823f98fSScott Wood */
25b823f98fSScott Wood
265df554adSScott Wood #include <linux/slab.h>
275df554adSScott Wood #include <linux/mutex.h>
285df554adSScott Wood #include <linux/kvm_host.h>
295df554adSScott Wood #include <linux/errno.h>
305df554adSScott Wood #include <linux/fs.h>
315df554adSScott Wood #include <linux/anon_inodes.h>
32*7c0f6ba6SLinus Torvalds #include <linux/uaccess.h>
335df554adSScott Wood #include <asm/mpic.h>
345df554adSScott Wood #include <asm/kvm_para.h>
355df554adSScott Wood #include <asm/kvm_ppc.h>
36af669ac6SAndre Przywara #include <kvm/iodev.h>
375df554adSScott Wood
38b823f98fSScott Wood #define MAX_CPU 32
39b823f98fSScott Wood #define MAX_SRC 256
40b823f98fSScott Wood #define MAX_TMR 4
41b823f98fSScott Wood #define MAX_IPI 4
42b823f98fSScott Wood #define MAX_MSI 8
43b823f98fSScott Wood #define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR)
44b823f98fSScott Wood #define VID 0x03 /* MPIC version ID */
45b823f98fSScott Wood
46b823f98fSScott Wood /* OpenPIC capability flags */
47b823f98fSScott Wood #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
48b823f98fSScott Wood #define OPENPIC_FLAG_ILR (2 << 0)
49b823f98fSScott Wood
50b823f98fSScott Wood /* OpenPIC address map */
515df554adSScott Wood #define OPENPIC_REG_SIZE 0x40000
52b823f98fSScott Wood #define OPENPIC_GLB_REG_START 0x0
53b823f98fSScott Wood #define OPENPIC_GLB_REG_SIZE 0x10F0
54b823f98fSScott Wood #define OPENPIC_TMR_REG_START 0x10F0
55b823f98fSScott Wood #define OPENPIC_TMR_REG_SIZE 0x220
56b823f98fSScott Wood #define OPENPIC_MSI_REG_START 0x1600
57b823f98fSScott Wood #define OPENPIC_MSI_REG_SIZE 0x200
58b823f98fSScott Wood #define OPENPIC_SUMMARY_REG_START 0x3800
59b823f98fSScott Wood #define OPENPIC_SUMMARY_REG_SIZE 0x800
60b823f98fSScott Wood #define OPENPIC_SRC_REG_START 0x10000
61b823f98fSScott Wood #define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
62b823f98fSScott Wood #define OPENPIC_CPU_REG_START 0x20000
63f0f5c481SScott Wood #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000))
64b823f98fSScott Wood
65f0f5c481SScott Wood struct fsl_mpic_info {
66b823f98fSScott Wood int max_ext;
67f0f5c481SScott Wood };
68b823f98fSScott Wood
69f0f5c481SScott Wood static struct fsl_mpic_info fsl_mpic_20 = {
70b823f98fSScott Wood .max_ext = 12,
71b823f98fSScott Wood };
72b823f98fSScott Wood
73f0f5c481SScott Wood static struct fsl_mpic_info fsl_mpic_42 = {
74b823f98fSScott Wood .max_ext = 12,
75b823f98fSScott Wood };
76b823f98fSScott Wood
77b823f98fSScott Wood #define FRR_NIRQ_SHIFT 16
78b823f98fSScott Wood #define FRR_NCPU_SHIFT 8
79b823f98fSScott Wood #define FRR_VID_SHIFT 0
80b823f98fSScott Wood
81b823f98fSScott Wood #define VID_REVISION_1_2 2
82b823f98fSScott Wood #define VID_REVISION_1_3 3
83b823f98fSScott Wood
84b823f98fSScott Wood #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */
85b823f98fSScott Wood
86b823f98fSScott Wood #define GCR_RESET 0x80000000
87b823f98fSScott Wood #define GCR_MODE_PASS 0x00000000
88b823f98fSScott Wood #define GCR_MODE_MIXED 0x20000000
89b823f98fSScott Wood #define GCR_MODE_PROXY 0x60000000
90b823f98fSScott Wood
91b823f98fSScott Wood #define TBCR_CI 0x80000000 /* count inhibit */
92b823f98fSScott Wood #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
93b823f98fSScott Wood
94b823f98fSScott Wood #define IDR_EP_SHIFT 31
95b823f98fSScott Wood #define IDR_EP_MASK (1 << IDR_EP_SHIFT)
96b823f98fSScott Wood #define IDR_CI0_SHIFT 30
97b823f98fSScott Wood #define IDR_CI1_SHIFT 29
98b823f98fSScott Wood #define IDR_P1_SHIFT 1
99b823f98fSScott Wood #define IDR_P0_SHIFT 0
100b823f98fSScott Wood
101b823f98fSScott Wood #define ILR_INTTGT_MASK 0x000000ff
102b823f98fSScott Wood #define ILR_INTTGT_INT 0x00
103b823f98fSScott Wood #define ILR_INTTGT_CINT 0x01 /* critical */
104b823f98fSScott Wood #define ILR_INTTGT_MCP 0x02 /* machine check */
1055df554adSScott Wood #define NUM_OUTPUTS 3
106b823f98fSScott Wood
107b823f98fSScott Wood #define MSIIR_OFFSET 0x140
108b823f98fSScott Wood #define MSIIR_SRS_SHIFT 29
109b823f98fSScott Wood #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
110b823f98fSScott Wood #define MSIIR_IBS_SHIFT 24
111b823f98fSScott Wood #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT)
112b823f98fSScott Wood
get_current_cpu(void)113b823f98fSScott Wood static int get_current_cpu(void)
114b823f98fSScott Wood {
1155df554adSScott Wood #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
1165df554adSScott Wood struct kvm_vcpu *vcpu = current->thread.kvm_vcpu;
117eb1e4f43SScott Wood return vcpu ? vcpu->arch.irq_cpu_id : -1;
1185df554adSScott Wood #else
1195df554adSScott Wood /* XXX */
120b823f98fSScott Wood return -1;
1215df554adSScott Wood #endif
122b823f98fSScott Wood }
123b823f98fSScott Wood
1245df554adSScott Wood static int openpic_cpu_write_internal(void *opaque, gpa_t addr,
1255df554adSScott Wood u32 val, int idx);
1265df554adSScott Wood static int openpic_cpu_read_internal(void *opaque, gpa_t addr,
1275df554adSScott Wood u32 *ptr, int idx);
128aae65596SAlexander Graf static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
129aae65596SAlexander Graf uint32_t val);
130b823f98fSScott Wood
131f0f5c481SScott Wood enum irq_type {
132b823f98fSScott Wood IRQ_TYPE_NORMAL = 0,
133b823f98fSScott Wood IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
134b823f98fSScott Wood IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
135f0f5c481SScott Wood };
136b823f98fSScott Wood
137f0f5c481SScott Wood struct irq_queue {
138b823f98fSScott Wood /* Round up to the nearest 64 IRQs so that the queue length
139b823f98fSScott Wood * won't change when moving between 32 and 64 bit hosts.
140b823f98fSScott Wood */
141b823f98fSScott Wood unsigned long queue[BITS_TO_LONGS((MAX_IRQ + 63) & ~63)];
142b823f98fSScott Wood int next;
143b823f98fSScott Wood int priority;
144f0f5c481SScott Wood };
145b823f98fSScott Wood
146f0f5c481SScott Wood struct irq_source {
147b823f98fSScott Wood uint32_t ivpr; /* IRQ vector/priority register */
148b823f98fSScott Wood uint32_t idr; /* IRQ destination register */
149b823f98fSScott Wood uint32_t destmask; /* bitmap of CPU destinations */
150b823f98fSScott Wood int last_cpu;
1515df554adSScott Wood int output; /* IRQ level, e.g. ILR_INTTGT_INT */
152b823f98fSScott Wood int pending; /* TRUE if IRQ is pending */
153f0f5c481SScott Wood enum irq_type type;
154b823f98fSScott Wood bool level:1; /* level-triggered */
155b823f98fSScott Wood bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
156f0f5c481SScott Wood };
157b823f98fSScott Wood
158b823f98fSScott Wood #define IVPR_MASK_SHIFT 31
159b823f98fSScott Wood #define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT)
160b823f98fSScott Wood #define IVPR_ACTIVITY_SHIFT 30
161b823f98fSScott Wood #define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT)
162b823f98fSScott Wood #define IVPR_MODE_SHIFT 29
163b823f98fSScott Wood #define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT)
164b823f98fSScott Wood #define IVPR_POLARITY_SHIFT 23
165b823f98fSScott Wood #define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT)
166b823f98fSScott Wood #define IVPR_SENSE_SHIFT 22
167b823f98fSScott Wood #define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT)
168b823f98fSScott Wood
169b823f98fSScott Wood #define IVPR_PRIORITY_MASK (0xF << 16)
170b823f98fSScott Wood #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
171b823f98fSScott Wood #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
172b823f98fSScott Wood
173b823f98fSScott Wood /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
174b823f98fSScott Wood #define IDR_EP 0x80000000 /* external pin */
175b823f98fSScott Wood #define IDR_CI 0x40000000 /* critical interrupt */
176b823f98fSScott Wood
177f0f5c481SScott Wood struct irq_dest {
1785df554adSScott Wood struct kvm_vcpu *vcpu;
1795df554adSScott Wood
180b823f98fSScott Wood int32_t ctpr; /* CPU current task priority */
181f0f5c481SScott Wood struct irq_queue raised;
182f0f5c481SScott Wood struct irq_queue servicing;
183b823f98fSScott Wood
184b823f98fSScott Wood /* Count of IRQ sources asserting on non-INT outputs */
1855df554adSScott Wood uint32_t outputs_active[NUM_OUTPUTS];
186f0f5c481SScott Wood };
187b823f98fSScott Wood
188398d8783SScott Wood #define MAX_MMIO_REGIONS 10
189398d8783SScott Wood
190f0f5c481SScott Wood struct openpic {
1915df554adSScott Wood struct kvm *kvm;
1925df554adSScott Wood struct kvm_device *dev;
1935df554adSScott Wood struct kvm_io_device mmio;
194398d8783SScott Wood const struct mem_reg *mmio_regions[MAX_MMIO_REGIONS];
195398d8783SScott Wood int num_mmio_regions;
1965df554adSScott Wood
1975df554adSScott Wood gpa_t reg_base;
1985df554adSScott Wood spinlock_t lock;
1995df554adSScott Wood
200b823f98fSScott Wood /* Behavior control */
201f0f5c481SScott Wood struct fsl_mpic_info *fsl;
202b823f98fSScott Wood uint32_t model;
203b823f98fSScott Wood uint32_t flags;
204b823f98fSScott Wood uint32_t nb_irqs;
205b823f98fSScott Wood uint32_t vid;
206b823f98fSScott Wood uint32_t vir; /* Vendor identification register */
207b823f98fSScott Wood uint32_t vector_mask;
208b823f98fSScott Wood uint32_t tfrr_reset;
209b823f98fSScott Wood uint32_t ivpr_reset;
210b823f98fSScott Wood uint32_t idr_reset;
211b823f98fSScott Wood uint32_t brr1;
212b823f98fSScott Wood uint32_t mpic_mode_mask;
213b823f98fSScott Wood
214b823f98fSScott Wood /* Global registers */
215b823f98fSScott Wood uint32_t frr; /* Feature reporting register */
216b823f98fSScott Wood uint32_t gcr; /* Global configuration register */
217b823f98fSScott Wood uint32_t pir; /* Processor initialization register */
218b823f98fSScott Wood uint32_t spve; /* Spurious vector register */
219b823f98fSScott Wood uint32_t tfrr; /* Timer frequency reporting register */
220b823f98fSScott Wood /* Source registers */
221f0f5c481SScott Wood struct irq_source src[MAX_IRQ];
222b823f98fSScott Wood /* Local registers per output pin */
223f0f5c481SScott Wood struct irq_dest dst[MAX_CPU];
224b823f98fSScott Wood uint32_t nb_cpus;
225b823f98fSScott Wood /* Timer registers */
226b823f98fSScott Wood struct {
227b823f98fSScott Wood uint32_t tccr; /* Global timer current count register */
228b823f98fSScott Wood uint32_t tbcr; /* Global timer base count register */
229b823f98fSScott Wood } timers[MAX_TMR];
230b823f98fSScott Wood /* Shared MSI registers */
231b823f98fSScott Wood struct {
232b823f98fSScott Wood uint32_t msir; /* Shared Message Signaled Interrupt Register */
233b823f98fSScott Wood } msi[MAX_MSI];
234b823f98fSScott Wood uint32_t max_irq;
235b823f98fSScott Wood uint32_t irq_ipi0;
236b823f98fSScott Wood uint32_t irq_tim0;
237b823f98fSScott Wood uint32_t irq_msi;
238f0f5c481SScott Wood };
239b823f98fSScott Wood
2405df554adSScott Wood
mpic_irq_raise(struct openpic * opp,struct irq_dest * dst,int output)2415df554adSScott Wood static void mpic_irq_raise(struct openpic *opp, struct irq_dest *dst,
2425df554adSScott Wood int output)
2435df554adSScott Wood {
2445df554adSScott Wood struct kvm_interrupt irq = {
2455df554adSScott Wood .irq = KVM_INTERRUPT_SET_LEVEL,
2465df554adSScott Wood };
2475df554adSScott Wood
2485df554adSScott Wood if (!dst->vcpu) {
2495df554adSScott Wood pr_debug("%s: destination cpu %d does not exist\n",
2505df554adSScott Wood __func__, (int)(dst - &opp->dst[0]));
2515df554adSScott Wood return;
2525df554adSScott Wood }
2535df554adSScott Wood
254eb1e4f43SScott Wood pr_debug("%s: cpu %d output %d\n", __func__, dst->vcpu->arch.irq_cpu_id,
2555df554adSScott Wood output);
2565df554adSScott Wood
2575df554adSScott Wood if (output != ILR_INTTGT_INT) /* TODO */
2585df554adSScott Wood return;
2595df554adSScott Wood
2605df554adSScott Wood kvm_vcpu_ioctl_interrupt(dst->vcpu, &irq);
2615df554adSScott Wood }
2625df554adSScott Wood
mpic_irq_lower(struct openpic * opp,struct irq_dest * dst,int output)2635df554adSScott Wood static void mpic_irq_lower(struct openpic *opp, struct irq_dest *dst,
2645df554adSScott Wood int output)
2655df554adSScott Wood {
2665df554adSScott Wood if (!dst->vcpu) {
2675df554adSScott Wood pr_debug("%s: destination cpu %d does not exist\n",
2685df554adSScott Wood __func__, (int)(dst - &opp->dst[0]));
2695df554adSScott Wood return;
2705df554adSScott Wood }
2715df554adSScott Wood
272eb1e4f43SScott Wood pr_debug("%s: cpu %d output %d\n", __func__, dst->vcpu->arch.irq_cpu_id,
2735df554adSScott Wood output);
2745df554adSScott Wood
2755df554adSScott Wood if (output != ILR_INTTGT_INT) /* TODO */
2765df554adSScott Wood return;
2775df554adSScott Wood
2785df554adSScott Wood kvmppc_core_dequeue_external(dst->vcpu);
2795df554adSScott Wood }
2805df554adSScott Wood
IRQ_setbit(struct irq_queue * q,int n_IRQ)281f0f5c481SScott Wood static inline void IRQ_setbit(struct irq_queue *q, int n_IRQ)
282b823f98fSScott Wood {
283b823f98fSScott Wood set_bit(n_IRQ, q->queue);
284b823f98fSScott Wood }
285b823f98fSScott Wood
IRQ_resetbit(struct irq_queue * q,int n_IRQ)286f0f5c481SScott Wood static inline void IRQ_resetbit(struct irq_queue *q, int n_IRQ)
287b823f98fSScott Wood {
288b823f98fSScott Wood clear_bit(n_IRQ, q->queue);
289b823f98fSScott Wood }
290b823f98fSScott Wood
IRQ_check(struct openpic * opp,struct irq_queue * q)291f0f5c481SScott Wood static void IRQ_check(struct openpic *opp, struct irq_queue *q)
292b823f98fSScott Wood {
293b823f98fSScott Wood int irq = -1;
294b823f98fSScott Wood int next = -1;
295b823f98fSScott Wood int priority = -1;
296b823f98fSScott Wood
297b823f98fSScott Wood for (;;) {
298b823f98fSScott Wood irq = find_next_bit(q->queue, opp->max_irq, irq + 1);
299f0f5c481SScott Wood if (irq == opp->max_irq)
300b823f98fSScott Wood break;
301b823f98fSScott Wood
302f0f5c481SScott Wood pr_debug("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
303b823f98fSScott Wood irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);
304b823f98fSScott Wood
305b823f98fSScott Wood if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
306b823f98fSScott Wood next = irq;
307b823f98fSScott Wood priority = IVPR_PRIORITY(opp->src[irq].ivpr);
308b823f98fSScott Wood }
309b823f98fSScott Wood }
310b823f98fSScott Wood
311b823f98fSScott Wood q->next = next;
312b823f98fSScott Wood q->priority = priority;
313b823f98fSScott Wood }
314b823f98fSScott Wood
IRQ_get_next(struct openpic * opp,struct irq_queue * q)315f0f5c481SScott Wood static int IRQ_get_next(struct openpic *opp, struct irq_queue *q)
316b823f98fSScott Wood {
317b823f98fSScott Wood /* XXX: optimize */
318b823f98fSScott Wood IRQ_check(opp, q);
319b823f98fSScott Wood
320b823f98fSScott Wood return q->next;
321b823f98fSScott Wood }
322b823f98fSScott Wood
IRQ_local_pipe(struct openpic * opp,int n_CPU,int n_IRQ,bool active,bool was_active)323f0f5c481SScott Wood static void IRQ_local_pipe(struct openpic *opp, int n_CPU, int n_IRQ,
324b823f98fSScott Wood bool active, bool was_active)
325b823f98fSScott Wood {
326f0f5c481SScott Wood struct irq_dest *dst;
327f0f5c481SScott Wood struct irq_source *src;
328b823f98fSScott Wood int priority;
329b823f98fSScott Wood
330b823f98fSScott Wood dst = &opp->dst[n_CPU];
331b823f98fSScott Wood src = &opp->src[n_IRQ];
332b823f98fSScott Wood
333f0f5c481SScott Wood pr_debug("%s: IRQ %d active %d was %d\n",
334b823f98fSScott Wood __func__, n_IRQ, active, was_active);
335b823f98fSScott Wood
3365df554adSScott Wood if (src->output != ILR_INTTGT_INT) {
337f0f5c481SScott Wood pr_debug("%s: output %d irq %d active %d was %d count %d\n",
338b823f98fSScott Wood __func__, src->output, n_IRQ, active, was_active,
339b823f98fSScott Wood dst->outputs_active[src->output]);
340b823f98fSScott Wood
341b823f98fSScott Wood /* On Freescale MPIC, critical interrupts ignore priority,
342b823f98fSScott Wood * IACK, EOI, etc. Before MPIC v4.1 they also ignore
343b823f98fSScott Wood * masking.
344b823f98fSScott Wood */
345b823f98fSScott Wood if (active) {
346f0f5c481SScott Wood if (!was_active &&
347f0f5c481SScott Wood dst->outputs_active[src->output]++ == 0) {
348f0f5c481SScott Wood pr_debug("%s: Raise OpenPIC output %d cpu %d irq %d\n",
349b823f98fSScott Wood __func__, src->output, n_CPU, n_IRQ);
3505df554adSScott Wood mpic_irq_raise(opp, dst, src->output);
351b823f98fSScott Wood }
352b823f98fSScott Wood } else {
353f0f5c481SScott Wood if (was_active &&
354f0f5c481SScott Wood --dst->outputs_active[src->output] == 0) {
355f0f5c481SScott Wood pr_debug("%s: Lower OpenPIC output %d cpu %d irq %d\n",
356b823f98fSScott Wood __func__, src->output, n_CPU, n_IRQ);
3575df554adSScott Wood mpic_irq_lower(opp, dst, src->output);
358b823f98fSScott Wood }
359b823f98fSScott Wood }
360b823f98fSScott Wood
361b823f98fSScott Wood return;
362b823f98fSScott Wood }
363b823f98fSScott Wood
364b823f98fSScott Wood priority = IVPR_PRIORITY(src->ivpr);
365b823f98fSScott Wood
366b823f98fSScott Wood /* Even if the interrupt doesn't have enough priority,
367b823f98fSScott Wood * it is still raised, in case ctpr is lowered later.
368b823f98fSScott Wood */
369f0f5c481SScott Wood if (active)
370b823f98fSScott Wood IRQ_setbit(&dst->raised, n_IRQ);
371f0f5c481SScott Wood else
372b823f98fSScott Wood IRQ_resetbit(&dst->raised, n_IRQ);
373b823f98fSScott Wood
374b823f98fSScott Wood IRQ_check(opp, &dst->raised);
375b823f98fSScott Wood
376b823f98fSScott Wood if (active && priority <= dst->ctpr) {
377f0f5c481SScott Wood pr_debug("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
378b823f98fSScott Wood __func__, n_IRQ, priority, dst->ctpr, n_CPU);
379b823f98fSScott Wood active = 0;
380b823f98fSScott Wood }
381b823f98fSScott Wood
382b823f98fSScott Wood if (active) {
383b823f98fSScott Wood if (IRQ_get_next(opp, &dst->servicing) >= 0 &&
384b823f98fSScott Wood priority <= dst->servicing.priority) {
385f0f5c481SScott Wood pr_debug("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
386b823f98fSScott Wood __func__, n_IRQ, dst->servicing.next, n_CPU);
387b823f98fSScott Wood } else {
388f0f5c481SScott Wood pr_debug("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
389b823f98fSScott Wood __func__, n_CPU, n_IRQ, dst->raised.next);
3905df554adSScott Wood mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
391b823f98fSScott Wood }
392b823f98fSScott Wood } else {
393b823f98fSScott Wood IRQ_get_next(opp, &dst->servicing);
394b823f98fSScott Wood if (dst->raised.priority > dst->ctpr &&
395b823f98fSScott Wood dst->raised.priority > dst->servicing.priority) {
396f0f5c481SScott Wood pr_debug("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
397b823f98fSScott Wood __func__, n_IRQ, dst->raised.next,
398b823f98fSScott Wood dst->raised.priority, dst->ctpr,
399b823f98fSScott Wood dst->servicing.priority, n_CPU);
400b823f98fSScott Wood /* IRQ line stays asserted */
401b823f98fSScott Wood } else {
402f0f5c481SScott Wood pr_debug("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
403b823f98fSScott Wood __func__, n_IRQ, dst->ctpr,
404b823f98fSScott Wood dst->servicing.priority, n_CPU);
4055df554adSScott Wood mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
406b823f98fSScott Wood }
407b823f98fSScott Wood }
408b823f98fSScott Wood }
409b823f98fSScott Wood
410b823f98fSScott Wood /* update pic state because registers for n_IRQ have changed value */
openpic_update_irq(struct openpic * opp,int n_IRQ)411f0f5c481SScott Wood static void openpic_update_irq(struct openpic *opp, int n_IRQ)
412b823f98fSScott Wood {
413f0f5c481SScott Wood struct irq_source *src;
414b823f98fSScott Wood bool active, was_active;
415b823f98fSScott Wood int i;
416b823f98fSScott Wood
417b823f98fSScott Wood src = &opp->src[n_IRQ];
418b823f98fSScott Wood active = src->pending;
419b823f98fSScott Wood
420b823f98fSScott Wood if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) {
421b823f98fSScott Wood /* Interrupt source is disabled */
422f0f5c481SScott Wood pr_debug("%s: IRQ %d is disabled\n", __func__, n_IRQ);
423b823f98fSScott Wood active = false;
424b823f98fSScott Wood }
425b823f98fSScott Wood
426b823f98fSScott Wood was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK);
427b823f98fSScott Wood
428b823f98fSScott Wood /*
429b823f98fSScott Wood * We don't have a similar check for already-active because
430b823f98fSScott Wood * ctpr may have changed and we need to withdraw the interrupt.
431b823f98fSScott Wood */
432b823f98fSScott Wood if (!active && !was_active) {
433f0f5c481SScott Wood pr_debug("%s: IRQ %d is already inactive\n", __func__, n_IRQ);
434b823f98fSScott Wood return;
435b823f98fSScott Wood }
436b823f98fSScott Wood
437f0f5c481SScott Wood if (active)
438b823f98fSScott Wood src->ivpr |= IVPR_ACTIVITY_MASK;
439f0f5c481SScott Wood else
440b823f98fSScott Wood src->ivpr &= ~IVPR_ACTIVITY_MASK;
441b823f98fSScott Wood
442b823f98fSScott Wood if (src->destmask == 0) {
443b823f98fSScott Wood /* No target */
444f0f5c481SScott Wood pr_debug("%s: IRQ %d has no target\n", __func__, n_IRQ);
445b823f98fSScott Wood return;
446b823f98fSScott Wood }
447b823f98fSScott Wood
448b823f98fSScott Wood if (src->destmask == (1 << src->last_cpu)) {
449b823f98fSScott Wood /* Only one CPU is allowed to receive this IRQ */
450b823f98fSScott Wood IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active);
451b823f98fSScott Wood } else if (!(src->ivpr & IVPR_MODE_MASK)) {
452b823f98fSScott Wood /* Directed delivery mode */
453b823f98fSScott Wood for (i = 0; i < opp->nb_cpus; i++) {
454b823f98fSScott Wood if (src->destmask & (1 << i)) {
455b823f98fSScott Wood IRQ_local_pipe(opp, i, n_IRQ, active,
456b823f98fSScott Wood was_active);
457b823f98fSScott Wood }
458b823f98fSScott Wood }
459b823f98fSScott Wood } else {
460b823f98fSScott Wood /* Distributed delivery mode */
461b823f98fSScott Wood for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
462f0f5c481SScott Wood if (i == opp->nb_cpus)
463b823f98fSScott Wood i = 0;
464f0f5c481SScott Wood
465b823f98fSScott Wood if (src->destmask & (1 << i)) {
466b823f98fSScott Wood IRQ_local_pipe(opp, i, n_IRQ, active,
467b823f98fSScott Wood was_active);
468b823f98fSScott Wood src->last_cpu = i;
469b823f98fSScott Wood break;
470b823f98fSScott Wood }
471b823f98fSScott Wood }
472b823f98fSScott Wood }
473b823f98fSScott Wood }
474b823f98fSScott Wood
openpic_set_irq(void * opaque,int n_IRQ,int level)475b823f98fSScott Wood static void openpic_set_irq(void *opaque, int n_IRQ, int level)
476b823f98fSScott Wood {
477f0f5c481SScott Wood struct openpic *opp = opaque;
478f0f5c481SScott Wood struct irq_source *src;
479b823f98fSScott Wood
480b823f98fSScott Wood if (n_IRQ >= MAX_IRQ) {
4815df554adSScott Wood WARN_ONCE(1, "%s: IRQ %d out of range\n", __func__, n_IRQ);
4825df554adSScott Wood return;
483b823f98fSScott Wood }
484b823f98fSScott Wood
485b823f98fSScott Wood src = &opp->src[n_IRQ];
486f0f5c481SScott Wood pr_debug("openpic: set irq %d = %d ivpr=0x%08x\n",
487b823f98fSScott Wood n_IRQ, level, src->ivpr);
488b823f98fSScott Wood if (src->level) {
489b823f98fSScott Wood /* level-sensitive irq */
490b823f98fSScott Wood src->pending = level;
491b823f98fSScott Wood openpic_update_irq(opp, n_IRQ);
492b823f98fSScott Wood } else {
493b823f98fSScott Wood /* edge-sensitive irq */
494b823f98fSScott Wood if (level) {
495b823f98fSScott Wood src->pending = 1;
496b823f98fSScott Wood openpic_update_irq(opp, n_IRQ);
497b823f98fSScott Wood }
498b823f98fSScott Wood
4995df554adSScott Wood if (src->output != ILR_INTTGT_INT) {
500b823f98fSScott Wood /* Edge-triggered interrupts shouldn't be used
501b823f98fSScott Wood * with non-INT delivery, but just in case,
502b823f98fSScott Wood * try to make it do something sane rather than
503b823f98fSScott Wood * cause an interrupt storm. This is close to
504b823f98fSScott Wood * what you'd probably see happen in real hardware.
505b823f98fSScott Wood */
506b823f98fSScott Wood src->pending = 0;
507b823f98fSScott Wood openpic_update_irq(opp, n_IRQ);
508b823f98fSScott Wood }
509b823f98fSScott Wood }
510b823f98fSScott Wood }
511b823f98fSScott Wood
openpic_reset(struct openpic * opp)5125df554adSScott Wood static void openpic_reset(struct openpic *opp)
513b823f98fSScott Wood {
514b823f98fSScott Wood int i;
515b823f98fSScott Wood
516b823f98fSScott Wood opp->gcr = GCR_RESET;
517b823f98fSScott Wood /* Initialise controller registers */
518b823f98fSScott Wood opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) |
519b823f98fSScott Wood (opp->vid << FRR_VID_SHIFT);
520b823f98fSScott Wood
521b823f98fSScott Wood opp->pir = 0;
522b823f98fSScott Wood opp->spve = -1 & opp->vector_mask;
523b823f98fSScott Wood opp->tfrr = opp->tfrr_reset;
524b823f98fSScott Wood /* Initialise IRQ sources */
525b823f98fSScott Wood for (i = 0; i < opp->max_irq; i++) {
526b823f98fSScott Wood opp->src[i].ivpr = opp->ivpr_reset;
527b823f98fSScott Wood
528b823f98fSScott Wood switch (opp->src[i].type) {
529b823f98fSScott Wood case IRQ_TYPE_NORMAL:
530b823f98fSScott Wood opp->src[i].level =
531b823f98fSScott Wood !!(opp->ivpr_reset & IVPR_SENSE_MASK);
532b823f98fSScott Wood break;
533b823f98fSScott Wood
534b823f98fSScott Wood case IRQ_TYPE_FSLINT:
535b823f98fSScott Wood opp->src[i].ivpr |= IVPR_POLARITY_MASK;
536b823f98fSScott Wood break;
537b823f98fSScott Wood
538b823f98fSScott Wood case IRQ_TYPE_FSLSPECIAL:
539b823f98fSScott Wood break;
540b823f98fSScott Wood }
541aae65596SAlexander Graf
542aae65596SAlexander Graf write_IRQreg_idr(opp, i, opp->idr_reset);
543b823f98fSScott Wood }
544b823f98fSScott Wood /* Initialise IRQ destinations */
545b823f98fSScott Wood for (i = 0; i < MAX_CPU; i++) {
546b823f98fSScott Wood opp->dst[i].ctpr = 15;
547f0f5c481SScott Wood memset(&opp->dst[i].raised, 0, sizeof(struct irq_queue));
548b823f98fSScott Wood opp->dst[i].raised.next = -1;
549f0f5c481SScott Wood memset(&opp->dst[i].servicing, 0, sizeof(struct irq_queue));
550b823f98fSScott Wood opp->dst[i].servicing.next = -1;
551b823f98fSScott Wood }
552b823f98fSScott Wood /* Initialise timers */
553b823f98fSScott Wood for (i = 0; i < MAX_TMR; i++) {
554b823f98fSScott Wood opp->timers[i].tccr = 0;
555b823f98fSScott Wood opp->timers[i].tbcr = TBCR_CI;
556b823f98fSScott Wood }
557b823f98fSScott Wood /* Go out of RESET state */
558b823f98fSScott Wood opp->gcr = 0;
559b823f98fSScott Wood }
560b823f98fSScott Wood
read_IRQreg_idr(struct openpic * opp,int n_IRQ)561f0f5c481SScott Wood static inline uint32_t read_IRQreg_idr(struct openpic *opp, int n_IRQ)
562b823f98fSScott Wood {
563b823f98fSScott Wood return opp->src[n_IRQ].idr;
564b823f98fSScott Wood }
565b823f98fSScott Wood
read_IRQreg_ilr(struct openpic * opp,int n_IRQ)566f0f5c481SScott Wood static inline uint32_t read_IRQreg_ilr(struct openpic *opp, int n_IRQ)
567b823f98fSScott Wood {
568f0f5c481SScott Wood if (opp->flags & OPENPIC_FLAG_ILR)
5695df554adSScott Wood return opp->src[n_IRQ].output;
570b823f98fSScott Wood
571b823f98fSScott Wood return 0xffffffff;
572b823f98fSScott Wood }
573b823f98fSScott Wood
read_IRQreg_ivpr(struct openpic * opp,int n_IRQ)574f0f5c481SScott Wood static inline uint32_t read_IRQreg_ivpr(struct openpic *opp, int n_IRQ)
575b823f98fSScott Wood {
576b823f98fSScott Wood return opp->src[n_IRQ].ivpr;
577b823f98fSScott Wood }
578b823f98fSScott Wood
write_IRQreg_idr(struct openpic * opp,int n_IRQ,uint32_t val)579f0f5c481SScott Wood static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
580f0f5c481SScott Wood uint32_t val)
581b823f98fSScott Wood {
582f0f5c481SScott Wood struct irq_source *src = &opp->src[n_IRQ];
583b823f98fSScott Wood uint32_t normal_mask = (1UL << opp->nb_cpus) - 1;
584b823f98fSScott Wood uint32_t crit_mask = 0;
585b823f98fSScott Wood uint32_t mask = normal_mask;
586b823f98fSScott Wood int crit_shift = IDR_EP_SHIFT - opp->nb_cpus;
587b823f98fSScott Wood int i;
588b823f98fSScott Wood
589b823f98fSScott Wood if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
590b823f98fSScott Wood crit_mask = mask << crit_shift;
591b823f98fSScott Wood mask |= crit_mask | IDR_EP;
592b823f98fSScott Wood }
593b823f98fSScott Wood
594b823f98fSScott Wood src->idr = val & mask;
595f0f5c481SScott Wood pr_debug("Set IDR %d to 0x%08x\n", n_IRQ, src->idr);
596b823f98fSScott Wood
597b823f98fSScott Wood if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
598b823f98fSScott Wood if (src->idr & crit_mask) {
599b823f98fSScott Wood if (src->idr & normal_mask) {
600f0f5c481SScott Wood pr_debug("%s: IRQ configured for multiple output types, using critical\n",
601f0f5c481SScott Wood __func__);
602b823f98fSScott Wood }
603b823f98fSScott Wood
6045df554adSScott Wood src->output = ILR_INTTGT_CINT;
605b823f98fSScott Wood src->nomask = true;
606b823f98fSScott Wood src->destmask = 0;
607b823f98fSScott Wood
608b823f98fSScott Wood for (i = 0; i < opp->nb_cpus; i++) {
609b823f98fSScott Wood int n_ci = IDR_CI0_SHIFT - i;
610b823f98fSScott Wood
611f0f5c481SScott Wood if (src->idr & (1UL << n_ci))
612b823f98fSScott Wood src->destmask |= 1UL << i;
613b823f98fSScott Wood }
614b823f98fSScott Wood } else {
6155df554adSScott Wood src->output = ILR_INTTGT_INT;
616b823f98fSScott Wood src->nomask = false;
617b823f98fSScott Wood src->destmask = src->idr & normal_mask;
618b823f98fSScott Wood }
619b823f98fSScott Wood } else {
620b823f98fSScott Wood src->destmask = src->idr;
621b823f98fSScott Wood }
622b823f98fSScott Wood }
623b823f98fSScott Wood
write_IRQreg_ilr(struct openpic * opp,int n_IRQ,uint32_t val)624f0f5c481SScott Wood static inline void write_IRQreg_ilr(struct openpic *opp, int n_IRQ,
625f0f5c481SScott Wood uint32_t val)
626b823f98fSScott Wood {
627b823f98fSScott Wood if (opp->flags & OPENPIC_FLAG_ILR) {
628f0f5c481SScott Wood struct irq_source *src = &opp->src[n_IRQ];
629b823f98fSScott Wood
6305df554adSScott Wood src->output = val & ILR_INTTGT_MASK;
631f0f5c481SScott Wood pr_debug("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr,
632b823f98fSScott Wood src->output);
633b823f98fSScott Wood
634b823f98fSScott Wood /* TODO: on MPIC v4.0 only, set nomask for non-INT */
635b823f98fSScott Wood }
636b823f98fSScott Wood }
637b823f98fSScott Wood
write_IRQreg_ivpr(struct openpic * opp,int n_IRQ,uint32_t val)638f0f5c481SScott Wood static inline void write_IRQreg_ivpr(struct openpic *opp, int n_IRQ,
639b823f98fSScott Wood uint32_t val)
640b823f98fSScott Wood {
641b823f98fSScott Wood uint32_t mask;
642b823f98fSScott Wood
643b823f98fSScott Wood /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
644b823f98fSScott Wood * the polarity bit is read-only on internal interrupts.
645b823f98fSScott Wood */
646b823f98fSScott Wood mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK |
647b823f98fSScott Wood IVPR_POLARITY_MASK | opp->vector_mask;
648b823f98fSScott Wood
649b823f98fSScott Wood /* ACTIVITY bit is read-only */
650b823f98fSScott Wood opp->src[n_IRQ].ivpr =
651b823f98fSScott Wood (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
652b823f98fSScott Wood
653b823f98fSScott Wood /* For FSL internal interrupts, The sense bit is reserved and zero,
654b823f98fSScott Wood * and the interrupt is always level-triggered. Timers and IPIs
655b823f98fSScott Wood * have no sense or polarity bits, and are edge-triggered.
656b823f98fSScott Wood */
657b823f98fSScott Wood switch (opp->src[n_IRQ].type) {
658b823f98fSScott Wood case IRQ_TYPE_NORMAL:
659b823f98fSScott Wood opp->src[n_IRQ].level =
660b823f98fSScott Wood !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK);
661b823f98fSScott Wood break;
662b823f98fSScott Wood
663b823f98fSScott Wood case IRQ_TYPE_FSLINT:
664b823f98fSScott Wood opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK;
665b823f98fSScott Wood break;
666b823f98fSScott Wood
667b823f98fSScott Wood case IRQ_TYPE_FSLSPECIAL:
668b823f98fSScott Wood opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK);
669b823f98fSScott Wood break;
670b823f98fSScott Wood }
671b823f98fSScott Wood
672b823f98fSScott Wood openpic_update_irq(opp, n_IRQ);
673f0f5c481SScott Wood pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
674b823f98fSScott Wood opp->src[n_IRQ].ivpr);
675b823f98fSScott Wood }
676b823f98fSScott Wood
openpic_gcr_write(struct openpic * opp,uint64_t val)677f0f5c481SScott Wood static void openpic_gcr_write(struct openpic *opp, uint64_t val)
678b823f98fSScott Wood {
679b823f98fSScott Wood if (val & GCR_RESET) {
6805df554adSScott Wood openpic_reset(opp);
681b823f98fSScott Wood return;
682b823f98fSScott Wood }
683b823f98fSScott Wood
684b823f98fSScott Wood opp->gcr &= ~opp->mpic_mode_mask;
685b823f98fSScott Wood opp->gcr |= val & opp->mpic_mode_mask;
686b823f98fSScott Wood }
687b823f98fSScott Wood
openpic_gbl_write(void * opaque,gpa_t addr,u32 val)6885df554adSScott Wood static int openpic_gbl_write(void *opaque, gpa_t addr, u32 val)
689b823f98fSScott Wood {
690f0f5c481SScott Wood struct openpic *opp = opaque;
6915df554adSScott Wood int err = 0;
692b823f98fSScott Wood
6935df554adSScott Wood pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
694f0f5c481SScott Wood if (addr & 0xF)
6955df554adSScott Wood return 0;
696f0f5c481SScott Wood
697b823f98fSScott Wood switch (addr) {
698b823f98fSScott Wood case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
699b823f98fSScott Wood break;
700b823f98fSScott Wood case 0x40:
701b823f98fSScott Wood case 0x50:
702b823f98fSScott Wood case 0x60:
703b823f98fSScott Wood case 0x70:
704b823f98fSScott Wood case 0x80:
705b823f98fSScott Wood case 0x90:
706b823f98fSScott Wood case 0xA0:
707b823f98fSScott Wood case 0xB0:
7085df554adSScott Wood err = openpic_cpu_write_internal(opp, addr, val,
7095df554adSScott Wood get_current_cpu());
710b823f98fSScott Wood break;
711b823f98fSScott Wood case 0x1000: /* FRR */
712b823f98fSScott Wood break;
713b823f98fSScott Wood case 0x1020: /* GCR */
714b823f98fSScott Wood openpic_gcr_write(opp, val);
715b823f98fSScott Wood break;
716b823f98fSScott Wood case 0x1080: /* VIR */
717b823f98fSScott Wood break;
718b823f98fSScott Wood case 0x1090: /* PIR */
7195df554adSScott Wood /*
7205df554adSScott Wood * This register is used to reset a CPU core --
7215df554adSScott Wood * let userspace handle it.
7225df554adSScott Wood */
7235df554adSScott Wood err = -ENXIO;
724b823f98fSScott Wood break;
725b823f98fSScott Wood case 0x10A0: /* IPI_IVPR */
726b823f98fSScott Wood case 0x10B0:
727b823f98fSScott Wood case 0x10C0:
728f0f5c481SScott Wood case 0x10D0: {
729b823f98fSScott Wood int idx;
730b823f98fSScott Wood idx = (addr - 0x10A0) >> 4;
731b823f98fSScott Wood write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val);
732b823f98fSScott Wood break;
733f0f5c481SScott Wood }
734b823f98fSScott Wood case 0x10E0: /* SPVE */
735b823f98fSScott Wood opp->spve = val & opp->vector_mask;
736b823f98fSScott Wood break;
737b823f98fSScott Wood default:
738b823f98fSScott Wood break;
739b823f98fSScott Wood }
7405df554adSScott Wood
7415df554adSScott Wood return err;
742b823f98fSScott Wood }
743b823f98fSScott Wood
openpic_gbl_read(void * opaque,gpa_t addr,u32 * ptr)7445df554adSScott Wood static int openpic_gbl_read(void *opaque, gpa_t addr, u32 *ptr)
745b823f98fSScott Wood {
746f0f5c481SScott Wood struct openpic *opp = opaque;
7475df554adSScott Wood u32 retval;
7485df554adSScott Wood int err = 0;
749b823f98fSScott Wood
7505df554adSScott Wood pr_debug("%s: addr %#llx\n", __func__, addr);
751b823f98fSScott Wood retval = 0xFFFFFFFF;
752f0f5c481SScott Wood if (addr & 0xF)
7535df554adSScott Wood goto out;
754f0f5c481SScott Wood
755b823f98fSScott Wood switch (addr) {
756b823f98fSScott Wood case 0x1000: /* FRR */
757b823f98fSScott Wood retval = opp->frr;
7585df554adSScott Wood retval |= (opp->nb_cpus - 1) << FRR_NCPU_SHIFT;
759b823f98fSScott Wood break;
760b823f98fSScott Wood case 0x1020: /* GCR */
761b823f98fSScott Wood retval = opp->gcr;
762b823f98fSScott Wood break;
763b823f98fSScott Wood case 0x1080: /* VIR */
764b823f98fSScott Wood retval = opp->vir;
765b823f98fSScott Wood break;
766b823f98fSScott Wood case 0x1090: /* PIR */
767b823f98fSScott Wood retval = 0x00000000;
768b823f98fSScott Wood break;
769b823f98fSScott Wood case 0x00: /* Block Revision Register1 (BRR1) */
770b823f98fSScott Wood retval = opp->brr1;
771b823f98fSScott Wood break;
772b823f98fSScott Wood case 0x40:
773b823f98fSScott Wood case 0x50:
774b823f98fSScott Wood case 0x60:
775b823f98fSScott Wood case 0x70:
776b823f98fSScott Wood case 0x80:
777b823f98fSScott Wood case 0x90:
778b823f98fSScott Wood case 0xA0:
779b823f98fSScott Wood case 0xB0:
7805df554adSScott Wood err = openpic_cpu_read_internal(opp, addr,
7815df554adSScott Wood &retval, get_current_cpu());
782b823f98fSScott Wood break;
783b823f98fSScott Wood case 0x10A0: /* IPI_IVPR */
784b823f98fSScott Wood case 0x10B0:
785b823f98fSScott Wood case 0x10C0:
786b823f98fSScott Wood case 0x10D0:
787b823f98fSScott Wood {
788b823f98fSScott Wood int idx;
789b823f98fSScott Wood idx = (addr - 0x10A0) >> 4;
790b823f98fSScott Wood retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx);
791b823f98fSScott Wood }
792b823f98fSScott Wood break;
793b823f98fSScott Wood case 0x10E0: /* SPVE */
794b823f98fSScott Wood retval = opp->spve;
795b823f98fSScott Wood break;
796b823f98fSScott Wood default:
797b823f98fSScott Wood break;
798b823f98fSScott Wood }
799b823f98fSScott Wood
8005df554adSScott Wood out:
8015df554adSScott Wood pr_debug("%s: => 0x%08x\n", __func__, retval);
8025df554adSScott Wood *ptr = retval;
8035df554adSScott Wood return err;
804b823f98fSScott Wood }
805b823f98fSScott Wood
openpic_tmr_write(void * opaque,gpa_t addr,u32 val)8065df554adSScott Wood static int openpic_tmr_write(void *opaque, gpa_t addr, u32 val)
807b823f98fSScott Wood {
808f0f5c481SScott Wood struct openpic *opp = opaque;
809b823f98fSScott Wood int idx;
810b823f98fSScott Wood
811b823f98fSScott Wood addr += 0x10f0;
812b823f98fSScott Wood
8135df554adSScott Wood pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
814f0f5c481SScott Wood if (addr & 0xF)
8155df554adSScott Wood return 0;
816b823f98fSScott Wood
817b823f98fSScott Wood if (addr == 0x10f0) {
818b823f98fSScott Wood /* TFRR */
819b823f98fSScott Wood opp->tfrr = val;
8205df554adSScott Wood return 0;
821b823f98fSScott Wood }
822b823f98fSScott Wood
823b823f98fSScott Wood idx = (addr >> 6) & 0x3;
824b823f98fSScott Wood addr = addr & 0x30;
825b823f98fSScott Wood
826b823f98fSScott Wood switch (addr & 0x30) {
827b823f98fSScott Wood case 0x00: /* TCCR */
828b823f98fSScott Wood break;
829b823f98fSScott Wood case 0x10: /* TBCR */
830b823f98fSScott Wood if ((opp->timers[idx].tccr & TCCR_TOG) != 0 &&
831b823f98fSScott Wood (val & TBCR_CI) == 0 &&
832f0f5c481SScott Wood (opp->timers[idx].tbcr & TBCR_CI) != 0)
833b823f98fSScott Wood opp->timers[idx].tccr &= ~TCCR_TOG;
834f0f5c481SScott Wood
835b823f98fSScott Wood opp->timers[idx].tbcr = val;
836b823f98fSScott Wood break;
837b823f98fSScott Wood case 0x20: /* TVPR */
838b823f98fSScott Wood write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val);
839b823f98fSScott Wood break;
840b823f98fSScott Wood case 0x30: /* TDR */
841b823f98fSScott Wood write_IRQreg_idr(opp, opp->irq_tim0 + idx, val);
842b823f98fSScott Wood break;
843b823f98fSScott Wood }
8445df554adSScott Wood
8455df554adSScott Wood return 0;
846b823f98fSScott Wood }
847b823f98fSScott Wood
openpic_tmr_read(void * opaque,gpa_t addr,u32 * ptr)8485df554adSScott Wood static int openpic_tmr_read(void *opaque, gpa_t addr, u32 *ptr)
849b823f98fSScott Wood {
850f0f5c481SScott Wood struct openpic *opp = opaque;
851b823f98fSScott Wood uint32_t retval = -1;
852b823f98fSScott Wood int idx;
853b823f98fSScott Wood
8545df554adSScott Wood pr_debug("%s: addr %#llx\n", __func__, addr);
855f0f5c481SScott Wood if (addr & 0xF)
856b823f98fSScott Wood goto out;
857f0f5c481SScott Wood
858b823f98fSScott Wood idx = (addr >> 6) & 0x3;
859b823f98fSScott Wood if (addr == 0x0) {
860b823f98fSScott Wood /* TFRR */
861b823f98fSScott Wood retval = opp->tfrr;
862b823f98fSScott Wood goto out;
863b823f98fSScott Wood }
8645df554adSScott Wood
865b823f98fSScott Wood switch (addr & 0x30) {
866b823f98fSScott Wood case 0x00: /* TCCR */
867b823f98fSScott Wood retval = opp->timers[idx].tccr;
868b823f98fSScott Wood break;
869b823f98fSScott Wood case 0x10: /* TBCR */
870b823f98fSScott Wood retval = opp->timers[idx].tbcr;
871b823f98fSScott Wood break;
872b823f98fSScott Wood case 0x20: /* TIPV */
873b823f98fSScott Wood retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);
874b823f98fSScott Wood break;
875b823f98fSScott Wood case 0x30: /* TIDE (TIDR) */
876b823f98fSScott Wood retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);
877b823f98fSScott Wood break;
878b823f98fSScott Wood }
879b823f98fSScott Wood
880b823f98fSScott Wood out:
881f0f5c481SScott Wood pr_debug("%s: => 0x%08x\n", __func__, retval);
8825df554adSScott Wood *ptr = retval;
8835df554adSScott Wood return 0;
884b823f98fSScott Wood }
885b823f98fSScott Wood
openpic_src_write(void * opaque,gpa_t addr,u32 val)8865df554adSScott Wood static int openpic_src_write(void *opaque, gpa_t addr, u32 val)
887b823f98fSScott Wood {
888f0f5c481SScott Wood struct openpic *opp = opaque;
889b823f98fSScott Wood int idx;
890b823f98fSScott Wood
8915df554adSScott Wood pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
892b823f98fSScott Wood
893b823f98fSScott Wood addr = addr & 0xffff;
894b823f98fSScott Wood idx = addr >> 5;
895b823f98fSScott Wood
896b823f98fSScott Wood switch (addr & 0x1f) {
897b823f98fSScott Wood case 0x00:
898b823f98fSScott Wood write_IRQreg_ivpr(opp, idx, val);
899b823f98fSScott Wood break;
900b823f98fSScott Wood case 0x10:
901b823f98fSScott Wood write_IRQreg_idr(opp, idx, val);
902b823f98fSScott Wood break;
903b823f98fSScott Wood case 0x18:
904b823f98fSScott Wood write_IRQreg_ilr(opp, idx, val);
905b823f98fSScott Wood break;
906b823f98fSScott Wood }
9075df554adSScott Wood
9085df554adSScott Wood return 0;
909b823f98fSScott Wood }
910b823f98fSScott Wood
openpic_src_read(void * opaque,gpa_t addr,u32 * ptr)9115df554adSScott Wood static int openpic_src_read(void *opaque, gpa_t addr, u32 *ptr)
912b823f98fSScott Wood {
913f0f5c481SScott Wood struct openpic *opp = opaque;
914b823f98fSScott Wood uint32_t retval;
915b823f98fSScott Wood int idx;
916b823f98fSScott Wood
9175df554adSScott Wood pr_debug("%s: addr %#llx\n", __func__, addr);
918b823f98fSScott Wood retval = 0xFFFFFFFF;
919b823f98fSScott Wood
920b823f98fSScott Wood addr = addr & 0xffff;
921b823f98fSScott Wood idx = addr >> 5;
922b823f98fSScott Wood
923b823f98fSScott Wood switch (addr & 0x1f) {
924b823f98fSScott Wood case 0x00:
925b823f98fSScott Wood retval = read_IRQreg_ivpr(opp, idx);
926b823f98fSScott Wood break;
927b823f98fSScott Wood case 0x10:
928b823f98fSScott Wood retval = read_IRQreg_idr(opp, idx);
929b823f98fSScott Wood break;
930b823f98fSScott Wood case 0x18:
931b823f98fSScott Wood retval = read_IRQreg_ilr(opp, idx);
932b823f98fSScott Wood break;
933b823f98fSScott Wood }
934b823f98fSScott Wood
935f0f5c481SScott Wood pr_debug("%s: => 0x%08x\n", __func__, retval);
9365df554adSScott Wood *ptr = retval;
9375df554adSScott Wood return 0;
938b823f98fSScott Wood }
939b823f98fSScott Wood
openpic_msi_write(void * opaque,gpa_t addr,u32 val)9405df554adSScott Wood static int openpic_msi_write(void *opaque, gpa_t addr, u32 val)
941b823f98fSScott Wood {
942f0f5c481SScott Wood struct openpic *opp = opaque;
943b823f98fSScott Wood int idx = opp->irq_msi;
944b823f98fSScott Wood int srs, ibs;
945b823f98fSScott Wood
9465df554adSScott Wood pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val);
947f0f5c481SScott Wood if (addr & 0xF)
9485df554adSScott Wood return 0;
949b823f98fSScott Wood
950b823f98fSScott Wood switch (addr) {
951b823f98fSScott Wood case MSIIR_OFFSET:
952b823f98fSScott Wood srs = val >> MSIIR_SRS_SHIFT;
953b823f98fSScott Wood idx += srs;
954b823f98fSScott Wood ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT;
955b823f98fSScott Wood opp->msi[srs].msir |= 1 << ibs;
956b823f98fSScott Wood openpic_set_irq(opp, idx, 1);
957b823f98fSScott Wood break;
958b823f98fSScott Wood default:
959b823f98fSScott Wood /* most registers are read-only, thus ignored */
960b823f98fSScott Wood break;
961b823f98fSScott Wood }
9625df554adSScott Wood
9635df554adSScott Wood return 0;
964b823f98fSScott Wood }
965b823f98fSScott Wood
openpic_msi_read(void * opaque,gpa_t addr,u32 * ptr)9665df554adSScott Wood static int openpic_msi_read(void *opaque, gpa_t addr, u32 *ptr)
967b823f98fSScott Wood {
968f0f5c481SScott Wood struct openpic *opp = opaque;
9695df554adSScott Wood uint32_t r = 0;
970b823f98fSScott Wood int i, srs;
971b823f98fSScott Wood
9725df554adSScott Wood pr_debug("%s: addr %#llx\n", __func__, addr);
973f0f5c481SScott Wood if (addr & 0xF)
9745df554adSScott Wood return -ENXIO;
975b823f98fSScott Wood
976b823f98fSScott Wood srs = addr >> 4;
977b823f98fSScott Wood
978b823f98fSScott Wood switch (addr) {
979b823f98fSScott Wood case 0x00:
980b823f98fSScott Wood case 0x10:
981b823f98fSScott Wood case 0x20:
982b823f98fSScott Wood case 0x30:
983b823f98fSScott Wood case 0x40:
984b823f98fSScott Wood case 0x50:
985b823f98fSScott Wood case 0x60:
986b823f98fSScott Wood case 0x70: /* MSIRs */
987b823f98fSScott Wood r = opp->msi[srs].msir;
988b823f98fSScott Wood /* Clear on read */
989b823f98fSScott Wood opp->msi[srs].msir = 0;
990b823f98fSScott Wood openpic_set_irq(opp, opp->irq_msi + srs, 0);
991b823f98fSScott Wood break;
992b823f98fSScott Wood case 0x120: /* MSISR */
993f0f5c481SScott Wood for (i = 0; i < MAX_MSI; i++)
994b823f98fSScott Wood r |= (opp->msi[i].msir ? 1 : 0) << i;
995b823f98fSScott Wood break;
996b823f98fSScott Wood }
997b823f98fSScott Wood
9985df554adSScott Wood pr_debug("%s: => 0x%08x\n", __func__, r);
9995df554adSScott Wood *ptr = r;
10005df554adSScott Wood return 0;
1001b823f98fSScott Wood }
1002b823f98fSScott Wood
openpic_summary_read(void * opaque,gpa_t addr,u32 * ptr)10035df554adSScott Wood static int openpic_summary_read(void *opaque, gpa_t addr, u32 *ptr)
1004b823f98fSScott Wood {
10055df554adSScott Wood uint32_t r = 0;
1006b823f98fSScott Wood
10075df554adSScott Wood pr_debug("%s: addr %#llx\n", __func__, addr);
1008b823f98fSScott Wood
1009b823f98fSScott Wood /* TODO: EISR/EIMR */
1010b823f98fSScott Wood
10115df554adSScott Wood *ptr = r;
10125df554adSScott Wood return 0;
1013b823f98fSScott Wood }
1014b823f98fSScott Wood
openpic_summary_write(void * opaque,gpa_t addr,u32 val)10155df554adSScott Wood static int openpic_summary_write(void *opaque, gpa_t addr, u32 val)
1016b823f98fSScott Wood {
10175df554adSScott Wood pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val);
1018b823f98fSScott Wood
1019b823f98fSScott Wood /* TODO: EISR/EIMR */
10205df554adSScott Wood return 0;
1021b823f98fSScott Wood }
1022b823f98fSScott Wood
openpic_cpu_write_internal(void * opaque,gpa_t addr,u32 val,int idx)10235df554adSScott Wood static int openpic_cpu_write_internal(void *opaque, gpa_t addr,
10245df554adSScott Wood u32 val, int idx)
1025b823f98fSScott Wood {
1026f0f5c481SScott Wood struct openpic *opp = opaque;
1027f0f5c481SScott Wood struct irq_source *src;
1028f0f5c481SScott Wood struct irq_dest *dst;
1029b823f98fSScott Wood int s_IRQ, n_IRQ;
1030b823f98fSScott Wood
10315df554adSScott Wood pr_debug("%s: cpu %d addr %#llx <= 0x%08x\n", __func__, idx,
1032b823f98fSScott Wood addr, val);
1033b823f98fSScott Wood
1034f0f5c481SScott Wood if (idx < 0)
10355df554adSScott Wood return 0;
1036b823f98fSScott Wood
1037f0f5c481SScott Wood if (addr & 0xF)
10385df554adSScott Wood return 0;
1039f0f5c481SScott Wood
1040b823f98fSScott Wood dst = &opp->dst[idx];
1041b823f98fSScott Wood addr &= 0xFF0;
1042b823f98fSScott Wood switch (addr) {
1043b823f98fSScott Wood case 0x40: /* IPIDR */
1044b823f98fSScott Wood case 0x50:
1045b823f98fSScott Wood case 0x60:
1046b823f98fSScott Wood case 0x70:
1047b823f98fSScott Wood idx = (addr - 0x40) >> 4;
1048b823f98fSScott Wood /* we use IDE as mask which CPUs to deliver the IPI to still. */
1049b823f98fSScott Wood opp->src[opp->irq_ipi0 + idx].destmask |= val;
1050b823f98fSScott Wood openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
1051b823f98fSScott Wood openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
1052b823f98fSScott Wood break;
1053b823f98fSScott Wood case 0x80: /* CTPR */
1054b823f98fSScott Wood dst->ctpr = val & 0x0000000F;
1055b823f98fSScott Wood
1056f0f5c481SScott Wood pr_debug("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
1057b823f98fSScott Wood __func__, idx, dst->ctpr, dst->raised.priority,
1058b823f98fSScott Wood dst->servicing.priority);
1059b823f98fSScott Wood
1060b823f98fSScott Wood if (dst->raised.priority <= dst->ctpr) {
1061f0f5c481SScott Wood pr_debug("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
1062b823f98fSScott Wood __func__, idx);
10635df554adSScott Wood mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
1064b823f98fSScott Wood } else if (dst->raised.priority > dst->servicing.priority) {
1065f0f5c481SScott Wood pr_debug("%s: Raise OpenPIC INT output cpu %d irq %d\n",
1066b823f98fSScott Wood __func__, idx, dst->raised.next);
10675df554adSScott Wood mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
1068b823f98fSScott Wood }
1069b823f98fSScott Wood
1070b823f98fSScott Wood break;
1071b823f98fSScott Wood case 0x90: /* WHOAMI */
1072b823f98fSScott Wood /* Read-only register */
1073b823f98fSScott Wood break;
1074b823f98fSScott Wood case 0xA0: /* IACK */
1075b823f98fSScott Wood /* Read-only register */
1076b823f98fSScott Wood break;
1077de9ba2f3SAlexander Graf case 0xB0: { /* EOI */
1078de9ba2f3SAlexander Graf int notify_eoi;
1079de9ba2f3SAlexander Graf
1080f0f5c481SScott Wood pr_debug("EOI\n");
1081b823f98fSScott Wood s_IRQ = IRQ_get_next(opp, &dst->servicing);
1082b823f98fSScott Wood
1083b823f98fSScott Wood if (s_IRQ < 0) {
1084f0f5c481SScott Wood pr_debug("%s: EOI with no interrupt in service\n",
1085b823f98fSScott Wood __func__);
1086b823f98fSScott Wood break;
1087b823f98fSScott Wood }
1088b823f98fSScott Wood
1089b823f98fSScott Wood IRQ_resetbit(&dst->servicing, s_IRQ);
1090de9ba2f3SAlexander Graf /* Notify listeners that the IRQ is over */
1091de9ba2f3SAlexander Graf notify_eoi = s_IRQ;
1092b823f98fSScott Wood /* Set up next servicing IRQ */
1093b823f98fSScott Wood s_IRQ = IRQ_get_next(opp, &dst->servicing);
1094b823f98fSScott Wood /* Check queued interrupts. */
1095b823f98fSScott Wood n_IRQ = IRQ_get_next(opp, &dst->raised);
1096b823f98fSScott Wood src = &opp->src[n_IRQ];
1097b823f98fSScott Wood if (n_IRQ != -1 &&
1098b823f98fSScott Wood (s_IRQ == -1 ||
1099b823f98fSScott Wood IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) {
1100f0f5c481SScott Wood pr_debug("Raise OpenPIC INT output cpu %d irq %d\n",
1101b823f98fSScott Wood idx, n_IRQ);
11025df554adSScott Wood mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
1103b823f98fSScott Wood }
1104de9ba2f3SAlexander Graf
1105de9ba2f3SAlexander Graf spin_unlock(&opp->lock);
1106de9ba2f3SAlexander Graf kvm_notify_acked_irq(opp->kvm, 0, notify_eoi);
1107de9ba2f3SAlexander Graf spin_lock(&opp->lock);
1108de9ba2f3SAlexander Graf
1109b823f98fSScott Wood break;
1110de9ba2f3SAlexander Graf }
1111b823f98fSScott Wood default:
1112b823f98fSScott Wood break;
1113b823f98fSScott Wood }
11145df554adSScott Wood
11155df554adSScott Wood return 0;
1116b823f98fSScott Wood }
1117b823f98fSScott Wood
openpic_cpu_write(void * opaque,gpa_t addr,u32 val)11185df554adSScott Wood static int openpic_cpu_write(void *opaque, gpa_t addr, u32 val)
1119b823f98fSScott Wood {
11205df554adSScott Wood struct openpic *opp = opaque;
11215df554adSScott Wood
11225df554adSScott Wood return openpic_cpu_write_internal(opp, addr, val,
11235df554adSScott Wood (addr & 0x1f000) >> 12);
1124b823f98fSScott Wood }
1125b823f98fSScott Wood
openpic_iack(struct openpic * opp,struct irq_dest * dst,int cpu)1126f0f5c481SScott Wood static uint32_t openpic_iack(struct openpic *opp, struct irq_dest *dst,
1127f0f5c481SScott Wood int cpu)
1128b823f98fSScott Wood {
1129f0f5c481SScott Wood struct irq_source *src;
1130b823f98fSScott Wood int retval, irq;
1131b823f98fSScott Wood
1132f0f5c481SScott Wood pr_debug("Lower OpenPIC INT output\n");
11335df554adSScott Wood mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
1134b823f98fSScott Wood
1135b823f98fSScott Wood irq = IRQ_get_next(opp, &dst->raised);
1136f0f5c481SScott Wood pr_debug("IACK: irq=%d\n", irq);
1137b823f98fSScott Wood
1138f0f5c481SScott Wood if (irq == -1)
1139b823f98fSScott Wood /* No more interrupt pending */
1140b823f98fSScott Wood return opp->spve;
1141b823f98fSScott Wood
1142b823f98fSScott Wood src = &opp->src[irq];
1143b823f98fSScott Wood if (!(src->ivpr & IVPR_ACTIVITY_MASK) ||
1144b823f98fSScott Wood !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) {
1145f0f5c481SScott Wood pr_err("%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n",
1146b823f98fSScott Wood __func__, irq, dst->ctpr, src->ivpr);
1147b823f98fSScott Wood openpic_update_irq(opp, irq);
1148b823f98fSScott Wood retval = opp->spve;
1149b823f98fSScott Wood } else {
1150b823f98fSScott Wood /* IRQ enter servicing state */
1151b823f98fSScott Wood IRQ_setbit(&dst->servicing, irq);
1152b823f98fSScott Wood retval = IVPR_VECTOR(opp, src->ivpr);
1153b823f98fSScott Wood }
1154b823f98fSScott Wood
1155b823f98fSScott Wood if (!src->level) {
1156b823f98fSScott Wood /* edge-sensitive IRQ */
1157b823f98fSScott Wood src->ivpr &= ~IVPR_ACTIVITY_MASK;
1158b823f98fSScott Wood src->pending = 0;
1159b823f98fSScott Wood IRQ_resetbit(&dst->raised, irq);
1160b823f98fSScott Wood }
1161b823f98fSScott Wood
1162b823f98fSScott Wood if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + MAX_IPI))) {
1163b823f98fSScott Wood src->destmask &= ~(1 << cpu);
1164b823f98fSScott Wood if (src->destmask && !src->level) {
1165b823f98fSScott Wood /* trigger on CPUs that didn't know about it yet */
1166b823f98fSScott Wood openpic_set_irq(opp, irq, 1);
1167b823f98fSScott Wood openpic_set_irq(opp, irq, 0);
1168b823f98fSScott Wood /* if all CPUs knew about it, set active bit again */
1169b823f98fSScott Wood src->ivpr |= IVPR_ACTIVITY_MASK;
1170b823f98fSScott Wood }
1171b823f98fSScott Wood }
1172b823f98fSScott Wood
1173b823f98fSScott Wood return retval;
1174b823f98fSScott Wood }
1175b823f98fSScott Wood
kvmppc_mpic_set_epr(struct kvm_vcpu * vcpu)1176eb1e4f43SScott Wood void kvmppc_mpic_set_epr(struct kvm_vcpu *vcpu)
1177eb1e4f43SScott Wood {
1178eb1e4f43SScott Wood struct openpic *opp = vcpu->arch.mpic;
1179eb1e4f43SScott Wood int cpu = vcpu->arch.irq_cpu_id;
1180eb1e4f43SScott Wood unsigned long flags;
1181eb1e4f43SScott Wood
1182eb1e4f43SScott Wood spin_lock_irqsave(&opp->lock, flags);
1183eb1e4f43SScott Wood
1184eb1e4f43SScott Wood if ((opp->gcr & opp->mpic_mode_mask) == GCR_MODE_PROXY)
1185eb1e4f43SScott Wood kvmppc_set_epr(vcpu, openpic_iack(opp, &opp->dst[cpu], cpu));
1186eb1e4f43SScott Wood
1187eb1e4f43SScott Wood spin_unlock_irqrestore(&opp->lock, flags);
1188eb1e4f43SScott Wood }
1189eb1e4f43SScott Wood
openpic_cpu_read_internal(void * opaque,gpa_t addr,u32 * ptr,int idx)11905df554adSScott Wood static int openpic_cpu_read_internal(void *opaque, gpa_t addr,
11915df554adSScott Wood u32 *ptr, int idx)
1192b823f98fSScott Wood {
1193f0f5c481SScott Wood struct openpic *opp = opaque;
1194f0f5c481SScott Wood struct irq_dest *dst;
1195b823f98fSScott Wood uint32_t retval;
1196b823f98fSScott Wood
11975df554adSScott Wood pr_debug("%s: cpu %d addr %#llx\n", __func__, idx, addr);
1198b823f98fSScott Wood retval = 0xFFFFFFFF;
1199b823f98fSScott Wood
1200f0f5c481SScott Wood if (idx < 0)
12015df554adSScott Wood goto out;
1202b823f98fSScott Wood
1203f0f5c481SScott Wood if (addr & 0xF)
12045df554adSScott Wood goto out;
1205f0f5c481SScott Wood
1206b823f98fSScott Wood dst = &opp->dst[idx];
1207b823f98fSScott Wood addr &= 0xFF0;
1208b823f98fSScott Wood switch (addr) {
1209b823f98fSScott Wood case 0x80: /* CTPR */
1210b823f98fSScott Wood retval = dst->ctpr;
1211b823f98fSScott Wood break;
1212b823f98fSScott Wood case 0x90: /* WHOAMI */
1213b823f98fSScott Wood retval = idx;
1214b823f98fSScott Wood break;
1215b823f98fSScott Wood case 0xA0: /* IACK */
1216b823f98fSScott Wood retval = openpic_iack(opp, dst, idx);
1217b823f98fSScott Wood break;
1218b823f98fSScott Wood case 0xB0: /* EOI */
1219b823f98fSScott Wood retval = 0;
1220b823f98fSScott Wood break;
1221b823f98fSScott Wood default:
1222b823f98fSScott Wood break;
1223b823f98fSScott Wood }
1224f0f5c481SScott Wood pr_debug("%s: => 0x%08x\n", __func__, retval);
1225b823f98fSScott Wood
12265df554adSScott Wood out:
12275df554adSScott Wood *ptr = retval;
12285df554adSScott Wood return 0;
1229b823f98fSScott Wood }
1230b823f98fSScott Wood
openpic_cpu_read(void * opaque,gpa_t addr,u32 * ptr)12315df554adSScott Wood static int openpic_cpu_read(void *opaque, gpa_t addr, u32 *ptr)
1232b823f98fSScott Wood {
12335df554adSScott Wood struct openpic *opp = opaque;
12345df554adSScott Wood
12355df554adSScott Wood return openpic_cpu_read_internal(opp, addr, ptr,
12365df554adSScott Wood (addr & 0x1f000) >> 12);
1237b823f98fSScott Wood }
1238b823f98fSScott Wood
1239f0f5c481SScott Wood struct mem_reg {
12405df554adSScott Wood int (*read)(void *opaque, gpa_t addr, u32 *ptr);
12415df554adSScott Wood int (*write)(void *opaque, gpa_t addr, u32 val);
1242f0f5c481SScott Wood gpa_t start_addr;
1243f0f5c481SScott Wood int size;
1244f0f5c481SScott Wood };
1245b823f98fSScott Wood
1246398d8783SScott Wood static const struct mem_reg openpic_gbl_mmio = {
12475df554adSScott Wood .write = openpic_gbl_write,
12485df554adSScott Wood .read = openpic_gbl_read,
12495df554adSScott Wood .start_addr = OPENPIC_GLB_REG_START,
12505df554adSScott Wood .size = OPENPIC_GLB_REG_SIZE,
12515df554adSScott Wood };
12525df554adSScott Wood
1253398d8783SScott Wood static const struct mem_reg openpic_tmr_mmio = {
12545df554adSScott Wood .write = openpic_tmr_write,
12555df554adSScott Wood .read = openpic_tmr_read,
12565df554adSScott Wood .start_addr = OPENPIC_TMR_REG_START,
12575df554adSScott Wood .size = OPENPIC_TMR_REG_SIZE,
12585df554adSScott Wood };
12595df554adSScott Wood
1260398d8783SScott Wood static const struct mem_reg openpic_cpu_mmio = {
12615df554adSScott Wood .write = openpic_cpu_write,
12625df554adSScott Wood .read = openpic_cpu_read,
12635df554adSScott Wood .start_addr = OPENPIC_CPU_REG_START,
12645df554adSScott Wood .size = OPENPIC_CPU_REG_SIZE,
12655df554adSScott Wood };
12665df554adSScott Wood
1267398d8783SScott Wood static const struct mem_reg openpic_src_mmio = {
12685df554adSScott Wood .write = openpic_src_write,
12695df554adSScott Wood .read = openpic_src_read,
12705df554adSScott Wood .start_addr = OPENPIC_SRC_REG_START,
12715df554adSScott Wood .size = OPENPIC_SRC_REG_SIZE,
12725df554adSScott Wood };
12735df554adSScott Wood
1274398d8783SScott Wood static const struct mem_reg openpic_msi_mmio = {
12755df554adSScott Wood .read = openpic_msi_read,
12765df554adSScott Wood .write = openpic_msi_write,
12775df554adSScott Wood .start_addr = OPENPIC_MSI_REG_START,
12785df554adSScott Wood .size = OPENPIC_MSI_REG_SIZE,
12795df554adSScott Wood };
12805df554adSScott Wood
1281398d8783SScott Wood static const struct mem_reg openpic_summary_mmio = {
12825df554adSScott Wood .read = openpic_summary_read,
12835df554adSScott Wood .write = openpic_summary_write,
12845df554adSScott Wood .start_addr = OPENPIC_SUMMARY_REG_START,
12855df554adSScott Wood .size = OPENPIC_SUMMARY_REG_SIZE,
12865df554adSScott Wood };
12875df554adSScott Wood
add_mmio_region(struct openpic * opp,const struct mem_reg * mr)1288398d8783SScott Wood static void add_mmio_region(struct openpic *opp, const struct mem_reg *mr)
1289398d8783SScott Wood {
1290398d8783SScott Wood if (opp->num_mmio_regions >= MAX_MMIO_REGIONS) {
1291398d8783SScott Wood WARN(1, "kvm mpic: too many mmio regions\n");
1292398d8783SScott Wood return;
1293398d8783SScott Wood }
1294398d8783SScott Wood
1295398d8783SScott Wood opp->mmio_regions[opp->num_mmio_regions++] = mr;
1296398d8783SScott Wood }
1297398d8783SScott Wood
fsl_common_init(struct openpic * opp)1298f0f5c481SScott Wood static void fsl_common_init(struct openpic *opp)
1299b823f98fSScott Wood {
1300b823f98fSScott Wood int i;
1301b823f98fSScott Wood int virq = MAX_SRC;
1302b823f98fSScott Wood
1303398d8783SScott Wood add_mmio_region(opp, &openpic_msi_mmio);
1304398d8783SScott Wood add_mmio_region(opp, &openpic_summary_mmio);
13055df554adSScott Wood
1306b823f98fSScott Wood opp->vid = VID_REVISION_1_2;
1307b823f98fSScott Wood opp->vir = VIR_GENERIC;
1308b823f98fSScott Wood opp->vector_mask = 0xFFFF;
1309b823f98fSScott Wood opp->tfrr_reset = 0;
1310b823f98fSScott Wood opp->ivpr_reset = IVPR_MASK_MASK;
1311b823f98fSScott Wood opp->idr_reset = 1 << 0;
1312b823f98fSScott Wood opp->max_irq = MAX_IRQ;
1313b823f98fSScott Wood
1314b823f98fSScott Wood opp->irq_ipi0 = virq;
1315b823f98fSScott Wood virq += MAX_IPI;
1316b823f98fSScott Wood opp->irq_tim0 = virq;
1317b823f98fSScott Wood virq += MAX_TMR;
1318b823f98fSScott Wood
13195df554adSScott Wood BUG_ON(virq > MAX_IRQ);
1320b823f98fSScott Wood
1321b823f98fSScott Wood opp->irq_msi = 224;
1322b823f98fSScott Wood
1323f0f5c481SScott Wood for (i = 0; i < opp->fsl->max_ext; i++)
1324b823f98fSScott Wood opp->src[i].level = false;
1325b823f98fSScott Wood
1326b823f98fSScott Wood /* Internal interrupts, including message and MSI */
1327b823f98fSScott Wood for (i = 16; i < MAX_SRC; i++) {
1328b823f98fSScott Wood opp->src[i].type = IRQ_TYPE_FSLINT;
1329b823f98fSScott Wood opp->src[i].level = true;
1330b823f98fSScott Wood }
1331b823f98fSScott Wood
1332b823f98fSScott Wood /* timers and IPIs */
1333b823f98fSScott Wood for (i = MAX_SRC; i < virq; i++) {
1334b823f98fSScott Wood opp->src[i].type = IRQ_TYPE_FSLSPECIAL;
1335b823f98fSScott Wood opp->src[i].level = false;
1336b823f98fSScott Wood }
1337b823f98fSScott Wood }
1338b823f98fSScott Wood
kvm_mpic_read_internal(struct openpic * opp,gpa_t addr,u32 * ptr)13395df554adSScott Wood static int kvm_mpic_read_internal(struct openpic *opp, gpa_t addr, u32 *ptr)
1340b823f98fSScott Wood {
1341398d8783SScott Wood int i;
1342b823f98fSScott Wood
1343398d8783SScott Wood for (i = 0; i < opp->num_mmio_regions; i++) {
1344398d8783SScott Wood const struct mem_reg *mr = opp->mmio_regions[i];
1345b823f98fSScott Wood
13465df554adSScott Wood if (mr->start_addr > addr || addr >= mr->start_addr + mr->size)
13475df554adSScott Wood continue;
1348b823f98fSScott Wood
13495df554adSScott Wood return mr->read(opp, addr - mr->start_addr, ptr);
1350b823f98fSScott Wood }
1351b823f98fSScott Wood
13525df554adSScott Wood return -ENXIO;
13535df554adSScott Wood }
13545df554adSScott Wood
kvm_mpic_write_internal(struct openpic * opp,gpa_t addr,u32 val)13555df554adSScott Wood static int kvm_mpic_write_internal(struct openpic *opp, gpa_t addr, u32 val)
1356b823f98fSScott Wood {
1357398d8783SScott Wood int i;
13585df554adSScott Wood
1359398d8783SScott Wood for (i = 0; i < opp->num_mmio_regions; i++) {
1360398d8783SScott Wood const struct mem_reg *mr = opp->mmio_regions[i];
13615df554adSScott Wood
13625df554adSScott Wood if (mr->start_addr > addr || addr >= mr->start_addr + mr->size)
13635df554adSScott Wood continue;
13645df554adSScott Wood
13655df554adSScott Wood return mr->write(opp, addr - mr->start_addr, val);
13665df554adSScott Wood }
13675df554adSScott Wood
13685df554adSScott Wood return -ENXIO;
13695df554adSScott Wood }
13705df554adSScott Wood
kvm_mpic_read(struct kvm_vcpu * vcpu,struct kvm_io_device * this,gpa_t addr,int len,void * ptr)1371e32edf4fSNikolay Nikolaev static int kvm_mpic_read(struct kvm_vcpu *vcpu,
1372e32edf4fSNikolay Nikolaev struct kvm_io_device *this,
1373e32edf4fSNikolay Nikolaev gpa_t addr, int len, void *ptr)
13745df554adSScott Wood {
13755df554adSScott Wood struct openpic *opp = container_of(this, struct openpic, mmio);
13765df554adSScott Wood int ret;
13775df554adSScott Wood union {
13785df554adSScott Wood u32 val;
13795df554adSScott Wood u8 bytes[4];
13805df554adSScott Wood } u;
13815df554adSScott Wood
13825df554adSScott Wood if (addr & (len - 1)) {
13835df554adSScott Wood pr_debug("%s: bad alignment %llx/%d\n",
13845df554adSScott Wood __func__, addr, len);
13855df554adSScott Wood return -EINVAL;
13865df554adSScott Wood }
13875df554adSScott Wood
13885df554adSScott Wood spin_lock_irq(&opp->lock);
13895df554adSScott Wood ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val);
13905df554adSScott Wood spin_unlock_irq(&opp->lock);
13915df554adSScott Wood
13925df554adSScott Wood /*
13935df554adSScott Wood * Technically only 32-bit accesses are allowed, but be nice to
13945df554adSScott Wood * people dumping registers a byte at a time -- it works in real
13955df554adSScott Wood * hardware (reads only, not writes).
13965df554adSScott Wood */
13975df554adSScott Wood if (len == 4) {
13985df554adSScott Wood *(u32 *)ptr = u.val;
13995df554adSScott Wood pr_debug("%s: addr %llx ret %d len 4 val %x\n",
14005df554adSScott Wood __func__, addr, ret, u.val);
14015df554adSScott Wood } else if (len == 1) {
14025df554adSScott Wood *(u8 *)ptr = u.bytes[addr & 3];
14035df554adSScott Wood pr_debug("%s: addr %llx ret %d len 1 val %x\n",
14045df554adSScott Wood __func__, addr, ret, u.bytes[addr & 3]);
14055df554adSScott Wood } else {
14065df554adSScott Wood pr_debug("%s: bad length %d\n", __func__, len);
14075df554adSScott Wood return -EINVAL;
14085df554adSScott Wood }
14095df554adSScott Wood
14105df554adSScott Wood return ret;
14115df554adSScott Wood }
14125df554adSScott Wood
kvm_mpic_write(struct kvm_vcpu * vcpu,struct kvm_io_device * this,gpa_t addr,int len,const void * ptr)1413e32edf4fSNikolay Nikolaev static int kvm_mpic_write(struct kvm_vcpu *vcpu,
1414e32edf4fSNikolay Nikolaev struct kvm_io_device *this,
1415e32edf4fSNikolay Nikolaev gpa_t addr, int len, const void *ptr)
14165df554adSScott Wood {
14175df554adSScott Wood struct openpic *opp = container_of(this, struct openpic, mmio);
14185df554adSScott Wood int ret;
14195df554adSScott Wood
14205df554adSScott Wood if (len != 4) {
14215df554adSScott Wood pr_debug("%s: bad length %d\n", __func__, len);
14225df554adSScott Wood return -EOPNOTSUPP;
14235df554adSScott Wood }
14245df554adSScott Wood if (addr & 3) {
14255df554adSScott Wood pr_debug("%s: bad alignment %llx/%d\n", __func__, addr, len);
14265df554adSScott Wood return -EOPNOTSUPP;
14275df554adSScott Wood }
14285df554adSScott Wood
14295df554adSScott Wood spin_lock_irq(&opp->lock);
14305df554adSScott Wood ret = kvm_mpic_write_internal(opp, addr - opp->reg_base,
14315df554adSScott Wood *(const u32 *)ptr);
14325df554adSScott Wood spin_unlock_irq(&opp->lock);
14335df554adSScott Wood
14345df554adSScott Wood pr_debug("%s: addr %llx ret %d val %x\n",
14355df554adSScott Wood __func__, addr, ret, *(const u32 *)ptr);
14365df554adSScott Wood
14375df554adSScott Wood return ret;
14385df554adSScott Wood }
14395df554adSScott Wood
14405df554adSScott Wood static const struct kvm_io_device_ops mpic_mmio_ops = {
14415df554adSScott Wood .read = kvm_mpic_read,
14425df554adSScott Wood .write = kvm_mpic_write,
1443b823f98fSScott Wood };
1444b823f98fSScott Wood
map_mmio(struct openpic * opp)14455df554adSScott Wood static void map_mmio(struct openpic *opp)
14465df554adSScott Wood {
14475df554adSScott Wood kvm_iodevice_init(&opp->mmio, &mpic_mmio_ops);
14485df554adSScott Wood
14495df554adSScott Wood kvm_io_bus_register_dev(opp->kvm, KVM_MMIO_BUS,
14505df554adSScott Wood opp->reg_base, OPENPIC_REG_SIZE,
14515df554adSScott Wood &opp->mmio);
14525df554adSScott Wood }
14535df554adSScott Wood
unmap_mmio(struct openpic * opp)14545df554adSScott Wood static void unmap_mmio(struct openpic *opp)
14555df554adSScott Wood {
14565df554adSScott Wood kvm_io_bus_unregister_dev(opp->kvm, KVM_MMIO_BUS, &opp->mmio);
14575df554adSScott Wood }
14585df554adSScott Wood
set_base_addr(struct openpic * opp,struct kvm_device_attr * attr)14595df554adSScott Wood static int set_base_addr(struct openpic *opp, struct kvm_device_attr *attr)
14605df554adSScott Wood {
14615df554adSScott Wood u64 base;
14625df554adSScott Wood
14635df554adSScott Wood if (copy_from_user(&base, (u64 __user *)(long)attr->addr, sizeof(u64)))
14645df554adSScott Wood return -EFAULT;
14655df554adSScott Wood
14665df554adSScott Wood if (base & 0x3ffff) {
14675df554adSScott Wood pr_debug("kvm mpic %s: KVM_DEV_MPIC_BASE_ADDR %08llx not aligned\n",
14685df554adSScott Wood __func__, base);
14695df554adSScott Wood return -EINVAL;
14705df554adSScott Wood }
14715df554adSScott Wood
14725df554adSScott Wood if (base == opp->reg_base)
14735df554adSScott Wood return 0;
14745df554adSScott Wood
14755df554adSScott Wood mutex_lock(&opp->kvm->slots_lock);
14765df554adSScott Wood
14775df554adSScott Wood unmap_mmio(opp);
14785df554adSScott Wood opp->reg_base = base;
14795df554adSScott Wood
14805df554adSScott Wood pr_debug("kvm mpic %s: KVM_DEV_MPIC_BASE_ADDR %08llx\n",
14815df554adSScott Wood __func__, base);
14825df554adSScott Wood
14835df554adSScott Wood if (base == 0)
14845df554adSScott Wood goto out;
14855df554adSScott Wood
14865df554adSScott Wood map_mmio(opp);
14875df554adSScott Wood
14885df554adSScott Wood out:
1489d133b40fSWei Yongjun mutex_unlock(&opp->kvm->slots_lock);
14905df554adSScott Wood return 0;
14915df554adSScott Wood }
14925df554adSScott Wood
14935df554adSScott Wood #define ATTR_SET 0
14945df554adSScott Wood #define ATTR_GET 1
14955df554adSScott Wood
access_reg(struct openpic * opp,gpa_t addr,u32 * val,int type)14965df554adSScott Wood static int access_reg(struct openpic *opp, gpa_t addr, u32 *val, int type)
14975df554adSScott Wood {
14985df554adSScott Wood int ret;
14995df554adSScott Wood
15005df554adSScott Wood if (addr & 3)
15015df554adSScott Wood return -ENXIO;
15025df554adSScott Wood
15035df554adSScott Wood spin_lock_irq(&opp->lock);
15045df554adSScott Wood
15055df554adSScott Wood if (type == ATTR_SET)
15065df554adSScott Wood ret = kvm_mpic_write_internal(opp, addr, *val);
15075df554adSScott Wood else
15085df554adSScott Wood ret = kvm_mpic_read_internal(opp, addr, val);
15095df554adSScott Wood
15105df554adSScott Wood spin_unlock_irq(&opp->lock);
15115df554adSScott Wood
15125df554adSScott Wood pr_debug("%s: type %d addr %llx val %x\n", __func__, type, addr, *val);
15135df554adSScott Wood
15145df554adSScott Wood return ret;
15155df554adSScott Wood }
15165df554adSScott Wood
mpic_set_attr(struct kvm_device * dev,struct kvm_device_attr * attr)15175df554adSScott Wood static int mpic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
15185df554adSScott Wood {
15195df554adSScott Wood struct openpic *opp = dev->private;
15205df554adSScott Wood u32 attr32;
15215df554adSScott Wood
15225df554adSScott Wood switch (attr->group) {
15235df554adSScott Wood case KVM_DEV_MPIC_GRP_MISC:
15245df554adSScott Wood switch (attr->attr) {
15255df554adSScott Wood case KVM_DEV_MPIC_BASE_ADDR:
15265df554adSScott Wood return set_base_addr(opp, attr);
15275df554adSScott Wood }
15285df554adSScott Wood
15295df554adSScott Wood break;
15305df554adSScott Wood
15315df554adSScott Wood case KVM_DEV_MPIC_GRP_REGISTER:
15325df554adSScott Wood if (get_user(attr32, (u32 __user *)(long)attr->addr))
15335df554adSScott Wood return -EFAULT;
15345df554adSScott Wood
15355df554adSScott Wood return access_reg(opp, attr->attr, &attr32, ATTR_SET);
15365df554adSScott Wood
15375df554adSScott Wood case KVM_DEV_MPIC_GRP_IRQ_ACTIVE:
15385df554adSScott Wood if (attr->attr > MAX_SRC)
15395df554adSScott Wood return -EINVAL;
15405df554adSScott Wood
15415df554adSScott Wood if (get_user(attr32, (u32 __user *)(long)attr->addr))
15425df554adSScott Wood return -EFAULT;
15435df554adSScott Wood
15445df554adSScott Wood if (attr32 != 0 && attr32 != 1)
15455df554adSScott Wood return -EINVAL;
15465df554adSScott Wood
15475df554adSScott Wood spin_lock_irq(&opp->lock);
15485df554adSScott Wood openpic_set_irq(opp, attr->attr, attr32);
15495df554adSScott Wood spin_unlock_irq(&opp->lock);
15505df554adSScott Wood return 0;
15515df554adSScott Wood }
15525df554adSScott Wood
15535df554adSScott Wood return -ENXIO;
15545df554adSScott Wood }
15555df554adSScott Wood
mpic_get_attr(struct kvm_device * dev,struct kvm_device_attr * attr)15565df554adSScott Wood static int mpic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
15575df554adSScott Wood {
15585df554adSScott Wood struct openpic *opp = dev->private;
15595df554adSScott Wood u64 attr64;
15605df554adSScott Wood u32 attr32;
15615df554adSScott Wood int ret;
15625df554adSScott Wood
15635df554adSScott Wood switch (attr->group) {
15645df554adSScott Wood case KVM_DEV_MPIC_GRP_MISC:
15655df554adSScott Wood switch (attr->attr) {
15665df554adSScott Wood case KVM_DEV_MPIC_BASE_ADDR:
15675df554adSScott Wood mutex_lock(&opp->kvm->slots_lock);
15685df554adSScott Wood attr64 = opp->reg_base;
15695df554adSScott Wood mutex_unlock(&opp->kvm->slots_lock);
15705df554adSScott Wood
15715df554adSScott Wood if (copy_to_user((u64 __user *)(long)attr->addr,
15725df554adSScott Wood &attr64, sizeof(u64)))
15735df554adSScott Wood return -EFAULT;
15745df554adSScott Wood
15755df554adSScott Wood return 0;
15765df554adSScott Wood }
15775df554adSScott Wood
15785df554adSScott Wood break;
15795df554adSScott Wood
15805df554adSScott Wood case KVM_DEV_MPIC_GRP_REGISTER:
15815df554adSScott Wood ret = access_reg(opp, attr->attr, &attr32, ATTR_GET);
15825df554adSScott Wood if (ret)
15835df554adSScott Wood return ret;
15845df554adSScott Wood
15855df554adSScott Wood if (put_user(attr32, (u32 __user *)(long)attr->addr))
15865df554adSScott Wood return -EFAULT;
15875df554adSScott Wood
15885df554adSScott Wood return 0;
15895df554adSScott Wood
15905df554adSScott Wood case KVM_DEV_MPIC_GRP_IRQ_ACTIVE:
15915df554adSScott Wood if (attr->attr > MAX_SRC)
15925df554adSScott Wood return -EINVAL;
15935df554adSScott Wood
15945df554adSScott Wood spin_lock_irq(&opp->lock);
15955df554adSScott Wood attr32 = opp->src[attr->attr].pending;
15965df554adSScott Wood spin_unlock_irq(&opp->lock);
15975df554adSScott Wood
15985df554adSScott Wood if (put_user(attr32, (u32 __user *)(long)attr->addr))
15995df554adSScott Wood return -EFAULT;
16005df554adSScott Wood
16015df554adSScott Wood return 0;
16025df554adSScott Wood }
16035df554adSScott Wood
16045df554adSScott Wood return -ENXIO;
16055df554adSScott Wood }
16065df554adSScott Wood
mpic_has_attr(struct kvm_device * dev,struct kvm_device_attr * attr)16075df554adSScott Wood static int mpic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
16085df554adSScott Wood {
16095df554adSScott Wood switch (attr->group) {
16105df554adSScott Wood case KVM_DEV_MPIC_GRP_MISC:
16115df554adSScott Wood switch (attr->attr) {
16125df554adSScott Wood case KVM_DEV_MPIC_BASE_ADDR:
16135df554adSScott Wood return 0;
16145df554adSScott Wood }
16155df554adSScott Wood
16165df554adSScott Wood break;
16175df554adSScott Wood
16185df554adSScott Wood case KVM_DEV_MPIC_GRP_REGISTER:
16195df554adSScott Wood return 0;
16205df554adSScott Wood
16215df554adSScott Wood case KVM_DEV_MPIC_GRP_IRQ_ACTIVE:
16225df554adSScott Wood if (attr->attr > MAX_SRC)
16235df554adSScott Wood break;
16245df554adSScott Wood
16255df554adSScott Wood return 0;
16265df554adSScott Wood }
16275df554adSScott Wood
16285df554adSScott Wood return -ENXIO;
16295df554adSScott Wood }
16305df554adSScott Wood
mpic_destroy(struct kvm_device * dev)16315df554adSScott Wood static void mpic_destroy(struct kvm_device *dev)
16325df554adSScott Wood {
16335df554adSScott Wood struct openpic *opp = dev->private;
16345df554adSScott Wood
1635de9ba2f3SAlexander Graf dev->kvm->arch.mpic = NULL;
16365df554adSScott Wood kfree(opp);
1637458ff3c0SGleb Natapov kfree(dev);
16385df554adSScott Wood }
16395df554adSScott Wood
mpic_set_default_irq_routing(struct openpic * opp)1640de9ba2f3SAlexander Graf static int mpic_set_default_irq_routing(struct openpic *opp)
1641de9ba2f3SAlexander Graf {
1642de9ba2f3SAlexander Graf struct kvm_irq_routing_entry *routing;
1643de9ba2f3SAlexander Graf
1644de9ba2f3SAlexander Graf /* Create a nop default map, so that dereferencing it still works */
1645de9ba2f3SAlexander Graf routing = kzalloc((sizeof(*routing)), GFP_KERNEL);
1646de9ba2f3SAlexander Graf if (!routing)
1647de9ba2f3SAlexander Graf return -ENOMEM;
1648de9ba2f3SAlexander Graf
1649de9ba2f3SAlexander Graf kvm_set_irq_routing(opp->kvm, routing, 0, 0);
1650de9ba2f3SAlexander Graf
1651de9ba2f3SAlexander Graf kfree(routing);
1652de9ba2f3SAlexander Graf return 0;
1653de9ba2f3SAlexander Graf }
1654de9ba2f3SAlexander Graf
mpic_create(struct kvm_device * dev,u32 type)16555df554adSScott Wood static int mpic_create(struct kvm_device *dev, u32 type)
16565df554adSScott Wood {
16575df554adSScott Wood struct openpic *opp;
16585df554adSScott Wood int ret;
16595df554adSScott Wood
1660de9ba2f3SAlexander Graf /* We only support one MPIC at a time for now */
1661de9ba2f3SAlexander Graf if (dev->kvm->arch.mpic)
1662de9ba2f3SAlexander Graf return -EINVAL;
1663de9ba2f3SAlexander Graf
16645df554adSScott Wood opp = kzalloc(sizeof(struct openpic), GFP_KERNEL);
16655df554adSScott Wood if (!opp)
16665df554adSScott Wood return -ENOMEM;
16675df554adSScott Wood
16685df554adSScott Wood dev->private = opp;
16695df554adSScott Wood opp->kvm = dev->kvm;
16705df554adSScott Wood opp->dev = dev;
16715df554adSScott Wood opp->model = type;
16725df554adSScott Wood spin_lock_init(&opp->lock);
16735df554adSScott Wood
1674398d8783SScott Wood add_mmio_region(opp, &openpic_gbl_mmio);
1675398d8783SScott Wood add_mmio_region(opp, &openpic_tmr_mmio);
1676398d8783SScott Wood add_mmio_region(opp, &openpic_src_mmio);
1677398d8783SScott Wood add_mmio_region(opp, &openpic_cpu_mmio);
1678b823f98fSScott Wood
1679b823f98fSScott Wood switch (opp->model) {
16805df554adSScott Wood case KVM_DEV_TYPE_FSL_MPIC_20:
1681b823f98fSScott Wood opp->fsl = &fsl_mpic_20;
1682b823f98fSScott Wood opp->brr1 = 0x00400200;
1683b823f98fSScott Wood opp->flags |= OPENPIC_FLAG_IDR_CRIT;
1684b823f98fSScott Wood opp->nb_irqs = 80;
1685b823f98fSScott Wood opp->mpic_mode_mask = GCR_MODE_MIXED;
1686b823f98fSScott Wood
1687b823f98fSScott Wood fsl_common_init(opp);
1688b823f98fSScott Wood
1689b823f98fSScott Wood break;
1690b823f98fSScott Wood
16915df554adSScott Wood case KVM_DEV_TYPE_FSL_MPIC_42:
1692b823f98fSScott Wood opp->fsl = &fsl_mpic_42;
1693b823f98fSScott Wood opp->brr1 = 0x00400402;
1694b823f98fSScott Wood opp->flags |= OPENPIC_FLAG_ILR;
1695b823f98fSScott Wood opp->nb_irqs = 196;
1696b823f98fSScott Wood opp->mpic_mode_mask = GCR_MODE_PROXY;
1697b823f98fSScott Wood
1698b823f98fSScott Wood fsl_common_init(opp);
1699b823f98fSScott Wood
1700b823f98fSScott Wood break;
17015df554adSScott Wood
17025df554adSScott Wood default:
17035df554adSScott Wood ret = -ENODEV;
17045df554adSScott Wood goto err;
1705b823f98fSScott Wood }
1706b823f98fSScott Wood
1707de9ba2f3SAlexander Graf ret = mpic_set_default_irq_routing(opp);
1708de9ba2f3SAlexander Graf if (ret)
1709de9ba2f3SAlexander Graf goto err;
1710de9ba2f3SAlexander Graf
17115df554adSScott Wood openpic_reset(opp);
1712de9ba2f3SAlexander Graf
1713de9ba2f3SAlexander Graf smp_wmb();
1714de9ba2f3SAlexander Graf dev->kvm->arch.mpic = opp;
1715de9ba2f3SAlexander Graf
1716b823f98fSScott Wood return 0;
17175df554adSScott Wood
17185df554adSScott Wood err:
17195df554adSScott Wood kfree(opp);
17205df554adSScott Wood return ret;
1721b823f98fSScott Wood }
17225df554adSScott Wood
17235df554adSScott Wood struct kvm_device_ops kvm_mpic_ops = {
17245df554adSScott Wood .name = "kvm-mpic",
17255df554adSScott Wood .create = mpic_create,
17265df554adSScott Wood .destroy = mpic_destroy,
17275df554adSScott Wood .set_attr = mpic_set_attr,
17285df554adSScott Wood .get_attr = mpic_get_attr,
17295df554adSScott Wood .has_attr = mpic_has_attr,
17305df554adSScott Wood };
1731eb1e4f43SScott Wood
kvmppc_mpic_connect_vcpu(struct kvm_device * dev,struct kvm_vcpu * vcpu,u32 cpu)1732eb1e4f43SScott Wood int kvmppc_mpic_connect_vcpu(struct kvm_device *dev, struct kvm_vcpu *vcpu,
1733eb1e4f43SScott Wood u32 cpu)
1734eb1e4f43SScott Wood {
1735eb1e4f43SScott Wood struct openpic *opp = dev->private;
1736eb1e4f43SScott Wood int ret = 0;
1737eb1e4f43SScott Wood
1738eb1e4f43SScott Wood if (dev->ops != &kvm_mpic_ops)
1739eb1e4f43SScott Wood return -EPERM;
1740eb1e4f43SScott Wood if (opp->kvm != vcpu->kvm)
1741eb1e4f43SScott Wood return -EPERM;
1742eb1e4f43SScott Wood if (cpu < 0 || cpu >= MAX_CPU)
1743eb1e4f43SScott Wood return -EPERM;
1744eb1e4f43SScott Wood
1745eb1e4f43SScott Wood spin_lock_irq(&opp->lock);
1746eb1e4f43SScott Wood
1747eb1e4f43SScott Wood if (opp->dst[cpu].vcpu) {
1748eb1e4f43SScott Wood ret = -EEXIST;
1749eb1e4f43SScott Wood goto out;
1750eb1e4f43SScott Wood }
1751eb1e4f43SScott Wood if (vcpu->arch.irq_type) {
1752eb1e4f43SScott Wood ret = -EBUSY;
1753eb1e4f43SScott Wood goto out;
1754eb1e4f43SScott Wood }
1755eb1e4f43SScott Wood
1756eb1e4f43SScott Wood opp->dst[cpu].vcpu = vcpu;
1757eb1e4f43SScott Wood opp->nb_cpus = max(opp->nb_cpus, cpu + 1);
1758eb1e4f43SScott Wood
1759eb1e4f43SScott Wood vcpu->arch.mpic = opp;
1760eb1e4f43SScott Wood vcpu->arch.irq_cpu_id = cpu;
1761eb1e4f43SScott Wood vcpu->arch.irq_type = KVMPPC_IRQ_MPIC;
1762eb1e4f43SScott Wood
1763eb1e4f43SScott Wood /* This might need to be changed if GCR gets extended */
1764eb1e4f43SScott Wood if (opp->mpic_mode_mask == GCR_MODE_PROXY)
1765eb1e4f43SScott Wood vcpu->arch.epr_flags |= KVMPPC_EPR_KERNEL;
1766eb1e4f43SScott Wood
1767eb1e4f43SScott Wood out:
1768eb1e4f43SScott Wood spin_unlock_irq(&opp->lock);
1769eb1e4f43SScott Wood return ret;
1770eb1e4f43SScott Wood }
1771eb1e4f43SScott Wood
1772eb1e4f43SScott Wood /*
1773eb1e4f43SScott Wood * This should only happen immediately before the mpic is destroyed,
1774eb1e4f43SScott Wood * so we shouldn't need to worry about anything still trying to
1775eb1e4f43SScott Wood * access the vcpu pointer.
1776eb1e4f43SScott Wood */
kvmppc_mpic_disconnect_vcpu(struct openpic * opp,struct kvm_vcpu * vcpu)1777eb1e4f43SScott Wood void kvmppc_mpic_disconnect_vcpu(struct openpic *opp, struct kvm_vcpu *vcpu)
1778eb1e4f43SScott Wood {
1779eb1e4f43SScott Wood BUG_ON(!opp->dst[vcpu->arch.irq_cpu_id].vcpu);
1780eb1e4f43SScott Wood
1781eb1e4f43SScott Wood opp->dst[vcpu->arch.irq_cpu_id].vcpu = NULL;
1782eb1e4f43SScott Wood }
1783de9ba2f3SAlexander Graf
1784de9ba2f3SAlexander Graf /*
1785de9ba2f3SAlexander Graf * Return value:
1786de9ba2f3SAlexander Graf * < 0 Interrupt was ignored (masked or not delivered for other reasons)
1787de9ba2f3SAlexander Graf * = 0 Interrupt was coalesced (previous irq is still pending)
1788de9ba2f3SAlexander Graf * > 0 Number of CPUs interrupt was delivered to
1789de9ba2f3SAlexander Graf */
mpic_set_irq(struct kvm_kernel_irq_routing_entry * e,struct kvm * kvm,int irq_source_id,int level,bool line_status)1790de9ba2f3SAlexander Graf static int mpic_set_irq(struct kvm_kernel_irq_routing_entry *e,
1791de9ba2f3SAlexander Graf struct kvm *kvm, int irq_source_id, int level,
1792de9ba2f3SAlexander Graf bool line_status)
1793de9ba2f3SAlexander Graf {
1794de9ba2f3SAlexander Graf u32 irq = e->irqchip.pin;
1795de9ba2f3SAlexander Graf struct openpic *opp = kvm->arch.mpic;
1796de9ba2f3SAlexander Graf unsigned long flags;
1797de9ba2f3SAlexander Graf
1798de9ba2f3SAlexander Graf spin_lock_irqsave(&opp->lock, flags);
1799de9ba2f3SAlexander Graf openpic_set_irq(opp, irq, level);
1800de9ba2f3SAlexander Graf spin_unlock_irqrestore(&opp->lock, flags);
1801de9ba2f3SAlexander Graf
1802de9ba2f3SAlexander Graf /* All code paths we care about don't check for the return value */
1803de9ba2f3SAlexander Graf return 0;
1804de9ba2f3SAlexander Graf }
1805de9ba2f3SAlexander Graf
kvm_set_msi(struct kvm_kernel_irq_routing_entry * e,struct kvm * kvm,int irq_source_id,int level,bool line_status)1806de9ba2f3SAlexander Graf int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
1807de9ba2f3SAlexander Graf struct kvm *kvm, int irq_source_id, int level, bool line_status)
1808de9ba2f3SAlexander Graf {
1809de9ba2f3SAlexander Graf struct openpic *opp = kvm->arch.mpic;
1810de9ba2f3SAlexander Graf unsigned long flags;
1811de9ba2f3SAlexander Graf
1812de9ba2f3SAlexander Graf spin_lock_irqsave(&opp->lock, flags);
1813de9ba2f3SAlexander Graf
1814de9ba2f3SAlexander Graf /*
1815de9ba2f3SAlexander Graf * XXX We ignore the target address for now, as we only support
1816de9ba2f3SAlexander Graf * a single MSI bank.
1817de9ba2f3SAlexander Graf */
1818de9ba2f3SAlexander Graf openpic_msi_write(kvm->arch.mpic, MSIIR_OFFSET, e->msi.data);
1819de9ba2f3SAlexander Graf spin_unlock_irqrestore(&opp->lock, flags);
1820de9ba2f3SAlexander Graf
1821de9ba2f3SAlexander Graf /* All code paths we care about don't check for the return value */
1822de9ba2f3SAlexander Graf return 0;
1823de9ba2f3SAlexander Graf }
1824de9ba2f3SAlexander Graf
kvm_set_routing_entry(struct kvm * kvm,struct kvm_kernel_irq_routing_entry * e,const struct kvm_irq_routing_entry * ue)1825c63cf538SRadim Krčmář int kvm_set_routing_entry(struct kvm *kvm,
1826c63cf538SRadim Krčmář struct kvm_kernel_irq_routing_entry *e,
1827de9ba2f3SAlexander Graf const struct kvm_irq_routing_entry *ue)
1828de9ba2f3SAlexander Graf {
1829de9ba2f3SAlexander Graf int r = -EINVAL;
1830de9ba2f3SAlexander Graf
1831de9ba2f3SAlexander Graf switch (ue->type) {
1832de9ba2f3SAlexander Graf case KVM_IRQ_ROUTING_IRQCHIP:
1833de9ba2f3SAlexander Graf e->set = mpic_set_irq;
1834de9ba2f3SAlexander Graf e->irqchip.irqchip = ue->u.irqchip.irqchip;
1835de9ba2f3SAlexander Graf e->irqchip.pin = ue->u.irqchip.pin;
1836de9ba2f3SAlexander Graf if (e->irqchip.pin >= KVM_IRQCHIP_NUM_PINS)
1837de9ba2f3SAlexander Graf goto out;
1838de9ba2f3SAlexander Graf break;
1839de9ba2f3SAlexander Graf case KVM_IRQ_ROUTING_MSI:
1840de9ba2f3SAlexander Graf e->set = kvm_set_msi;
1841de9ba2f3SAlexander Graf e->msi.address_lo = ue->u.msi.address_lo;
1842de9ba2f3SAlexander Graf e->msi.address_hi = ue->u.msi.address_hi;
1843de9ba2f3SAlexander Graf e->msi.data = ue->u.msi.data;
1844de9ba2f3SAlexander Graf break;
1845de9ba2f3SAlexander Graf default:
1846de9ba2f3SAlexander Graf goto out;
1847de9ba2f3SAlexander Graf }
1848de9ba2f3SAlexander Graf
1849de9ba2f3SAlexander Graf r = 0;
1850de9ba2f3SAlexander Graf out:
1851de9ba2f3SAlexander Graf return r;
1852de9ba2f3SAlexander Graf }
1853