/linux/Documentation/devicetree/bindings/powerpc/4xx/ |
H A D | cpm.txt | 4 - compatible : compatible list, currently only "ibm,cpm" 5 - dcr-access-method : "native" 6 - dcr-reg : < DCR register range > 9 - er-offset : All 4xx SoCs with a CPM controller have 10 one of two different order for the CPM 15 er-offset = <1>. 16 - unused-units : specifier consist of one cell. For each 17 bit in the cell, the corresponding bit 20 - idle-doze : specifier consist of one cell. For each 21 bit in the cell, the corresponding bit [all …]
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/linux/fs/afs/ |
H A D | super.c | 105 ret = -ENOMEM; in afs_fs_init() 158 struct afs_super_info *as = AFS_FS_S(root->d_sb); in afs_show_devname() 159 struct afs_volume *volume = as->volume; in afs_show_devname() 160 struct afs_cell *cell = as->cell; in afs_show_devname() local 164 if (as->dyn_root) { in afs_show_devname() 169 switch (volume->type) { in afs_show_devname() 174 if (volume->type_force) in afs_show_devname() 183 seq_printf(m, "%c%s:%s%s", pref, cell->name, volume->name, suf); in afs_show_devname() 192 struct afs_super_info *as = AFS_FS_S(root->d_sb); in afs_show_options() 195 if (as->dyn_root) in afs_show_options() [all …]
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H A D | security.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 14 #include <keys/rxrpc-type.h> 23 struct key *afs_request_key(struct afs_cell *cell) in afs_request_key() argument 27 _enter("{%x}", key_serial(cell->anonymous_key)); in afs_request_key() 29 _debug("key %s", cell->anonymous_key->description); in afs_request_key() 30 key = request_key_net(&key_type_rxrpc, cell->anonymous_key->description, in afs_request_key() 31 cell->net->net, NULL); in afs_request_key() 33 if (PTR_ERR(key) != -ENOKEY) { in afs_request_key() 39 _leave(" = {%x} [anon]", key_serial(cell->anonymous_key)); in afs_request_key() 40 return key_get(cell->anonymous_key); in afs_request_key() [all …]
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H A D | dynroot.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 13 #define AFS_MIN_DYNROOT_CELL_INO 4 /* Allow for ., .., @cell, .@cell */ 25 return inode->i_ino == fid->vnode; in afs_iget5_pseudo_test() 33 struct afs_super_info *as = AFS_FS_S(inode->i_sb); in afs_iget5_pseudo_set() 37 vnode->volume = as->volume; in afs_iget5_pseudo_set() 38 vnode->fid = *fid; in afs_iget5_pseudo_set() 39 inode->i_ino = fid->vnode; in afs_iget5_pseudo_set() 40 inode->i_generation = fid->unique; in afs_iget5_pseudo_set() 58 _leave(" = -ENOMEM"); in afs_iget_pseudo_dir() 59 return ERR_PTR(-ENOMEM); in afs_iget_pseudo_dir() [all …]
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H A D | server_list.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 16 if (slist && refcount_dec_and_test(&slist->usage)) { in afs_put_serverlist() 17 for (i = 0; i < slist->nr_servers; i++) in afs_put_serverlist() 18 afs_unuse_server(net, slist->servers[i].server, in afs_put_serverlist() 33 unsigned int type_mask = 1 << volume->type; in afs_alloc_server_list() 35 int ret = -ENOMEM, nr_servers = 0, newrep = 0, i, j, usable = 0; in afs_alloc_server_list() 37 /* Work out if we're going to restrict to NEWREPSITE-marked servers or in afs_alloc_server_list() 38 * not. If at least one site is marked as NEWREPSITE, then it's likely in afs_alloc_server_list() 39 * that "vos release" is busy updating RO sites. We cut over from one in afs_alloc_server_list() 43 for (i = 0; i < vldb->nr_servers; i++) { in afs_alloc_server_list() [all …]
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/linux/Documentation/devicetree/bindings/mips/cavium/ |
H A D | bootbus.txt | 7 - compatible: "cavium,octeon-3860-bootbus" 11 - reg: The base address of the Boot Bus' register bank. 13 - #address-cells: Must be <2>. The first cell is the chip select 14 within the bootbus. The second cell is the offset from the chip select. 16 - #size-cells: Must be <1>. 18 - ranges: There must be one one triplet of (child-bus-address, 19 parent-bus-address, length) for each active chip select. If the 27 - compatible: "cavium,octeon-3860-bootbus-config" 29 - cavium,cs-index: A single cell indicating the chip select that 32 - cavium,t-adr: A cell specifying the ADR timing (in nS). [all …]
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/linux/Documentation/mm/ |
H A D | numa.rst | 17 Each of the 'cells' may be viewed as an SMP [symmetric multi-processor] subset 18 of the system--although some components necessary for a stand-alone SMP system 19 may not be populated on any given cell. The cells of the NUMA system are 20 connected together with some sort of system interconnect--e.g., a crossbar or 21 point-to-point link are common types of NUMA system interconnects. Both of 27 to and accessible from any CPU attached to any cell and cache coherency 31 away the cell containing the CPU or IO bus making the memory access is from the 32 cell containing the target memory. For example, access to memory by CPUs 33 attached to the same cell will experience faster access times and higher 35 can have cells at multiple remote distances from any given cell. [all …]
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/linux/Documentation/devicetree/bindings/sound/ |
H A D | cirrus,madera.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - patches@opensource.cirrus.com 21 include/dt-bindings/sound/madera.h 26 - $ref: dai-common.yaml# 29 '#sound-dai-cells': 31 The first cell indicating the audio interface. 38 INnAR INnBL INnBR. For non-muxed inputs the first two cells 43 left and right B inputs. Valid mode values are one of the [all …]
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/linux/Documentation/filesystems/ |
H A D | afs.rst | 1 .. SPDX-License-Identifier: GPL-2.0 9 - Overview. 10 - Usage. 11 - Mountpoints. 12 - Dynamic root. 13 - Proc filesystem. 14 - The cell database. 15 - Security. 16 - The @sys substitution. 45 CONFIG_AF_RXRPC - The RxRPC protocol transport [all …]
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/linux/Documentation/devicetree/bindings/iommu/ |
H A D | iommu.txt | 13 Example: 32-bit DMA to 64-bit physical addresses 15 * Implement scatter-gather at page level granularity so that the device does 29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices 30 typically have a fixed association to the master device, whereas multiple- 31 master IOMMU devices can translate accesses from more than one master. 34 "dma-ranges" property that describes how the physical address space of the 35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a 39 -------------------- 40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an 44 the specific IOMMU. Below are a few examples of typical use-cases: [all …]
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/linux/Documentation/driver-api/ |
H A D | nvmem.rst | 1 .. SPDX-License-Identifier: GPL-2.0 20 register a sysfs file, allow in-kernel users to access the content of the 23 This was also a problem as far as other in-kernel users were involved, since 24 the solutions used were pretty much different from one driver to another, there 35 and write the non-volatile memory. 51 .name = "brcm-nvram", 55 config.dev = &pdev->dev; 62 Device drivers can define and register an nvmem cell using the nvmem_cell_info 75 Additionally it is possible to create nvmem cell lookup entries and register 79 .nvmem_name = "i2c-eeprom", [all …]
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/linux/Documentation/devicetree/bindings/powerpc/fsl/ |
H A D | mpc5200.txt | 2 ---------------------------- 4 (c) 2006-2009 Secret Lab Technologies Ltd 8 ------------------ 9 For mpc5200 on-chip devices, the format for each compatible value is 10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver 20 else; the 5200 compatible properties will contain only one item; 21 "fsl,mpc5200-<device>". 29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>"; 34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec"; 35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec"; [all …]
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/linux/Documentation/devicetree/bindings/extcon/ |
H A D | wlf,arizona.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - patches@opensource.cirrus.com 20 wlf,hpdet-channel: 30 wlf,use-jd2: 35 wlf,use-jd2-nopull: 40 wlf,jd-invert: 45 wlf,micd-software-compare: 50 wlf,micd-detect-debounce: [all …]
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/linux/Documentation/ABI/testing/ |
H A D | sysfs-nvmem-cells | 1 What: /sys/bus/nvmem/devices/.../cells/<cell-name> 6 The "cells" folder contains one file per cell exposed by the 8 with <name> being the cell name and <where> its location in 11 the file is the size of the cell (when known). The content of 12 the file is the binary content of the cell (may sometimes be 19 hexdump -C /sys/bus/nvmem/devices/1-00563/cells/product-name@d,0 20 00000000 54 4e 34 38 4d 2d 50 2d 44 4e |TN48M-P-DN|
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/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | cdns,xtensa-pic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 5 --- 6 $id: http://devicetree.org/schemas/interrupt-controller/cdns,xtensa-pic.yaml# 7 $schema: http://devicetree.org/meta-schemas/core.yaml# 12 - Max Filippov <jcmvbkbc@gmail.com> 16 Xtensa built-in Programmable Interrupt Controller (PIC) 21 - cdns,xtensa-mx 22 - cdns,xtensa-pic 24 '#interrupt-cells': 27 Number of cells to define the interrupts. When 1, the first cell is the [all …]
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H A D | arm,vic.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 13 One or more Vectored Interrupt Controllers (VIC's) can be connected in an 15 be nested or have the outputs wire-OR'd together. 18 - $ref: /schemas/interrupt-controller.yaml# 23 - arm,pl190-vic 24 - arm,pl192-vic [all …]
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H A D | interrupts.txt | 5 ------------------------- 8 "interrupts" property, an "interrupts-extended" property, or both. If both are 11 properties contain a list of interrupt specifiers, one per output interrupt. The 16 interrupt-parent = <&intc1>; 19 The "interrupt-parent" property is used to specify the controller to which 25 The "interrupts-extended" property is a special form; useful when a node needs 27 the inherited one. Each entry in this property contains both the parent phandle 31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>; 34 ----------------------------- 36 A device is marked as an interrupt controller with the "interrupt-controller" [all …]
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H A D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marc Zyngier <maz@kernel.org> 15 Software Generated Interrupts (SGI), and Locality-specific Peripheral 19 - $ref: /schemas/interrupt-controller.yaml# 24 - items: 25 - enum: 26 - qcom,msm8996-gic-v3 [all …]
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/linux/Documentation/devicetree/bindings/thermal/ |
H A D | sprd-thermal.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/thermal/sprd-thermal.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Orson Zhai <orsonzhai@gmail.com> 11 - Baolin Wang <baolin.wang7@gmail.com> 12 - Chunyan Zhang <zhang.lyra@gmail.com> 14 $ref: thermal-sensor.yaml# 18 const: sprd,ums512-thermal 26 clock-names: [all …]
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/linux/Documentation/devicetree/bindings/pwm/ |
H A D | loongson,ls7a-pwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pwm/loongson,ls7a-pwm.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Binbin Zhou <zhoubinbin@loongson.cn> 13 The Loongson PWM has one pulse width output signal and one pulse input 15 It can be found on Loongson-2K series cpus and Loongson LS7A bridge chips. 18 - $ref: pwm.yaml# 23 - const: loongson,ls7a-pwm 24 - items: [all …]
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/linux/drivers/md/ |
H A D | dm-bio-prison-v2.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2012-2017 Red Hat, Inc. 9 #include "dm-bio-prison-v2.h" 17 /*----------------------------------------------------------------*/ 31 /*----------------------------------------------------------------*/ 45 prison->wq = wq; in dm_bio_prison_create_v2() 46 spin_lock_init(&prison->lock); in dm_bio_prison_create_v2() 48 ret = mempool_init_slab_pool(&prison->cell_pool, MIN_CELLS, _cell_cache); in dm_bio_prison_create_v2() 54 prison->cells = RB_ROOT; in dm_bio_prison_create_v2() 62 mempool_exit(&prison->cell_pool); in dm_bio_prison_destroy_v2() [all …]
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/linux/Documentation/devicetree/bindings/net/ |
H A D | broadcom-bcm87xx.txt | 5 "ethernet-phy-ieee802.3-c45" 9 - broadcom,c45-reg-init : one of more sets of 4 cells. The first cell 11 address within the MMD, the third cell contains a mask to be ANDed 12 with the existing register value, and the fourth cell is ORed with 13 he result to yield the new register value. If the third cell has a 18 ethernet-phy@5 { 20 compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45"; 21 interrupt-parent = <&gpio>; 28 broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>;
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/linux/Documentation/devicetree/bindings/clock/ |
H A D | stericsson,u8500-clks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ST-Ericsson DB8500 (U8500) clocks 10 - Ulf Hansson <ulf.hansson@linaro.org> 11 - Linus Walleij <linus.walleij@linaro.org> 14 DB8500 digital baseband system-on-chip and its siblings such as 16 itself, not off-chip clocks. There are four different on-chip 17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | realtek,usb2phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Stanley Chang <stanley_chang@realtek.com> 16 support multiple XHCI controllers. One PHY device node maps to one XHCI 21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some 23 XHCI controller#0 -- usb2phy -- phy#0 24 |- usb3phy -- phy#0 25 XHCI controller#1 -- usb2phy -- phy#0 26 XHCI controller#2 -- usb2phy -- phy#0 [all …]
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/linux/Documentation/devicetree/bindings/firmware/ |
H A D | cznic,turris-omnia-mcu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marek Behún <kabel@kernel.org> 18 const: cznic,turris-omnia-mcu 27 interrupt-controller: true 29 '#interrupt-cells': 32 The first cell specifies the interrupt number (0 to 63), the second cell 33 specifies interrupt type (which can be one of IRQ_TYPE_EDGE_RISING, [all …]
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