1d524dac9SGrant LikelyMPC5200 Device Tree Bindings 2d524dac9SGrant Likely---------------------------- 3d524dac9SGrant Likely 4d524dac9SGrant Likely(c) 2006-2009 Secret Lab Technologies Ltd 5d524dac9SGrant LikelyGrant Likely <grant.likely@secretlab.ca> 6d524dac9SGrant Likely 7d524dac9SGrant LikelyNaming conventions 8d524dac9SGrant Likely------------------ 9d524dac9SGrant LikelyFor mpc5200 on-chip devices, the format for each compatible value is 10d524dac9SGrant Likely<chip>-<device>[-<mode>]. The OS should be able to match a device driver 11d524dac9SGrant Likelyto the device based solely on the compatible value. If two drivers 12d524dac9SGrant Likelymatch on the compatible list; the 'most compatible' driver should be 13d524dac9SGrant Likelyselected. 14d524dac9SGrant Likely 15d524dac9SGrant LikelyThe split between the MPC5200 and the MPC5200B leaves a bit of a 16d524dac9SGrant Likelyconundrum. How should the compatible property be set up to provide 17d524dac9SGrant Likelymaximum compatibility information; but still accurately describe the 18d524dac9SGrant Likelychip? For the MPC5200; the answer is easy. Most of the SoC devices 19d524dac9SGrant Likelyoriginally appeared on the MPC5200. Since they didn't exist anywhere 20d524dac9SGrant Likelyelse; the 5200 compatible properties will contain only one item; 21d524dac9SGrant Likely"fsl,mpc5200-<device>". 22d524dac9SGrant Likely 23d524dac9SGrant LikelyThe 5200B is almost the same as the 5200, but not quite. It fixes 24d524dac9SGrant Likelysilicon bugs and it adds a small number of enhancements. Most of the 25d524dac9SGrant Likelydevices either provide exactly the same interface as on the 5200. A few 26d524dac9SGrant Likelydevices have extra functions but still have a backwards compatible mode. 27d524dac9SGrant LikelyTo express this information as completely as possible, 5200B device trees 28d524dac9SGrant Likelyshould have two items in the compatible list: 29d524dac9SGrant Likely compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>"; 30d524dac9SGrant Likely 31d524dac9SGrant LikelyIt is *strongly* recommended that 5200B device trees follow this convention 32d524dac9SGrant Likely(instead of only listing the base mpc5200 item). 33d524dac9SGrant Likely 34d524dac9SGrant Likelyie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec"; 35d524dac9SGrant Likely ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec"; 36d524dac9SGrant Likely 37d524dac9SGrant LikelyModal devices, like PSCs, also append the configured function to the 38d524dac9SGrant Likelyend of the compatible field. ie. A PSC in i2s mode would specify 39d524dac9SGrant Likely"fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to 40d524dac9SGrant Likelyavoid naming conflicts with non-psc devices providing the same 41d524dac9SGrant Likelyfunction. For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe 42d524dac9SGrant Likelythe mpc5200 simple spi device and a PSC spi mode respectively. 43d524dac9SGrant Likely 44d524dac9SGrant LikelyAt the time of writing, exact chip may be either 'fsl,mpc5200' or 45d524dac9SGrant Likely'fsl,mpc5200b'. 46d524dac9SGrant Likely 47d524dac9SGrant LikelyThe soc node 48d524dac9SGrant Likely------------ 49d524dac9SGrant LikelyThis node describes the on chip SOC peripherals. Every mpc5200 based 50d524dac9SGrant Likelyboard will have this node, and as such there is a common naming 51d524dac9SGrant Likelyconvention for SOC devices. 52d524dac9SGrant Likely 53d524dac9SGrant LikelyRequired properties: 54d524dac9SGrant Likelyname description 55d524dac9SGrant Likely---- ----------- 56d524dac9SGrant Likelyranges Memory range of the internal memory mapped registers. 57d524dac9SGrant Likely Should be <0 [baseaddr] 0xc000> 58d524dac9SGrant Likelyreg Should be <[baseaddr] 0x100> 59d524dac9SGrant Likelycompatible mpc5200: "fsl,mpc5200-immr" 60d524dac9SGrant Likely mpc5200b: "fsl,mpc5200b-immr" 61d524dac9SGrant Likelysystem-frequency 'fsystem' frequency in Hz; XLB, IPB, USB and PCI 62d524dac9SGrant Likely clocks are derived from the fsystem clock. 63d524dac9SGrant Likelybus-frequency IPB bus frequency in Hz. Clock rate 64d524dac9SGrant Likely used by most of the soc devices. 65d524dac9SGrant Likely 66d524dac9SGrant Likelysoc child nodes 67d524dac9SGrant Likely--------------- 68d524dac9SGrant LikelyAny on chip SOC devices available to Linux must appear as soc5200 child nodes. 69d524dac9SGrant Likely 70d524dac9SGrant LikelyNote: The tables below show the value for the mpc5200. A mpc5200b device 71d524dac9SGrant Likelytree should use the "fsl,mpc5200b-<device>","fsl,mpc5200-<device>" form. 72d524dac9SGrant Likely 73d524dac9SGrant LikelyRequired soc5200 child nodes: 74d524dac9SGrant Likelyname compatible Description 75d524dac9SGrant Likely---- ---------- ----------- 76d524dac9SGrant Likelycdm@<addr> fsl,mpc5200-cdm Clock Distribution 77d524dac9SGrant Likelyinterrupt-controller@<addr> fsl,mpc5200-pic need an interrupt 78d524dac9SGrant Likely controller to boot 79d524dac9SGrant Likelybestcomm@<addr> fsl,mpc5200-bestcomm Bestcomm DMA controller 80d524dac9SGrant Likely 81d524dac9SGrant LikelyRecommended soc5200 child nodes; populate as needed for your board 82d524dac9SGrant Likelyname compatible Description 83d524dac9SGrant Likely---- ---------- ----------- 84d524dac9SGrant Likelytimer@<addr> fsl,mpc5200-gpt General purpose timers 85d524dac9SGrant Likelygpio@<addr> fsl,mpc5200-gpio MPC5200 simple gpio controller 86d524dac9SGrant Likelygpio@<addr> fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio controller 87d524dac9SGrant Likelyrtc@<addr> fsl,mpc5200-rtc Real time clock 88d524dac9SGrant Likelymscan@<addr> fsl,mpc5200-mscan CAN bus controller 89d524dac9SGrant Likelypci@<addr> fsl,mpc5200-pci PCI bridge 90d524dac9SGrant Likelyserial@<addr> fsl,mpc5200-psc-uart PSC in serial mode 91d524dac9SGrant Likelyi2s@<addr> fsl,mpc5200-psc-i2s PSC in i2s mode 92d524dac9SGrant Likelyac97@<addr> fsl,mpc5200-psc-ac97 PSC in ac97 mode 93d524dac9SGrant Likelyspi@<addr> fsl,mpc5200-psc-spi PSC in spi mode 94d524dac9SGrant Likelyirda@<addr> fsl,mpc5200-psc-irda PSC in IrDA mode 95d524dac9SGrant Likelyspi@<addr> fsl,mpc5200-spi MPC5200 spi device 96d524dac9SGrant Likelyethernet@<addr> fsl,mpc5200-fec MPC5200 ethernet device 97d524dac9SGrant Likelyata@<addr> fsl,mpc5200-ata IDE ATA interface 98d524dac9SGrant Likelyi2c@<addr> fsl,mpc5200-i2c I2C controller 99d524dac9SGrant Likelyusb@<addr> fsl,mpc5200-ohci,ohci-be USB controller 100d524dac9SGrant Likelyxlb@<addr> fsl,mpc5200-xlb XLB arbitrator 101d524dac9SGrant Likely 102d524dac9SGrant Likelyfsl,mpc5200-gpt nodes 103d524dac9SGrant Likely--------------------- 104d524dac9SGrant LikelyOn the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board 105d524dac9SGrant Likelydesign supports the internal wdt, then the device node for GPT0 should 106d524dac9SGrant Likelyinclude the empty property 'fsl,has-wdt'. Note that this does not activate 107d524dac9SGrant Likelythe watchdog. The timer will function as a GPT if the timer api is used, and 108d524dac9SGrant Likelyit will function as watchdog if the watchdog device is used. The watchdog 109d524dac9SGrant Likelymode has priority over the gpt mode, i.e. if the watchdog is activated, any 110d524dac9SGrant Likelygpt api call to this timer will fail with -EBUSY. 111d524dac9SGrant Likely 112d524dac9SGrant LikelyIf you add the property 113d524dac9SGrant Likely fsl,wdt-on-boot = <n>; 114d524dac9SGrant LikelyGPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it. 115d524dac9SGrant LikelyIf n>0, the watchdog is started with a timeout of n seconds. If n=0, the 116d524dac9SGrant Likelyconfiguration of the watchdog is not touched. This is useful in two cases: 117d524dac9SGrant Likely- just mark GPT0 as watchdog, blocking gpt accesses, and configure it later; 118d524dac9SGrant Likely- do not touch a configuration assigned by the boot loader which supervises 119d524dac9SGrant Likely the boot process itself. 120d524dac9SGrant Likely 121d524dac9SGrant LikelyThe watchdog will respect the CONFIG_WATCHDOG_NOWAYOUT option. 122d524dac9SGrant Likely 123d524dac9SGrant LikelyAn mpc5200-gpt can be used as a single line GPIO controller. To do so, 124d524dac9SGrant Likelyadd the following properties to the gpt node: 125d524dac9SGrant Likely gpio-controller; 126d524dac9SGrant Likely #gpio-cells = <2>; 127d524dac9SGrant LikelyWhen referencing the GPIO line from another node, the first cell must always 128d524dac9SGrant Likelybe zero and the second cell represents the gpio flags and described in the 129d524dac9SGrant Likelygpio device tree binding. 130d524dac9SGrant Likely 131d524dac9SGrant LikelyAn mpc5200-gpt can be used as a single line edge sensitive interrupt 132d524dac9SGrant Likelycontroller. To do so, add the following properties to the gpt node: 133d524dac9SGrant Likely interrupt-controller; 134d524dac9SGrant Likely #interrupt-cells = <1>; 135d524dac9SGrant LikelyWhen referencing the IRQ line from another node, the cell represents the 136d524dac9SGrant Likelysense mode; 1 for edge rising, 2 for edge falling. 137d524dac9SGrant Likely 138d524dac9SGrant Likelyfsl,mpc5200-psc nodes 139d524dac9SGrant Likely--------------------- 140d524dac9SGrant LikelyThe PSCs should include a cell-index which is the index of the PSC in 141d524dac9SGrant Likelyhardware. cell-index is used to determine which shared SoC registers to 142d524dac9SGrant Likelyuse when setting up PSC clocking. cell-index number starts at '0'. ie: 143d524dac9SGrant Likely PSC1 has 'cell-index = <0>' 144d524dac9SGrant Likely PSC4 has 'cell-index = <3>' 145d524dac9SGrant Likely 146d524dac9SGrant LikelyPSC in i2s mode: The mpc5200 and mpc5200b PSCs are not compatible when in 147d524dac9SGrant Likelyi2s mode. An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the 148d524dac9SGrant Likelycompatible field. 149d524dac9SGrant Likely 150d524dac9SGrant Likely 151d524dac9SGrant Likelyfsl,mpc5200-gpio and fsl,mpc5200-gpio-wkup nodes 152d524dac9SGrant Likely------------------------------------------------ 153d524dac9SGrant LikelyEach GPIO controller node should have the empty property gpio-controller and 154d524dac9SGrant Likely#gpio-cells set to 2. First cell is the GPIO number which is interpreted 155d524dac9SGrant Likelyaccording to the bit numbers in the GPIO control registers. The second cell 156d524dac9SGrant Likelyis for flags which is currently unused. 157d524dac9SGrant Likely 158d524dac9SGrant Likelyfsl,mpc5200-fec nodes 159d524dac9SGrant Likely--------------------- 160d524dac9SGrant LikelyThe FEC node can specify one of the following properties to configure 161d524dac9SGrant Likelythe MII link: 162d524dac9SGrant Likely- fsl,7-wire-mode - An empty property that specifies the link uses 7-wire 163d524dac9SGrant Likely mode instead of MII 164d524dac9SGrant Likely- current-speed - Specifies that the MII should be configured for a fixed 165d524dac9SGrant Likely speed. This property should contain two cells. The 166d524dac9SGrant Likely first cell specifies the speed in Mbps and the second 167d524dac9SGrant Likely should be '0' for half duplex and '1' for full duplex 168d524dac9SGrant Likely- phy-handle - Contains a phandle to an Ethernet PHY. 169d524dac9SGrant Likely 170d524dac9SGrant LikelyInterrupt controller (fsl,mpc5200-pic) node 171d524dac9SGrant Likely------------------------------------------- 172d524dac9SGrant LikelyThe mpc5200 pic binding splits hardware IRQ numbers into two levels. The 173d524dac9SGrant Likelysplit reflects the layout of the PIC hardware itself, which groups 174d524dac9SGrant Likelyinterrupts into one of three groups; CRIT, MAIN or PERP. Also, the 175*be55492eSRandy DunlapBestcomm dma engine has its own set of interrupt sources which are 176d524dac9SGrant Likelycascaded off of peripheral interrupt 0, which the driver interprets as a 177d524dac9SGrant Likelyfourth group, SDMA. 178d524dac9SGrant Likely 179d524dac9SGrant LikelyThe interrupts property for device nodes using the mpc5200 pic consists 180d524dac9SGrant Likelyof three cells; <L1 L2 level> 181d524dac9SGrant Likely 182d524dac9SGrant Likely L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3] 183d524dac9SGrant Likely L2 := interrupt number; directly mapped from the value in the 184d524dac9SGrant Likely "ICTL PerStat, MainStat, CritStat Encoded Register" 185d524dac9SGrant Likely level := [LEVEL_HIGH=0, EDGE_RISING=1, EDGE_FALLING=2, LEVEL_LOW=3] 186d524dac9SGrant Likely 187d524dac9SGrant LikelyFor external IRQs, use the following interrupt property values (how to 188d524dac9SGrant Likelyspecify external interrupts is a frequently asked question): 189d524dac9SGrant LikelyExternal interrupts: 190d524dac9SGrant Likely external irq0: interrupts = <0 0 n>; 191d524dac9SGrant Likely external irq1: interrupts = <1 1 n>; 192d524dac9SGrant Likely external irq2: interrupts = <1 2 n>; 193d524dac9SGrant Likely external irq3: interrupts = <1 3 n>; 194d524dac9SGrant Likely'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low) 195d524dac9SGrant Likely 196d524dac9SGrant Likelyfsl,mpc5200-mscan nodes 197d524dac9SGrant Likely----------------------- 198cea47072SMarc Kleine-BuddeSee file Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt 199