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/linux/drivers/interconnect/qcom/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Qualcomm Network-on-Chip interconnect drivers"
4 depends on ARCH_QCOM
6 Support for Qualcomm's Network-on-Chip interconnect hardware.
13 depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
17 This is a driver for the Qualcomm Network-on-Chip on Eliza-based
22 depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
26 This is a driver for the Qualcomm Network-on-Chip on glymur-based
31 depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
35 This is a driver for the Qualcomm Network-on-Chip on kaanapali-based
[all …]
/linux/drivers/media/usb/gspca/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 depends on VIDEO_DEV
5 depends on INPUT || INPUT=n
9 on the GSPCA framework.
11 See <file:Documentation/admin-guide/media/gspca-cardlist.rst> for more info.
23 depends on VIDEO_DEV && USB_GSPCA
32 depends on VIDEO_DEV && USB_GSPCA
34 Say Y here if you want support for cameras based on the Conexant chip.
41 depends on VIDEO_DEV && USB_GSPCA
43 Say Y here if you want support for USB cameras based on the cpia
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A Ddatasource.json10 …er this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are i…
40 …"All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happ…
45 …All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happ…
50 … "All successful D-side store dispatches for this thread that were L2 hits. Since the event happen…
55 … missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 t…
120 …or's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the lo…
125 …or's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the lo…
130 …ta cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the loca…
135 …ta cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the loca…
230 …line that was not in the M (exclusive) state from another core's L2 on the same chip in the same r…
[all …]
/linux/drivers/mtd/nand/raw/
H A Dnand_micron.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
15 * corrected by on-die ECC and should be rewritten.
20 * On chips with 8-bit ECC and additional bit can be used to distinguish
24 * ----- ----- ----- -----------
27 * 0 1 0 4 - 6 errors corrected, recommend rewrite
29 * 1 0 0 1 - 3 errors corrected
31 * 1 1 0 7 - 8 errors corrected, recommend rewrite
69 static int micron_nand_setup_read_retry(struct nand_chip *chip, int retry_mode) in micron_nand_setup_read_retry() argument
73 return nand_set_features(chip, ONFI_FEATURE_ADDR_READ_RETRY, feature); in micron_nand_setup_read_retry()
[all …]
H A Dnand_hynix.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
20 * struct hynix_read_retry - read-retry data
21 * @nregs: number of register to set when applying a new read-retry mode
22 * @regs: register offsets (NAND chip dependent)
33 * struct hynix_nand - private Hynix NAND struct
34 * @read_retry: read-retry information
41 * struct hynix_read_retry_otp - structure describing how the read-retry OTP
47 * @page: the address to pass to the READ_PAGE command. Depends on the NAND
48 * chip
[all …]
/linux/kernel/irq/
H A Dchip.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 * This file contains the core interrupt handling code, for irq-chip based
8 * Documentation/core-api/genericirq.rst
31 * Chained handlers should never call action on their IRQ. This default
39 * irq_set_chip - set the irq chip for an irq
41 * @chip: pointer to irq chip description structure
43 int irq_set_chip(unsigned int irq, const struct irq_chip *chip) in irq_set_chip() argument
45 int ret = -EINVAL; in irq_set_chip()
[all …]
/linux/sound/pci/echoaudio/
H A Decho3g_dsp.c1 // SPDX-License-Identifier: GPL-2.0-only
4 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
11 Translation from C++ and adaptation for use in ALSA-Driver
16 static int load_asic(struct echoaudio *chip);
17 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode);
18 static int set_digital_mode(struct echoaudio *chip, u8 mode);
19 static int check_asic_status(struct echoaudio *chip);
20 static int set_sample_rate(struct echoaudio *chip, u32 rate);
21 static int set_input_clock(struct echoaudio *chip, u16 clock);
22 static int set_professional_spdif(struct echoaudio *chip, char prof);
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/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
14 …) and the request was made by the Level-1 Data cache. This is a replacement for what was provided …
17 "Unit": "CPU-M-CF",
21 …-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th…
24 "Unit": "CPU-M-CF",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A Dfrontend.json47 "BriefDescription": "Number of I-ERAT reloads",
59 "BriefDescription": "IERAT Miss (Not implemented as DI on POWER6)",
71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru…
72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
89 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
90 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
95 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
96 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
[all …]
H A Dother.json11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data …
24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
36 … got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump w…
41 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a…
42 …urced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump w…
65 …ump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the origi…
66 …(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group…
71 …"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group…
[all …]
H A Dcache.json5 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
6 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
11 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
12 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
53 …ata cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a …
54 …ata cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to ei…
71 "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z17/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
14 …) and the request was made by the Level-1 Data cache. This is a replacement for what was provided …
17 "Unit": "CPU-M-CF",
21 …-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th…
24 "Unit": "CPU-M-CF",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
[all …]
/linux/sound/soc/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 tristate "ASoC support for Mediatek MT2701 chip"
10 depends on ARCH_MEDIATEK
20 depends on SND_SOC_MT2701 && I2C
31 depends on SND_SOC_MT2701 && I2C
40 tristate "ASoC support for Mediatek MT6797 chip"
41 depends on ARCH_MEDIATE
[all...]
/linux/drivers/base/regmap/
H A Dregmap-irq.c1 // SPDX-License-Identifier: GPL-2.0
28 const struct regmap_irq_chip *chip; member
59 return &data->chip->irqs[irq]; in irq_to_regmap_irq()
64 struct regmap *map = data->map; in regmap_irq_can_bulk_read_status()
67 * While possible that a user-defined ->get_irq_reg() callback might in regmap_irq_can_bulk_read_status()
71 return data->irq_reg_stride == 1 && map->reg_stride == 1 && in regmap_irq_can_bulk_read_status()
72 data->get_irq_reg == regmap_irq_get_irq_reg_linear && in regmap_irq_can_bulk_read_status()
73 !map->use_single_read; in regmap_irq_can_bulk_read_status()
80 mutex_lock(&d->lock); in regmap_irq_lock()
86 struct regmap *map = d->map; in regmap_irq_sync_unlock()
[all …]
/linux/drivers/thermal/qcom/
H A Dqcom-spmi-temp-alarm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved.
66 /* Over-temperature trip point values in mC */
91 * TEMP_DAC_STG* = 0 --> 80 C
99 (((temp) - TEMP_DAC_MIN) * TEMP_DAC_SCALE_NUM / TEMP_DAC_SCALE_DEN)
128 int (*sync_thresholds)(struct qpnp_tm_chip *chip);
129 int (*get_temp_stage)(struct qpnp_tm_chip *chip);
130 int (*configure_trip_temps)(struct qpnp_tm_chip *chip);
143 /* protects .thresh, .stage and chip registers */
155 static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data) in qpnp_tm_read() argument
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dtranslation.json15 …data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a dema…
20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
25 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …
35 …o the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
60 …the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
75 …to the TLB either shared or modified data from another core's L2/L3 on the same chip due to a inst…
80 …tion cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an ins…
95 …ta cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a dema…
100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…
130 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
[all …]
H A Dmarked.json20 …was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data…
25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
30 …"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or mem…
60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due…
70 …loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a mark…
95 …aded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a mark…
100 …loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data…
120 …tion": "The processor's Instruction cache was reloaded from another chip's memory on the same Node…
130 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a…
145 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a…
[all …]
/linux/drivers/leds/
H A Dleds-an30259a.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Driver for Panasonic AN30259A 3-channel LED driver
24 #define AN30259A_LED_EN(x) BIT((x) - 1)
25 #define AN30259A_LED_SLOPE(x) BIT(((x) - 1) + 4)
27 #define AN30259A_REG_LEDCC(x) (0x03 + ((x) - 1))
30 #define AN30259A_REG_SLOPE(x) (0x06 + ((x) - 1))
34 #define AN30259A_REG_LEDCNT1(x) (0x09 + (4 * ((x) - 1)))
38 #define AN30259A_REG_LEDCNT2(x) (0x0A + (4 * ((x) - 1)))
43 #define AN30259A_REG_LEDCNT3(x) (0x0B + (4 * ((x) - 1)))
47 #define AN30259A_REG_LEDCNT4(x) (0x0C + (4 * ((x) - 1)))
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dsmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include "chip.h"
13 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
16 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
20 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
26 * addresses, allowing two to coexist on the same SMI interface.
29 static int mv88e6xxx_smi_direct_read(struct mv88e6xxx_chip *chip, in mv88e6xxx_smi_direct_read() argument
34 ret = mdiobus_read_nested(chip->bus, dev, reg); in mv88e6xxx_smi_direct_read()
43 static int mv88e6xxx_smi_direct_write(struct mv88e6xxx_chip *chip, in mv88e6xxx_smi_direct_write() argument
48 ret = mdiobus_write_nested(chip->bus, dev, reg, data); in mv88e6xxx_smi_direct_write()
[all …]
/linux/drivers/gpio/
H A Dgpio-zynqmp-modepin.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the ps-mode pin configuration.
16 #include <linux/firmware/xlnx-zynqmp.h>
18 /* 4-bit boot mode pins */
22 * modepin_gpio_get_value - Get the state of the specified pin of GPIO device
23 * @chip: gpio_chip instance to be worked on
28 * Return: 0 if the pin is low, 1 if pin is high, -EINVAL wrong pin configured
31 static int modepin_gpio_get_value(struct gpio_chip *chip, unsigned int pin) in modepin_gpio_get_value() argument
50 * modepin_gpio_set_value - Modify the state of the pin with specified value
51 * @chip: gpio_chip instance to be worked on
[all …]
H A Dgpio-pca953x.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #include <linux/pinctrl/pinconf-generic.h>
144 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
167 * On Intel Galileo Gen 2 board the IRQ pin of one of
170 * relative. Since first controller (gpio-sch.c) and
171 * second (gpio-dwapb.c) are at the fixed bases, we may
193 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) argument
246 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off);
247 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg,
251 static int pca953x_bank_shift(struct pca953x_chip *chip) in pca953x_bank_shift() argument
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-dbg-g-chip-info.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_DBG_G_CHIP_INFO - Identify the chips on a TV card
40 query the driver about the chips present on the TV card. Regular
41 applications must not use it. When you found a chip specific bug, please
42 contact the linux-media mailing list
52 :ref:`VIDIOC_DBG_G_CHIP_INFO` with a pointer to this structure. On success
53 the driver stores information about the selected chip in the ``name``
57 selects the nth bridge 'chip' on the TV card. You can enumerate all
60 zero always selects the bridge chip itself, e. g. the chip connected to
61 the PCI or USB bus. Non-zero numbers identify specific parts of the
[all …]
/linux/drivers/rtc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 depends on !S390
26 bool "Set system time from RTC on startup and resume"
35 depends on RTC_HCTOSYS
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
54 bool "Set the RTC time based on NTP synchronization"
63 depends on RTC_SYSTOHC
80 depends on KUNIT
93 backed) storage present on RTCs.
[all …]
/linux/drivers/pwm/
H A Dpwm-adp5585.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2024 Ideas on Board Oy
9 * - The .apply() operation executes atomically, but may not wait for the
11 * - Disabling the PWM drives the output pin to a low level immediately.
12 * - The hardware can only generate normal polarity output.
48 static int pwm_adp5585_request(struct pwm_chip *chip, struct pwm_device *pwm) in pwm_adp5585_request() argument
50 struct adp5585_pwm *adp5585_pwm = pwmchip_get_drvdata(chip); in pwm_adp5585_request()
53 return regmap_update_bits(adp5585_pwm->regmap, adp5585_pwm->ext_cfg, in pwm_adp5585_request()
58 static void pwm_adp5585_free(struct pwm_chip *chip, struct pwm_device *pwm) in pwm_adp5585_free() argument
60 struct adp5585_pwm *adp5585_pwm = pwmchip_get_drvdata(chip); in pwm_adp5585_free()
[all …]
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2011-2012 Avionic Design GmbH
24 #include <dt-bindings/pwm/pwm.h>
38 static void pwmchip_lock(struct pwm_chip *chip) in pwmchip_lock() argument
40 if (chip->atomic) in pwmchip_lock()
41 spin_lock(&chip->atomic_lock); in pwmchip_lock()
43 mutex_lock(&chip->nonatomic_lock); in pwmchip_lock()
46 static void pwmchip_unlock(struct pwm_chip *chip) in pwmchip_unlock() argument
48 if (chip->atomic) in pwmchip_unlock()
49 spin_unlock(&chip->atomic_lock); in pwmchip_unlock()
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