Lines Matching +full:on +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0
25 const struct regmap_irq_chip *chip; member
55 return &data->chip->irqs[irq]; in irq_to_regmap_irq()
60 struct regmap *map = data->map; in regmap_irq_can_bulk_read_status()
63 * While possible that a user-defined ->get_irq_reg() callback might in regmap_irq_can_bulk_read_status()
67 return data->irq_reg_stride == 1 && map->reg_stride == 1 && in regmap_irq_can_bulk_read_status()
68 data->get_irq_reg == regmap_irq_get_irq_reg_linear && in regmap_irq_can_bulk_read_status()
69 !map->use_single_read; in regmap_irq_can_bulk_read_status()
76 mutex_lock(&d->lock); in regmap_irq_lock()
82 struct regmap *map = d->map; in regmap_irq_sync_unlock()
87 if (d->chip->runtime_pm) { in regmap_irq_sync_unlock()
88 ret = pm_runtime_get_sync(map->dev); in regmap_irq_sync_unlock()
90 dev_err(map->dev, "IRQ sync failed to resume: %d\n", in regmap_irq_sync_unlock()
94 if (d->clear_status) { in regmap_irq_sync_unlock()
95 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
96 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_irq_sync_unlock()
100 dev_err(d->map->dev, in regmap_irq_sync_unlock()
104 d->clear_status = false; in regmap_irq_sync_unlock()
109 * hardware. We rely on the use of the regmap core cache to in regmap_irq_sync_unlock()
112 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
113 if (d->chip->handle_mask_sync) in regmap_irq_sync_unlock()
114 d->chip->handle_mask_sync(i, d->mask_buf_def[i], in regmap_irq_sync_unlock()
115 d->mask_buf[i], in regmap_irq_sync_unlock()
116 d->chip->irq_drv_data); in regmap_irq_sync_unlock()
118 if (d->chip->mask_base && !d->chip->handle_mask_sync) { in regmap_irq_sync_unlock()
119 reg = d->get_irq_reg(d, d->chip->mask_base, i); in regmap_irq_sync_unlock()
120 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
121 d->mask_buf_def[i], in regmap_irq_sync_unlock()
122 d->mask_buf[i]); in regmap_irq_sync_unlock()
124 dev_err(d->map->dev, "Failed to sync masks in %x\n", reg); in regmap_irq_sync_unlock()
127 if (d->chip->unmask_base && !d->chip->handle_mask_sync) { in regmap_irq_sync_unlock()
128 reg = d->get_irq_reg(d, d->chip->unmask_base, i); in regmap_irq_sync_unlock()
129 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
130 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_irq_sync_unlock()
132 dev_err(d->map->dev, "Failed to sync masks in %x\n", in regmap_irq_sync_unlock()
136 reg = d->get_irq_reg(d, d->chip->wake_base, i); in regmap_irq_sync_unlock()
137 if (d->wake_buf) { in regmap_irq_sync_unlock()
138 if (d->chip->wake_invert) in regmap_irq_sync_unlock()
139 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
140 d->mask_buf_def[i], in regmap_irq_sync_unlock()
141 ~d->wake_buf[i]); in regmap_irq_sync_unlock()
143 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
144 d->mask_buf_def[i], in regmap_irq_sync_unlock()
145 d->wake_buf[i]); in regmap_irq_sync_unlock()
147 dev_err(d->map->dev, in regmap_irq_sync_unlock()
152 if (!d->chip->init_ack_masked) in regmap_irq_sync_unlock()
159 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { in regmap_irq_sync_unlock()
160 reg = d->get_irq_reg(d, d->chip->ack_base, i); in regmap_irq_sync_unlock()
163 if (d->chip->ack_invert) in regmap_irq_sync_unlock()
164 ret = regmap_write(map, reg, ~d->mask_buf[i]); in regmap_irq_sync_unlock()
166 ret = regmap_write(map, reg, d->mask_buf[i]); in regmap_irq_sync_unlock()
167 if (d->chip->clear_ack) { in regmap_irq_sync_unlock()
168 if (d->chip->ack_invert && !ret) in regmap_irq_sync_unlock()
174 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_sync_unlock()
179 for (i = 0; i < d->chip->num_config_bases; i++) { in regmap_irq_sync_unlock()
180 for (j = 0; j < d->chip->num_config_regs; j++) { in regmap_irq_sync_unlock()
181 reg = d->get_irq_reg(d, d->chip->config_base[i], j); in regmap_irq_sync_unlock()
182 ret = regmap_write(map, reg, d->config_buf[i][j]); in regmap_irq_sync_unlock()
184 dev_err(d->map->dev, in regmap_irq_sync_unlock()
190 if (d->chip->runtime_pm) in regmap_irq_sync_unlock()
191 pm_runtime_put(map->dev); in regmap_irq_sync_unlock()
194 if (d->wake_count < 0) in regmap_irq_sync_unlock()
195 for (i = d->wake_count; i < 0; i++) in regmap_irq_sync_unlock()
196 irq_set_irq_wake(d->irq, 0); in regmap_irq_sync_unlock()
197 else if (d->wake_count > 0) in regmap_irq_sync_unlock()
198 for (i = 0; i < d->wake_count; i++) in regmap_irq_sync_unlock()
199 irq_set_irq_wake(d->irq, 1); in regmap_irq_sync_unlock()
201 d->wake_count = 0; in regmap_irq_sync_unlock()
203 mutex_unlock(&d->lock); in regmap_irq_sync_unlock()
209 struct regmap *map = d->map; in regmap_irq_enable()
210 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_enable()
211 unsigned int reg = irq_data->reg_offset / map->reg_stride; in regmap_irq_enable()
224 if (d->chip->type_in_mask && irq_data->type.types_supported) in regmap_irq_enable()
225 mask = d->type_buf[reg] & irq_data->mask; in regmap_irq_enable()
227 mask = irq_data->mask; in regmap_irq_enable()
229 if (d->chip->clear_on_unmask) in regmap_irq_enable()
230 d->clear_status = true; in regmap_irq_enable()
232 d->mask_buf[reg] &= ~mask; in regmap_irq_enable()
238 struct regmap *map = d->map; in regmap_irq_disable()
239 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_disable()
241 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; in regmap_irq_disable()
247 struct regmap *map = d->map; in regmap_irq_set_type()
248 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_type()
250 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type()
252 if ((t->types_supported & type) != type) in regmap_irq_set_type()
255 reg = t->type_reg_offset / map->reg_stride; in regmap_irq_set_type()
257 if (d->chip->type_in_mask) { in regmap_irq_set_type()
258 ret = regmap_irq_set_type_config_simple(&d->type_buf, type, in regmap_irq_set_type()
259 irq_data, reg, d->chip->irq_drv_data); in regmap_irq_set_type()
264 if (d->chip->set_type_config) { in regmap_irq_set_type()
265 ret = d->chip->set_type_config(d->config_buf, type, irq_data, in regmap_irq_set_type()
266 reg, d->chip->irq_drv_data); in regmap_irq_set_type()
274 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on) in regmap_irq_set_wake() argument
277 struct regmap *map = d->map; in regmap_irq_set_wake()
278 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_wake()
280 if (on) { in regmap_irq_set_wake()
281 if (d->wake_buf) in regmap_irq_set_wake()
282 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
283 &= ~irq_data->mask; in regmap_irq_set_wake()
284 d->wake_count++; in regmap_irq_set_wake()
286 if (d->wake_buf) in regmap_irq_set_wake()
287 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
288 |= irq_data->mask; in regmap_irq_set_wake()
289 d->wake_count--; in regmap_irq_set_wake()
307 const struct regmap_irq_chip *chip = data->chip; in read_sub_irq_data() local
309 struct regmap *map = data->map; in read_sub_irq_data()
313 if (!chip->sub_reg_offsets) { in read_sub_irq_data()
314 reg = data->get_irq_reg(data, chip->status_base, b); in read_sub_irq_data()
315 ret = regmap_read(map, reg, &data->status_buf[b]); in read_sub_irq_data()
318 * Note we can't use ->get_irq_reg() here because the offsets in read_sub_irq_data()
321 subreg = &chip->sub_reg_offsets[b]; in read_sub_irq_data()
322 for (i = 0; i < subreg->num_regs; i++) { in read_sub_irq_data()
323 unsigned int offset = subreg->offset[i]; in read_sub_irq_data()
324 unsigned int index = offset / map->reg_stride; in read_sub_irq_data()
326 ret = regmap_read(map, chip->status_base + offset, in read_sub_irq_data()
327 &data->status_buf[index]); in read_sub_irq_data()
338 const struct regmap_irq_chip *chip = data->chip; in regmap_irq_thread() local
339 struct regmap *map = data->map; in regmap_irq_thread()
344 if (chip->handle_pre_irq) in regmap_irq_thread()
345 chip->handle_pre_irq(chip->irq_drv_data); in regmap_irq_thread()
347 if (chip->runtime_pm) { in regmap_irq_thread()
348 ret = pm_runtime_get_sync(map->dev); in regmap_irq_thread()
350 dev_err(map->dev, "IRQ thread failed to resume: %d\n", in regmap_irq_thread()
357 * Read only registers with active IRQs if the chip has 'main status in regmap_irq_thread()
362 if (chip->no_status) { in regmap_irq_thread()
364 memset32(data->status_buf, GENMASK(31, 0), chip->num_regs); in regmap_irq_thread()
365 } else if (chip->num_main_regs) { in regmap_irq_thread()
368 max_main_bits = (chip->num_main_status_bits) ? in regmap_irq_thread()
369 chip->num_main_status_bits : chip->num_regs; in regmap_irq_thread()
371 memset32(data->status_buf, 0, chip->num_regs); in regmap_irq_thread()
378 for (i = 0; i < chip->num_main_regs; i++) { in regmap_irq_thread()
379 reg = data->get_irq_reg(data, chip->main_status, i); in regmap_irq_thread()
380 ret = regmap_read(map, reg, &data->main_status_buf[i]); in regmap_irq_thread()
382 dev_err(map->dev, in regmap_irq_thread()
390 for (i = 0; i < chip->num_main_regs; i++) { in regmap_irq_thread()
392 const unsigned long mreg = data->main_status_buf[i]; in regmap_irq_thread()
394 for_each_set_bit(b, &mreg, map->format.val_bytes * 8) { in regmap_irq_thread()
395 if (i * map->format.val_bytes * 8 + b > in regmap_irq_thread()
401 dev_err(map->dev, in regmap_irq_thread()
411 u8 *buf8 = data->status_reg_buf; in regmap_irq_thread()
412 u16 *buf16 = data->status_reg_buf; in regmap_irq_thread()
413 u32 *buf32 = data->status_reg_buf; in regmap_irq_thread()
415 BUG_ON(!data->status_reg_buf); in regmap_irq_thread()
417 ret = regmap_bulk_read(map, chip->status_base, in regmap_irq_thread()
418 data->status_reg_buf, in regmap_irq_thread()
419 chip->num_regs); in regmap_irq_thread()
421 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_irq_thread()
426 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
427 switch (map->format.val_bytes) { in regmap_irq_thread()
429 data->status_buf[i] = buf8[i]; in regmap_irq_thread()
432 data->status_buf[i] = buf16[i]; in regmap_irq_thread()
435 data->status_buf[i] = buf32[i]; in regmap_irq_thread()
444 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
445 unsigned int reg = data->get_irq_reg(data, in regmap_irq_thread()
446 data->chip->status_base, i); in regmap_irq_thread()
447 ret = regmap_read(map, reg, &data->status_buf[i]); in regmap_irq_thread()
450 dev_err(map->dev, in regmap_irq_thread()
458 if (chip->status_invert) in regmap_irq_thread()
459 for (i = 0; i < data->chip->num_regs; i++) in regmap_irq_thread()
460 data->status_buf[i] = ~data->status_buf[i]; in regmap_irq_thread()
469 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
470 data->status_buf[i] &= ~data->mask_buf[i]; in regmap_irq_thread()
472 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_irq_thread()
473 reg = data->get_irq_reg(data, data->chip->ack_base, i); in regmap_irq_thread()
475 if (chip->ack_invert) in regmap_irq_thread()
477 ~data->status_buf[i]); in regmap_irq_thread()
480 data->status_buf[i]); in regmap_irq_thread()
481 if (chip->clear_ack) { in regmap_irq_thread()
482 if (chip->ack_invert && !ret) in regmap_irq_thread()
488 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_thread()
493 for (i = 0; i < chip->num_irqs; i++) { in regmap_irq_thread()
494 if (data->status_buf[chip->irqs[i].reg_offset / in regmap_irq_thread()
495 map->reg_stride] & chip->irqs[i].mask) { in regmap_irq_thread()
496 handle_nested_irq(irq_find_mapping(data->domain, i)); in regmap_irq_thread()
502 if (chip->handle_post_irq) in regmap_irq_thread()
503 chip->handle_post_irq(chip->irq_drv_data); in regmap_irq_thread()
505 if (chip->runtime_pm) in regmap_irq_thread()
506 pm_runtime_put(map->dev); in regmap_irq_thread()
520 struct regmap_irq_chip_data *data = h->host_data; in regmap_irq_map()
524 irq_set_chip(virq, &data->irq_chip); in regmap_irq_map()
526 irq_set_parent(virq, data->irq); in regmap_irq_map()
538 * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback.
549 struct regmap *map = data->map; in regmap_irq_get_irq_reg_linear()
551 return base + index * map->reg_stride * data->irq_reg_stride; in regmap_irq_get_irq_reg_linear()
556 * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback.
564 * This is a &struct regmap_irq_chip->set_type_config callback suitable for
572 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type_config_simple()
574 if (t->type_reg_mask) in regmap_irq_set_type_config_simple()
575 buf[0][idx] &= ~t->type_reg_mask; in regmap_irq_set_type_config_simple()
577 buf[0][idx] &= ~(t->type_falling_val | in regmap_irq_set_type_config_simple()
578 t->type_rising_val | in regmap_irq_set_type_config_simple()
579 t->type_level_low_val | in regmap_irq_set_type_config_simple()
580 t->type_level_high_val); in regmap_irq_set_type_config_simple()
584 buf[0][idx] |= t->type_falling_val; in regmap_irq_set_type_config_simple()
588 buf[0][idx] |= t->type_rising_val; in regmap_irq_set_type_config_simple()
592 buf[0][idx] |= (t->type_falling_val | in regmap_irq_set_type_config_simple()
593 t->type_rising_val); in regmap_irq_set_type_config_simple()
597 buf[0][idx] |= t->type_level_high_val; in regmap_irq_set_type_config_simple()
601 buf[0][idx] |= t->type_level_low_val; in regmap_irq_set_type_config_simple()
605 return -EINVAL; in regmap_irq_set_type_config_simple()
613 const struct regmap_irq_chip *chip, in regmap_irq_create_domain() argument
618 .size = chip->num_irqs, in regmap_irq_create_domain()
619 .hwirq_max = chip->num_irqs, in regmap_irq_create_domain()
623 .name_suffix = chip->domain_suffix, in regmap_irq_create_domain()
626 d->domain = irq_domain_instantiate(&info); in regmap_irq_create_domain()
627 if (IS_ERR(d->domain)) { in regmap_irq_create_domain()
628 dev_err(d->map->dev, "Failed to create IRQ domain\n"); in regmap_irq_create_domain()
629 return PTR_ERR(d->domain); in regmap_irq_create_domain()
637 * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
644 * @chip: Configuration for the interrupt controller.
645 * @data: Runtime data structure for the controller, allocated on success.
647 * Returns 0 on success or an errno on failure.
649 * In order for this to be efficient the chip really should use a
650 * register cache. The chip driver is responsible for restoring the
656 const struct regmap_irq_chip *chip, in regmap_add_irq_chip_fwnode() argument
661 int ret = -ENOMEM; in regmap_add_irq_chip_fwnode()
664 if (chip->num_regs <= 0) in regmap_add_irq_chip_fwnode()
665 return -EINVAL; in regmap_add_irq_chip_fwnode()
667 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack)) in regmap_add_irq_chip_fwnode()
668 return -EINVAL; in regmap_add_irq_chip_fwnode()
670 if (chip->mask_base && chip->unmask_base && !chip->mask_unmask_non_inverted) in regmap_add_irq_chip_fwnode()
671 return -EINVAL; in regmap_add_irq_chip_fwnode()
673 for (i = 0; i < chip->num_irqs; i++) { in regmap_add_irq_chip_fwnode()
674 if (chip->irqs[i].reg_offset % map->reg_stride) in regmap_add_irq_chip_fwnode()
675 return -EINVAL; in regmap_add_irq_chip_fwnode()
676 if (chip->irqs[i].reg_offset / map->reg_stride >= in regmap_add_irq_chip_fwnode()
677 chip->num_regs) in regmap_add_irq_chip_fwnode()
678 return -EINVAL; in regmap_add_irq_chip_fwnode()
682 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); in regmap_add_irq_chip_fwnode()
684 dev_warn(map->dev, "Failed to allocate IRQs: %d\n", in regmap_add_irq_chip_fwnode()
692 return -ENOMEM; in regmap_add_irq_chip_fwnode()
694 if (chip->num_main_regs) { in regmap_add_irq_chip_fwnode()
695 d->main_status_buf = kcalloc(chip->num_main_regs, in regmap_add_irq_chip_fwnode()
696 sizeof(*d->main_status_buf), in regmap_add_irq_chip_fwnode()
699 if (!d->main_status_buf) in regmap_add_irq_chip_fwnode()
703 d->status_buf = kcalloc(chip->num_regs, sizeof(*d->status_buf), in regmap_add_irq_chip_fwnode()
705 if (!d->status_buf) in regmap_add_irq_chip_fwnode()
708 d->mask_buf = kcalloc(chip->num_regs, sizeof(*d->mask_buf), in regmap_add_irq_chip_fwnode()
710 if (!d->mask_buf) in regmap_add_irq_chip_fwnode()
713 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(*d->mask_buf_def), in regmap_add_irq_chip_fwnode()
715 if (!d->mask_buf_def) in regmap_add_irq_chip_fwnode()
718 if (chip->wake_base) { in regmap_add_irq_chip_fwnode()
719 d->wake_buf = kcalloc(chip->num_regs, sizeof(*d->wake_buf), in regmap_add_irq_chip_fwnode()
721 if (!d->wake_buf) in regmap_add_irq_chip_fwnode()
725 if (chip->type_in_mask) { in regmap_add_irq_chip_fwnode()
726 d->type_buf_def = kcalloc(chip->num_regs, in regmap_add_irq_chip_fwnode()
727 sizeof(*d->type_buf_def), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
728 if (!d->type_buf_def) in regmap_add_irq_chip_fwnode()
731 d->type_buf = kcalloc(chip->num_regs, sizeof(*d->type_buf), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
732 if (!d->type_buf) in regmap_add_irq_chip_fwnode()
736 if (chip->num_config_bases && chip->num_config_regs) { in regmap_add_irq_chip_fwnode()
740 d->config_buf = kcalloc(chip->num_config_bases, in regmap_add_irq_chip_fwnode()
741 sizeof(*d->config_buf), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
742 if (!d->config_buf) in regmap_add_irq_chip_fwnode()
745 for (i = 0; i < chip->num_config_bases; i++) { in regmap_add_irq_chip_fwnode()
746 d->config_buf[i] = kcalloc(chip->num_config_regs, in regmap_add_irq_chip_fwnode()
747 sizeof(**d->config_buf), in regmap_add_irq_chip_fwnode()
749 if (!d->config_buf[i]) in regmap_add_irq_chip_fwnode()
754 d->irq_chip = regmap_irq_chip; in regmap_add_irq_chip_fwnode()
755 d->irq_chip.name = chip->name; in regmap_add_irq_chip_fwnode()
756 d->irq = irq; in regmap_add_irq_chip_fwnode()
757 d->map = map; in regmap_add_irq_chip_fwnode()
758 d->chip = chip; in regmap_add_irq_chip_fwnode()
759 d->irq_base = irq_base; in regmap_add_irq_chip_fwnode()
761 if (chip->irq_reg_stride) in regmap_add_irq_chip_fwnode()
762 d->irq_reg_stride = chip->irq_reg_stride; in regmap_add_irq_chip_fwnode()
764 d->irq_reg_stride = 1; in regmap_add_irq_chip_fwnode()
766 if (chip->get_irq_reg) in regmap_add_irq_chip_fwnode()
767 d->get_irq_reg = chip->get_irq_reg; in regmap_add_irq_chip_fwnode()
769 d->get_irq_reg = regmap_irq_get_irq_reg_linear; in regmap_add_irq_chip_fwnode()
772 d->status_reg_buf = kmalloc_array(chip->num_regs, in regmap_add_irq_chip_fwnode()
773 map->format.val_bytes, in regmap_add_irq_chip_fwnode()
775 if (!d->status_reg_buf) in regmap_add_irq_chip_fwnode()
779 mutex_init(&d->lock); in regmap_add_irq_chip_fwnode()
781 for (i = 0; i < chip->num_irqs; i++) in regmap_add_irq_chip_fwnode()
782 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride] in regmap_add_irq_chip_fwnode()
783 |= chip->irqs[i].mask; in regmap_add_irq_chip_fwnode()
786 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
787 d->mask_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
789 if (chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
790 ret = chip->handle_mask_sync(i, d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
791 d->mask_buf[i], in regmap_add_irq_chip_fwnode()
792 chip->irq_drv_data); in regmap_add_irq_chip_fwnode()
797 if (chip->mask_base && !chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
798 reg = d->get_irq_reg(d, chip->mask_base, i); in regmap_add_irq_chip_fwnode()
799 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
800 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
801 d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
803 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
809 if (chip->unmask_base && !chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
810 reg = d->get_irq_reg(d, chip->unmask_base, i); in regmap_add_irq_chip_fwnode()
811 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
812 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
814 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
820 if (!chip->init_ack_masked) in regmap_add_irq_chip_fwnode()
824 if (d->chip->no_status) { in regmap_add_irq_chip_fwnode()
826 d->status_buf[i] = UINT_MAX; in regmap_add_irq_chip_fwnode()
828 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_add_irq_chip_fwnode()
829 ret = regmap_read(map, reg, &d->status_buf[i]); in regmap_add_irq_chip_fwnode()
831 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_add_irq_chip_fwnode()
837 if (chip->status_invert) in regmap_add_irq_chip_fwnode()
838 d->status_buf[i] = ~d->status_buf[i]; in regmap_add_irq_chip_fwnode()
840 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_add_irq_chip_fwnode()
841 reg = d->get_irq_reg(d, d->chip->ack_base, i); in regmap_add_irq_chip_fwnode()
842 if (chip->ack_invert) in regmap_add_irq_chip_fwnode()
844 ~(d->status_buf[i] & d->mask_buf[i])); in regmap_add_irq_chip_fwnode()
847 d->status_buf[i] & d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
848 if (chip->clear_ack) { in regmap_add_irq_chip_fwnode()
849 if (chip->ack_invert && !ret) in regmap_add_irq_chip_fwnode()
855 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
863 if (d->wake_buf) { in regmap_add_irq_chip_fwnode()
864 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
865 d->wake_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
866 reg = d->get_irq_reg(d, d->chip->wake_base, i); in regmap_add_irq_chip_fwnode()
868 if (chip->wake_invert) in regmap_add_irq_chip_fwnode()
869 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
870 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
873 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
874 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
875 d->wake_buf[i]); in regmap_add_irq_chip_fwnode()
877 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
884 ret = regmap_irq_create_domain(fwnode, irq_base, chip, d); in regmap_add_irq_chip_fwnode()
890 chip->name, d); in regmap_add_irq_chip_fwnode()
892 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n", in regmap_add_irq_chip_fwnode()
893 irq, chip->name, ret); in regmap_add_irq_chip_fwnode()
904 kfree(d->type_buf); in regmap_add_irq_chip_fwnode()
905 kfree(d->type_buf_def); in regmap_add_irq_chip_fwnode()
906 kfree(d->wake_buf); in regmap_add_irq_chip_fwnode()
907 kfree(d->mask_buf_def); in regmap_add_irq_chip_fwnode()
908 kfree(d->mask_buf); in regmap_add_irq_chip_fwnode()
909 kfree(d->main_status_buf); in regmap_add_irq_chip_fwnode()
910 kfree(d->status_buf); in regmap_add_irq_chip_fwnode()
911 kfree(d->status_reg_buf); in regmap_add_irq_chip_fwnode()
912 if (d->config_buf) { in regmap_add_irq_chip_fwnode()
913 for (i = 0; i < chip->num_config_bases; i++) in regmap_add_irq_chip_fwnode()
914 kfree(d->config_buf[i]); in regmap_add_irq_chip_fwnode()
915 kfree(d->config_buf); in regmap_add_irq_chip_fwnode()
923 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
929 * @chip: Configuration for the interrupt controller.
930 * @data: Runtime data structure for the controller, allocated on success.
932 * Returns 0 on success or an errno on failure.
938 int irq_base, const struct regmap_irq_chip *chip, in regmap_add_irq_chip() argument
941 return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq, in regmap_add_irq_chip()
942 irq_flags, irq_base, chip, data); in regmap_add_irq_chip()
947 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
952 * This function also disposes of all mapped IRQs on the chip.
965 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) { in regmap_del_irq_chip()
967 if (!d->chip->irqs[hwirq].mask) in regmap_del_irq_chip()
971 * Find the virtual irq of hwirq on chip and if it is in regmap_del_irq_chip()
974 virq = irq_find_mapping(d->domain, hwirq); in regmap_del_irq_chip()
979 irq_domain_remove(d->domain); in regmap_del_irq_chip()
980 kfree(d->type_buf); in regmap_del_irq_chip()
981 kfree(d->type_buf_def); in regmap_del_irq_chip()
982 kfree(d->wake_buf); in regmap_del_irq_chip()
983 kfree(d->mask_buf_def); in regmap_del_irq_chip()
984 kfree(d->mask_buf); in regmap_del_irq_chip()
985 kfree(d->main_status_buf); in regmap_del_irq_chip()
986 kfree(d->status_reg_buf); in regmap_del_irq_chip()
987 kfree(d->status_buf); in regmap_del_irq_chip()
988 if (d->config_buf) { in regmap_del_irq_chip()
989 for (i = 0; i < d->chip->num_config_bases; i++) in regmap_del_irq_chip()
990 kfree(d->config_buf[i]); in regmap_del_irq_chip()
991 kfree(d->config_buf); in regmap_del_irq_chip()
1001 regmap_del_irq_chip(d->irq, d); in devm_regmap_irq_chip_release()
1017 * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
1019 * @dev: The device pointer on which irq_chip belongs to.
1025 * @chip: Configuration for the interrupt controller.
1026 * @data: Runtime data structure for the controller, allocated on success
1028 * Returns 0 on success or an errno on failure.
1037 const struct regmap_irq_chip *chip, in devm_regmap_add_irq_chip_fwnode() argument
1046 return -ENOMEM; in devm_regmap_add_irq_chip_fwnode()
1049 chip, &d); in devm_regmap_add_irq_chip_fwnode()
1063 * devm_regmap_add_irq_chip() - Resource managed regmap_add_irq_chip()
1065 * @dev: The device pointer on which irq_chip belongs to.
1070 * @chip: Configuration for the interrupt controller.
1071 * @data: Runtime data structure for the controller, allocated on success
1073 * Returns 0 on success or an errno on failure.
1080 const struct regmap_irq_chip *chip, in devm_regmap_add_irq_chip() argument
1083 return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map, in devm_regmap_add_irq_chip()
1084 irq, irq_flags, irq_base, chip, in devm_regmap_add_irq_chip()
1090 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
1103 WARN_ON(irq != data->irq); in devm_regmap_del_irq_chip()
1113 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
1115 * @data: regmap irq controller to operate on.
1121 WARN_ON(!data->irq_base); in regmap_irq_chip_get_base()
1122 return data->irq_base; in regmap_irq_chip_get_base()
1127 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
1129 * @data: regmap irq controller to operate on.
1130 * @irq: index of the interrupt requested in the chip IRQs.
1137 if (!data->chip->irqs[irq].mask) in regmap_irq_get_virq()
1138 return -EINVAL; in regmap_irq_get_virq()
1140 return irq_create_mapping(data->domain, irq); in regmap_irq_get_virq()
1145 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
1147 * @data: regmap_irq controller to operate on.
1157 return data->domain; in regmap_irq_get_domain()