1fc143580SKajol Jain[ 2fc143580SKajol Jain { 3*0edee819SKajol Jain "EventCode": "0x1505E", 4*0edee819SKajol Jain "EventName": "PM_LD_HIT_L1", 5*0edee819SKajol Jain "BriefDescription": "Load finished without experiencing an L1 miss." 6*0edee819SKajol Jain }, 7*0edee819SKajol Jain { 8*0edee819SKajol Jain "EventCode": "0x100FC", 9*0edee819SKajol Jain "EventName": "PM_LD_REF_L1", 10*0edee819SKajol Jain "BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included." 11*0edee819SKajol Jain }, 12*0edee819SKajol Jain { 13fc143580SKajol Jain "EventCode": "0x200FE", 14fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2MISS", 15fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss." 16fc143580SKajol Jain }, 17fc143580SKajol Jain { 18fc143580SKajol Jain "EventCode": "0x300FE", 19fc143580SKajol Jain "EventName": "PM_DATA_FROM_L3MISS", 20fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss." 21fc143580SKajol Jain }, 22fc143580SKajol Jain { 23*0edee819SKajol Jain "EventCode": "0x400F0", 24*0edee819SKajol Jain "EventName": "PM_LD_DEMAND_MISS_L1_FIN", 25*0edee819SKajol Jain "BriefDescription": "Load missed L1, counted at finish time." 26*0edee819SKajol Jain }, 27*0edee819SKajol Jain { 28fc143580SKajol Jain "EventCode": "0x400FE", 29fc143580SKajol Jain "EventName": "PM_DATA_FROM_MEMORY", 30fc143580SKajol Jain "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss." 31fc143580SKajol Jain }, 32fc143580SKajol Jain { 33c5d50457SKajol Jain "EventCode": "0x0000004080", 34c5d50457SKajol Jain "EventName": "PM_INST_FROM_L1", 35c5d50457SKajol Jain "BriefDescription": "An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched." 36c5d50457SKajol Jain }, 37c5d50457SKajol Jain { 38c5d50457SKajol Jain "EventCode": "0x000000026080", 39c5d50457SKajol Jain "EventName": "PM_L2_LD_MISS", 40c5d50457SKajol Jain "BriefDescription": "All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." 41c5d50457SKajol Jain }, 42c5d50457SKajol Jain { 43c5d50457SKajol Jain "EventCode": "0x000000026880", 44c5d50457SKajol Jain "EventName": "PM_L2_ST_MISS", 45c5d50457SKajol Jain "BriefDescription": "All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." 46c5d50457SKajol Jain }, 47c5d50457SKajol Jain { 48c5d50457SKajol Jain "EventCode": "0x010000046880", 49c5d50457SKajol Jain "EventName": "PM_L2_ST_HIT", 50c5d50457SKajol Jain "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." 51c5d50457SKajol Jain }, 52c5d50457SKajol Jain { 53c5d50457SKajol Jain "EventCode": "0x000000036880", 54c5d50457SKajol Jain "EventName": "PM_L2_INST_MISS", 55c5d50457SKajol Jain "BriefDescription": "All successful instruction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." 56c5d50457SKajol Jain }, 57c5d50457SKajol Jain { 58fc143580SKajol Jain "EventCode": "0x000300000000C040", 59fc143580SKajol Jain "EventName": "PM_INST_FROM_L2", 60fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss." 61fc143580SKajol Jain }, 62fc143580SKajol Jain { 63fc143580SKajol Jain "EventCode": "0x000340000000C040", 64fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2", 65fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss." 66fc143580SKajol Jain }, 67fc143580SKajol Jain { 68fc143580SKajol Jain "EventCode": "0x000300000010C040", 69fc143580SKajol Jain "EventName": "PM_INST_FROM_L2_ALL", 70fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload." 71fc143580SKajol Jain }, 72fc143580SKajol Jain { 73fc143580SKajol Jain "EventCode": "0x000340000020C040", 74fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2_ALL", 75fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload." 76fc143580SKajol Jain }, 77fc143580SKajol Jain { 78fc143580SKajol Jain "EventCode": "0x003F00000000C040", 79fc143580SKajol Jain "EventName": "PM_INST_FROM_L1MISS", 80fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss." 81fc143580SKajol Jain }, 82fc143580SKajol Jain { 83fc143580SKajol Jain "EventCode": "0x003F40000000C040", 84fc143580SKajol Jain "EventName": "PM_DATA_FROM_L1MISS", 85fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss." 86fc143580SKajol Jain }, 87fc143580SKajol Jain { 88fc143580SKajol Jain "EventCode": "0x003F00000010C040", 89fc143580SKajol Jain "EventName": "PM_INST_FROM_L1MISS_ALL", 90fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload." 91fc143580SKajol Jain }, 92fc143580SKajol Jain { 93fc143580SKajol Jain "EventCode": "0x003F40000020C040", 94fc143580SKajol Jain "EventName": "PM_DATA_FROM_L1MISS_ALL", 95fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload." 96fc143580SKajol Jain }, 97fc143580SKajol Jain { 98fc143580SKajol Jain "EventCode": "0x000040000000C040", 99fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2_NO_CONFLICT", 100fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss." 101fc143580SKajol Jain }, 102fc143580SKajol Jain { 103fc143580SKajol Jain "EventCode": "0x000040000020C040", 104fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2_NO_CONFLICT_ALL", 105fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload." 106fc143580SKajol Jain }, 107fc143580SKajol Jain { 108fc143580SKajol Jain "EventCode": "0x004040000000C040", 109fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2_MEPF", 110fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss." 111fc143580SKajol Jain }, 112fc143580SKajol Jain { 113fc143580SKajol Jain "EventCode": "0x004040000020C040", 114fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2_MEPF_ALL", 115fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload." 116fc143580SKajol Jain }, 117fc143580SKajol Jain { 118fc143580SKajol Jain "EventCode": "0x008040000000C040", 119fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2_LDHITST_CONFLICT", 120fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss." 121fc143580SKajol Jain }, 122fc143580SKajol Jain { 123fc143580SKajol Jain "EventCode": "0x008040000020C040", 124fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2_LDHITST_CONFLICT_ALL", 125fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload." 126fc143580SKajol Jain }, 127fc143580SKajol Jain { 128fc143580SKajol Jain "EventCode": "0x00C040000000C040", 129fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2_OTHER_CONFLICT", 130fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss." 131fc143580SKajol Jain }, 132fc143580SKajol Jain { 133fc143580SKajol Jain "EventCode": "0x00C040000020C040", 134fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2_OTHER_CONFLICT_ALL", 135fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload." 136fc143580SKajol Jain }, 137fc143580SKajol Jain { 138fc143580SKajol Jain "EventCode": "0x000380000000C040", 139fc143580SKajol Jain "EventName": "PM_INST_FROM_L2MISS", 140fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss." 141fc143580SKajol Jain }, 142fc143580SKajol Jain { 1439eef4101SAthira Rajeev "EventCode": "0x0003C0000000C040", 1449eef4101SAthira Rajeev "EventName": "PM_DATA_FROM_L2MISS_DSRC", 1459eef4101SAthira Rajeev "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss." 1469eef4101SAthira Rajeev }, 1479eef4101SAthira Rajeev { 148fc143580SKajol Jain "EventCode": "0x000380000010C040", 149fc143580SKajol Jain "EventName": "PM_INST_FROM_L2MISS_ALL", 150fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload." 151fc143580SKajol Jain }, 152fc143580SKajol Jain { 153fc143580SKajol Jain "EventCode": "0x0003C0000020C040", 154fc143580SKajol Jain "EventName": "PM_DATA_FROM_L2MISS_ALL", 155fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload." 156fc143580SKajol Jain }, 157fc143580SKajol Jain { 158fc143580SKajol Jain "EventCode": "0x010300000000C040", 159fc143580SKajol Jain "EventName": "PM_INST_FROM_L3", 160fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss." 161fc143580SKajol Jain }, 162fc143580SKajol Jain { 163fc143580SKajol Jain "EventCode": "0x010340000000C040", 164fc143580SKajol Jain "EventName": "PM_DATA_FROM_L3", 165fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss." 166fc143580SKajol Jain }, 167fc143580SKajol Jain { 168fc143580SKajol Jain "EventCode": "0x010300000010C040", 169fc143580SKajol Jain "EventName": "PM_INST_FROM_L3_ALL", 170fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload." 171fc143580SKajol Jain }, 172fc143580SKajol Jain { 173fc143580SKajol Jain "EventCode": "0x010340000020C040", 174fc143580SKajol Jain "EventName": "PM_DATA_FROM_L3_ALL", 175fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload." 176fc143580SKajol Jain }, 177fc143580SKajol Jain { 178fc143580SKajol Jain "EventCode": "0x010040000000C040", 179fc143580SKajol Jain "EventName": "PM_DATA_FROM_L3_NO_CONFLICT", 180fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss." 181fc143580SKajol Jain }, 182fc143580SKajol Jain { 183fc143580SKajol Jain "EventCode": "0x010040000020C040", 184fc143580SKajol Jain "EventName": "PM_DATA_FROM_L3_NO_CONFLICT_ALL", 185fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload." 186fc143580SKajol Jain }, 187fc143580SKajol Jain { 188fc143580SKajol Jain "EventCode": "0x014040000000C040", 189fc143580SKajol Jain "EventName": "PM_DATA_FROM_L3_MEPF", 190fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss." 191fc143580SKajol Jain }, 192fc143580SKajol Jain { 193fc143580SKajol Jain "EventCode": "0x014040000020C040", 194fc143580SKajol Jain "EventName": "PM_DATA_FROM_L3_MEPF_ALL", 195fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload." 196fc143580SKajol Jain }, 197fc143580SKajol Jain { 198fc143580SKajol Jain "EventCode": "0x01C040000000C040", 199fc143580SKajol Jain "EventName": "PM_DATA_FROM_L3_CONFLICT", 200fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss." 201fc143580SKajol Jain }, 202fc143580SKajol Jain { 203fc143580SKajol Jain "EventCode": "0x01C040000020C040", 204fc143580SKajol Jain "EventName": "PM_DATA_FROM_L3_CONFLICT_ALL", 205fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload." 206fc143580SKajol Jain }, 207fc143580SKajol Jain { 208fc143580SKajol Jain "EventCode": "0x000780000000C040", 2099eef4101SAthira Rajeev "EventName": "PM_INST_FROM_L3MISS_DSRC", 210fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss." 211fc143580SKajol Jain }, 212fc143580SKajol Jain { 2139eef4101SAthira Rajeev "EventCode": "0x0007C0000000C040", 2149eef4101SAthira Rajeev "EventName": "PM_DATA_FROM_L3MISS_DSRC", 2159eef4101SAthira Rajeev "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss." 2169eef4101SAthira Rajeev }, 2179eef4101SAthira Rajeev { 218fc143580SKajol Jain "EventCode": "0x000780000010C040", 219fc143580SKajol Jain "EventName": "PM_INST_FROM_L3MISS_ALL", 220fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload." 221fc143580SKajol Jain }, 222fc143580SKajol Jain { 223fc143580SKajol Jain "EventCode": "0x0007C0000020C040", 224fc143580SKajol Jain "EventName": "PM_DATA_FROM_L3MISS_ALL", 225fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload." 226fc143580SKajol Jain }, 227fc143580SKajol Jain { 228fc143580SKajol Jain "EventCode": "0x080040000000C040", 229fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_REGENT_SHR", 230fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss." 231fc143580SKajol Jain }, 232fc143580SKajol Jain { 233fc143580SKajol Jain "EventCode": "0x080040000020C040", 234fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_REGENT_SHR_ALL", 235fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload." 236fc143580SKajol Jain }, 237fc143580SKajol Jain { 238fc143580SKajol Jain "EventCode": "0x084040000000C040", 239fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_REGENT_MOD", 240fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss." 241fc143580SKajol Jain }, 242fc143580SKajol Jain { 243fc143580SKajol Jain "EventCode": "0x084040000020C040", 244fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_REGENT_MOD_ALL", 245fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload." 246fc143580SKajol Jain }, 247fc143580SKajol Jain { 248fc143580SKajol Jain "EventCode": "0x080100000000C040", 249fc143580SKajol Jain "EventName": "PM_INST_FROM_L21_REGENT", 250fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss." 251fc143580SKajol Jain }, 252fc143580SKajol Jain { 253fc143580SKajol Jain "EventCode": "0x080140000000C040", 254fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_REGENT", 255fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss." 256fc143580SKajol Jain }, 257fc143580SKajol Jain { 258fc143580SKajol Jain "EventCode": "0x080100000010C040", 259fc143580SKajol Jain "EventName": "PM_INST_FROM_L21_REGENT_ALL", 260fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload." 261fc143580SKajol Jain }, 262fc143580SKajol Jain { 263fc143580SKajol Jain "EventCode": "0x080140000020C040", 264fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_REGENT_ALL", 265fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload." 266fc143580SKajol Jain }, 267fc143580SKajol Jain { 268fc143580SKajol Jain "EventCode": "0x088040000000C040", 269fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_REGENT_SHR", 270fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss." 271fc143580SKajol Jain }, 272fc143580SKajol Jain { 273fc143580SKajol Jain "EventCode": "0x088040000020C040", 274fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_REGENT_SHR_ALL", 275fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload." 276fc143580SKajol Jain }, 277fc143580SKajol Jain { 278fc143580SKajol Jain "EventCode": "0x08C040000000C040", 279fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_REGENT_MOD", 280fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss." 281fc143580SKajol Jain }, 282fc143580SKajol Jain { 283fc143580SKajol Jain "EventCode": "0x08C040000020C040", 284fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_REGENT_MOD_ALL", 285fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload." 286fc143580SKajol Jain }, 287fc143580SKajol Jain { 288fc143580SKajol Jain "EventCode": "0x088100000000C040", 289fc143580SKajol Jain "EventName": "PM_INST_FROM_L31_REGENT", 290fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss." 291fc143580SKajol Jain }, 292fc143580SKajol Jain { 293fc143580SKajol Jain "EventCode": "0x088140000000C040", 294fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_REGENT", 295fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss." 296fc143580SKajol Jain }, 297fc143580SKajol Jain { 298fc143580SKajol Jain "EventCode": "0x088100000010C040", 299fc143580SKajol Jain "EventName": "PM_INST_FROM_L31_REGENT_ALL", 300fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload." 301fc143580SKajol Jain }, 302fc143580SKajol Jain { 303fc143580SKajol Jain "EventCode": "0x088140000020C040", 304fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_REGENT_ALL", 305fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload." 306fc143580SKajol Jain }, 307fc143580SKajol Jain { 308fc143580SKajol Jain "EventCode": "0x080240000000C040", 309fc143580SKajol Jain "EventName": "PM_DATA_FROM_REGENT_L2L3_SHR", 310fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss." 311fc143580SKajol Jain }, 312fc143580SKajol Jain { 313fc143580SKajol Jain "EventCode": "0x080240000020C040", 314fc143580SKajol Jain "EventName": "PM_DATA_FROM_REGENT_L2L3_SHR_ALL", 315fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload." 316fc143580SKajol Jain }, 317fc143580SKajol Jain { 318fc143580SKajol Jain "EventCode": "0x084240000000C040", 319fc143580SKajol Jain "EventName": "PM_DATA_FROM_REGENT_L2L3_MOD", 320fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss." 321fc143580SKajol Jain }, 322fc143580SKajol Jain { 323fc143580SKajol Jain "EventCode": "0x084240000020C040", 324fc143580SKajol Jain "EventName": "PM_DATA_FROM_REGENT_L2L3_MOD_ALL", 325fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload." 326fc143580SKajol Jain }, 327fc143580SKajol Jain { 328fc143580SKajol Jain "EventCode": "0x080300000000C040", 329fc143580SKajol Jain "EventName": "PM_INST_FROM_REGENT_L2L3", 330fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss." 331fc143580SKajol Jain }, 332fc143580SKajol Jain { 333fc143580SKajol Jain "EventCode": "0x080340000000C040", 334fc143580SKajol Jain "EventName": "PM_DATA_FROM_REGENT_L2L3", 335fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss." 336fc143580SKajol Jain }, 337fc143580SKajol Jain { 338fc143580SKajol Jain "EventCode": "0x080300000010C040", 339fc143580SKajol Jain "EventName": "PM_INST_FROM_REGENT_L2L3_ALL", 340fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload." 341fc143580SKajol Jain }, 342fc143580SKajol Jain { 343fc143580SKajol Jain "EventCode": "0x080340000020C040", 344fc143580SKajol Jain "EventName": "PM_DATA_FROM_REGENT_L2L3_ALL", 345fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload." 346fc143580SKajol Jain }, 347fc143580SKajol Jain { 348fc143580SKajol Jain "EventCode": "0x0A0040000000C040", 349fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_NON_REGENT_SHR", 350fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss." 351fc143580SKajol Jain }, 352fc143580SKajol Jain { 353fc143580SKajol Jain "EventCode": "0x0A0040000020C040", 354fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_NON_REGENT_SHR_ALL", 355fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload." 356fc143580SKajol Jain }, 357fc143580SKajol Jain { 358fc143580SKajol Jain "EventCode": "0x0A4040000000C040", 359fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_NON_REGENT_MOD", 360fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss." 361fc143580SKajol Jain }, 362fc143580SKajol Jain { 363fc143580SKajol Jain "EventCode": "0x0A4040000020C040", 364fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_NON_REGENT_MOD_ALL", 365fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload." 366fc143580SKajol Jain }, 367fc143580SKajol Jain { 368fc143580SKajol Jain "EventCode": "0x0A0100000000C040", 369fc143580SKajol Jain "EventName": "PM_INST_FROM_L21_NON_REGENT", 370fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss." 371fc143580SKajol Jain }, 372fc143580SKajol Jain { 373fc143580SKajol Jain "EventCode": "0x0A0140000000C040", 374fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_NON_REGENT", 375fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss." 376fc143580SKajol Jain }, 377fc143580SKajol Jain { 378fc143580SKajol Jain "EventCode": "0x0A0100000010C040", 379fc143580SKajol Jain "EventName": "PM_INST_FROM_L21_NON_REGENT_ALL", 380fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload." 381fc143580SKajol Jain }, 382fc143580SKajol Jain { 383fc143580SKajol Jain "EventCode": "0x0A0140000020C040", 384fc143580SKajol Jain "EventName": "PM_DATA_FROM_L21_NON_REGENT_ALL", 385fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload." 386fc143580SKajol Jain }, 387fc143580SKajol Jain { 388fc143580SKajol Jain "EventCode": "0x0A8040000000C040", 389fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_NON_REGENT_SHR", 390fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss." 391fc143580SKajol Jain }, 392fc143580SKajol Jain { 393fc143580SKajol Jain "EventCode": "0x0A8040000020C040", 394fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_NON_REGENT_SHR_ALL", 395fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload." 396fc143580SKajol Jain }, 397fc143580SKajol Jain { 398fc143580SKajol Jain "EventCode": "0x0AC040000000C040", 399fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_NON_REGENT_MOD", 400fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss." 401fc143580SKajol Jain }, 402fc143580SKajol Jain { 403fc143580SKajol Jain "EventCode": "0x0AC040000020C040", 404fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_NON_REGENT_MOD_ALL", 405fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload." 406fc143580SKajol Jain }, 407fc143580SKajol Jain { 408fc143580SKajol Jain "EventCode": "0x0A8100000000C040", 409fc143580SKajol Jain "EventName": "PM_INST_FROM_L31_NON_REGENT", 410fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss." 411fc143580SKajol Jain }, 412fc143580SKajol Jain { 413fc143580SKajol Jain "EventCode": "0x0A8140000000C040", 414fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_NON_REGENT", 415fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss." 416fc143580SKajol Jain }, 417fc143580SKajol Jain { 418fc143580SKajol Jain "EventCode": "0x0A8100000010C040", 419fc143580SKajol Jain "EventName": "PM_INST_FROM_L31_NON_REGENT_ALL", 420fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload." 421fc143580SKajol Jain }, 422fc143580SKajol Jain { 423fc143580SKajol Jain "EventCode": "0x0A8140000020C040", 424fc143580SKajol Jain "EventName": "PM_DATA_FROM_L31_NON_REGENT_ALL", 425fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload." 426fc143580SKajol Jain }, 427fc143580SKajol Jain { 428fc143580SKajol Jain "EventCode": "0x0A0240000000C040", 429fc143580SKajol Jain "EventName": "PM_DATA_FROM_NON_REGENT_L2L3_SHR", 430fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss." 431fc143580SKajol Jain }, 432fc143580SKajol Jain { 433fc143580SKajol Jain "EventCode": "0x0A0240000020C040", 434fc143580SKajol Jain "EventName": "PM_DATA_FROM_NON_REGENT_L2L3_SHR_ALL", 435fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload." 436fc143580SKajol Jain }, 437fc143580SKajol Jain { 438fc143580SKajol Jain "EventCode": "0x0A4240000000C040", 439fc143580SKajol Jain "EventName": "PM_DATA_FROM_NON_REGENT_L2L3_MOD", 440fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss." 441fc143580SKajol Jain }, 442fc143580SKajol Jain { 443fc143580SKajol Jain "EventCode": "0x0A4240000020C040", 444fc143580SKajol Jain "EventName": "PM_DATA_FROM_NON_REGENT_L2L3_MOD_ALL", 445fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload." 446fc143580SKajol Jain }, 447fc143580SKajol Jain { 448fc143580SKajol Jain "EventCode": "0x0A0300000000C040", 449fc143580SKajol Jain "EventName": "PM_INST_FROM_NON_REGENT_L2L3", 450fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss." 451fc143580SKajol Jain }, 452fc143580SKajol Jain { 453fc143580SKajol Jain "EventCode": "0x0A0340000000C040", 454fc143580SKajol Jain "EventName": "PM_DATA_FROM_NON_REGENT_L2L3", 455fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss." 456fc143580SKajol Jain }, 457fc143580SKajol Jain { 458fc143580SKajol Jain "EventCode": "0x0A0300000010C040", 459fc143580SKajol Jain "EventName": "PM_INST_FROM_NON_REGENT_L2L3_ALL", 460fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload." 461fc143580SKajol Jain }, 462fc143580SKajol Jain { 463fc143580SKajol Jain "EventCode": "0x0A0340000020C040", 464fc143580SKajol Jain "EventName": "PM_DATA_FROM_NON_REGENT_L2L3_ALL", 465fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload." 466fc143580SKajol Jain }, 467fc143580SKajol Jain { 468fc143580SKajol Jain "EventCode": "0x094100000000C040", 469fc143580SKajol Jain "EventName": "PM_INST_FROM_LMEM", 470fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory due to a demand miss." 471fc143580SKajol Jain }, 472fc143580SKajol Jain { 473fc143580SKajol Jain "EventCode": "0x094040000000C040", 474fc143580SKajol Jain "EventName": "PM_DATA_FROM_LMEM", 475fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss." 476fc143580SKajol Jain }, 477fc143580SKajol Jain { 478fc143580SKajol Jain "EventCode": "0x094100000010C040", 479fc143580SKajol Jain "EventName": "PM_INST_FROM_LMEM_ALL", 480fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload." 481fc143580SKajol Jain }, 482fc143580SKajol Jain { 483fc143580SKajol Jain "EventCode": "0x094040000020C040", 484fc143580SKajol Jain "EventName": "PM_DATA_FROM_LMEM_ALL", 485fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload." 486fc143580SKajol Jain }, 487fc143580SKajol Jain { 488fc143580SKajol Jain "EventCode": "0x098040000000C040", 489fc143580SKajol Jain "EventName": "PM_DATA_FROM_L_OC_CACHE", 490fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss." 491fc143580SKajol Jain }, 492fc143580SKajol Jain { 493fc143580SKajol Jain "EventCode": "0x098040000020C040", 494fc143580SKajol Jain "EventName": "PM_DATA_FROM_L_OC_CACHE_ALL", 495fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss or prefetch reload." 496fc143580SKajol Jain }, 497fc143580SKajol Jain { 498fc143580SKajol Jain "EventCode": "0x09C040000000C040", 499fc143580SKajol Jain "EventName": "PM_DATA_FROM_L_OC_MEM", 500fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss." 501fc143580SKajol Jain }, 502fc143580SKajol Jain { 503fc143580SKajol Jain "EventCode": "0x09C040000020C040", 504fc143580SKajol Jain "EventName": "PM_DATA_FROM_L_OC_MEM_ALL", 505fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss or prefetch reload." 506fc143580SKajol Jain }, 507fc143580SKajol Jain { 508fc143580SKajol Jain "EventCode": "0x098100000000C040", 509fc143580SKajol Jain "EventName": "PM_INST_FROM_L_OC_ANY", 510fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss." 511fc143580SKajol Jain }, 512fc143580SKajol Jain { 513fc143580SKajol Jain "EventCode": "0x098140000000C040", 514fc143580SKajol Jain "EventName": "PM_DATA_FROM_L_OC_ANY", 515fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss." 516fc143580SKajol Jain }, 517fc143580SKajol Jain { 518fc143580SKajol Jain "EventCode": "0x098100000010C040", 519fc143580SKajol Jain "EventName": "PM_INST_FROM_L_OC_ANY_ALL", 520fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload." 521fc143580SKajol Jain }, 522fc143580SKajol Jain { 523fc143580SKajol Jain "EventCode": "0x098140000020C040", 524fc143580SKajol Jain "EventName": "PM_DATA_FROM_L_OC_ANY_ALL", 525fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload." 526fc143580SKajol Jain }, 527fc143580SKajol Jain { 528fc143580SKajol Jain "EventCode": "0x0C0040000000C040", 529fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2_SHR", 530fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss." 531fc143580SKajol Jain }, 532fc143580SKajol Jain { 533fc143580SKajol Jain "EventCode": "0x0C0040000020C040", 534fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2_SHR_ALL", 535fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload." 536fc143580SKajol Jain }, 537fc143580SKajol Jain { 538fc143580SKajol Jain "EventCode": "0x0C4040000000C040", 539fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2_MOD", 540fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss." 541fc143580SKajol Jain }, 542fc143580SKajol Jain { 543fc143580SKajol Jain "EventCode": "0x0C4040000020C040", 544fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2_MOD_ALL", 545fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload." 546fc143580SKajol Jain }, 547fc143580SKajol Jain { 548fc143580SKajol Jain "EventCode": "0x0C0100000000C040", 549fc143580SKajol Jain "EventName": "PM_INST_FROM_RL2", 550fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss." 551fc143580SKajol Jain }, 552fc143580SKajol Jain { 553fc143580SKajol Jain "EventCode": "0x0C0140000000C040", 554fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2", 555fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss." 556fc143580SKajol Jain }, 557fc143580SKajol Jain { 558fc143580SKajol Jain "EventCode": "0x0C0100000010C040", 559fc143580SKajol Jain "EventName": "PM_INST_FROM_RL2_ALL", 560fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload." 561fc143580SKajol Jain }, 562fc143580SKajol Jain { 563fc143580SKajol Jain "EventCode": "0x0C0140000020C040", 564fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2_ALL", 565fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload." 566fc143580SKajol Jain }, 567fc143580SKajol Jain { 568fc143580SKajol Jain "EventCode": "0x0C8040000000C040", 569fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL3_SHR", 570fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss." 571fc143580SKajol Jain }, 572fc143580SKajol Jain { 573fc143580SKajol Jain "EventCode": "0x0C8040000020C040", 574fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL3_SHR_ALL", 575fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload." 576fc143580SKajol Jain }, 577fc143580SKajol Jain { 578fc143580SKajol Jain "EventCode": "0x0CC040000000C040", 579fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL3_MOD", 580fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss." 581fc143580SKajol Jain }, 582fc143580SKajol Jain { 583fc143580SKajol Jain "EventCode": "0x0CC040000020C040", 584fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL3_MOD_ALL", 585fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload." 586fc143580SKajol Jain }, 587fc143580SKajol Jain { 588fc143580SKajol Jain "EventCode": "0x0C8100000000C040", 589fc143580SKajol Jain "EventName": "PM_INST_FROM_RL3", 590fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss." 591fc143580SKajol Jain }, 592fc143580SKajol Jain { 593fc143580SKajol Jain "EventCode": "0x0C8140000000C040", 594fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL3", 595fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss." 596fc143580SKajol Jain }, 597fc143580SKajol Jain { 598fc143580SKajol Jain "EventCode": "0x0C8100000010C040", 599fc143580SKajol Jain "EventName": "PM_INST_FROM_RL3_ALL", 600fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload." 601fc143580SKajol Jain }, 602fc143580SKajol Jain { 603fc143580SKajol Jain "EventCode": "0x0C8140000020C040", 604fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL3_ALL", 605fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload." 606fc143580SKajol Jain }, 607fc143580SKajol Jain { 608fc143580SKajol Jain "EventCode": "0x0C0240000000C040", 609fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2L3_SHR", 610fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss." 611fc143580SKajol Jain }, 612fc143580SKajol Jain { 613fc143580SKajol Jain "EventCode": "0x0C0240000020C040", 614fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2L3_SHR_ALL", 615fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload." 616fc143580SKajol Jain }, 617fc143580SKajol Jain { 618fc143580SKajol Jain "EventCode": "0x0C4240000000C040", 619fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2L3_MOD", 620fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss." 621fc143580SKajol Jain }, 622fc143580SKajol Jain { 623fc143580SKajol Jain "EventCode": "0x0C4240000020C040", 624fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2L3_MOD_ALL", 625fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload." 626fc143580SKajol Jain }, 627fc143580SKajol Jain { 628fc143580SKajol Jain "EventCode": "0x0C0300000000C040", 629fc143580SKajol Jain "EventName": "PM_INST_FROM_RL2L3", 630fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss." 631fc143580SKajol Jain }, 632fc143580SKajol Jain { 633fc143580SKajol Jain "EventCode": "0x0C0340000000C040", 634fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2L3", 635fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss." 636fc143580SKajol Jain }, 637fc143580SKajol Jain { 638fc143580SKajol Jain "EventCode": "0x0C0300000010C040", 639fc143580SKajol Jain "EventName": "PM_INST_FROM_RL2L3_ALL", 640fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload." 641fc143580SKajol Jain }, 642fc143580SKajol Jain { 643fc143580SKajol Jain "EventCode": "0x0C0340000020C040", 644fc143580SKajol Jain "EventName": "PM_DATA_FROM_RL2L3_ALL", 645fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload." 646fc143580SKajol Jain }, 647fc143580SKajol Jain { 648fc143580SKajol Jain "EventCode": "0x0D4100000000C040", 649fc143580SKajol Jain "EventName": "PM_INST_FROM_RMEM", 650fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss." 651fc143580SKajol Jain }, 652fc143580SKajol Jain { 653fc143580SKajol Jain "EventCode": "0x0D4040000000C040", 654fc143580SKajol Jain "EventName": "PM_DATA_FROM_RMEM", 655fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss." 656fc143580SKajol Jain }, 657fc143580SKajol Jain { 658fc143580SKajol Jain "EventCode": "0x0D4100000010C040", 659fc143580SKajol Jain "EventName": "PM_INST_FROM_RMEM_ALL", 660fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload." 661fc143580SKajol Jain }, 662fc143580SKajol Jain { 663fc143580SKajol Jain "EventCode": "0x0D4040000020C040", 664fc143580SKajol Jain "EventName": "PM_DATA_FROM_RMEM_ALL", 665fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload." 666fc143580SKajol Jain }, 667fc143580SKajol Jain { 668fc143580SKajol Jain "EventCode": "0x0D8040000000C040", 669fc143580SKajol Jain "EventName": "PM_DATA_FROM_R_OC_CACHE", 670fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss." 671fc143580SKajol Jain }, 672fc143580SKajol Jain { 673fc143580SKajol Jain "EventCode": "0x0D8040000020C040", 674fc143580SKajol Jain "EventName": "PM_DATA_FROM_R_OC_CACHE_ALL", 675fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss or prefetch reload." 676fc143580SKajol Jain }, 677fc143580SKajol Jain { 678fc143580SKajol Jain "EventCode": "0x0DC040000000C040", 679fc143580SKajol Jain "EventName": "PM_DATA_FROM_R_OC_MEM", 680fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss." 681fc143580SKajol Jain }, 682fc143580SKajol Jain { 683fc143580SKajol Jain "EventCode": "0x0DC040000020C040", 684fc143580SKajol Jain "EventName": "PM_DATA_FROM_R_OC_MEM_ALL", 685fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss or prefetch reload." 686fc143580SKajol Jain }, 687fc143580SKajol Jain { 688fc143580SKajol Jain "EventCode": "0x0D8100000000C040", 689fc143580SKajol Jain "EventName": "PM_INST_FROM_R_OC_ANY", 690fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss." 691fc143580SKajol Jain }, 692fc143580SKajol Jain { 693fc143580SKajol Jain "EventCode": "0x0D8140000000C040", 694fc143580SKajol Jain "EventName": "PM_DATA_FROM_R_OC_ANY", 695fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss." 696fc143580SKajol Jain }, 697fc143580SKajol Jain { 698fc143580SKajol Jain "EventCode": "0x0D8100000010C040", 699fc143580SKajol Jain "EventName": "PM_INST_FROM_R_OC_ANY_ALL", 700fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload." 701fc143580SKajol Jain }, 702fc143580SKajol Jain { 703fc143580SKajol Jain "EventCode": "0x0D8140000020C040", 704fc143580SKajol Jain "EventName": "PM_DATA_FROM_R_OC_ANY_ALL", 705fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload." 706fc143580SKajol Jain }, 707fc143580SKajol Jain { 708fc143580SKajol Jain "EventCode": "0x0E0040000000C040", 709fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2_SHR", 710fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss." 711fc143580SKajol Jain }, 712fc143580SKajol Jain { 713fc143580SKajol Jain "EventCode": "0x0E0040000020C040", 714fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2_SHR_ALL", 715fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload." 716fc143580SKajol Jain }, 717fc143580SKajol Jain { 718fc143580SKajol Jain "EventCode": "0x0E4040000000C040", 719fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2_MOD", 720fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss." 721fc143580SKajol Jain }, 722fc143580SKajol Jain { 723fc143580SKajol Jain "EventCode": "0x0E4040000020C040", 724fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2_MOD_ALL", 725fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload." 726fc143580SKajol Jain }, 727fc143580SKajol Jain { 728fc143580SKajol Jain "EventCode": "0x0E0100000000C040", 729fc143580SKajol Jain "EventName": "PM_INST_FROM_DL2", 730fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss." 731fc143580SKajol Jain }, 732fc143580SKajol Jain { 733fc143580SKajol Jain "EventCode": "0x0E0140000000C040", 734fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2", 735fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss." 736fc143580SKajol Jain }, 737fc143580SKajol Jain { 738fc143580SKajol Jain "EventCode": "0x0E0100000010C040", 739fc143580SKajol Jain "EventName": "PM_INST_FROM_DL2_ALL", 740fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload." 741fc143580SKajol Jain }, 742fc143580SKajol Jain { 743fc143580SKajol Jain "EventCode": "0x0E0140000020C040", 744fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2_ALL", 745fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload." 746fc143580SKajol Jain }, 747fc143580SKajol Jain { 748fc143580SKajol Jain "EventCode": "0x0E8040000000C040", 749fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL3_SHR", 750fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss." 751fc143580SKajol Jain }, 752fc143580SKajol Jain { 753fc143580SKajol Jain "EventCode": "0x0E8040000020C040", 754fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL3_SHR_ALL", 755fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload." 756fc143580SKajol Jain }, 757fc143580SKajol Jain { 758fc143580SKajol Jain "EventCode": "0x0EC040000000C040", 759fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL3_MOD", 760fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss." 761fc143580SKajol Jain }, 762fc143580SKajol Jain { 763fc143580SKajol Jain "EventCode": "0x0EC040000020C040", 764fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL3_MOD_ALL", 765fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload." 766fc143580SKajol Jain }, 767fc143580SKajol Jain { 768fc143580SKajol Jain "EventCode": "0x0E8100000000C040", 769fc143580SKajol Jain "EventName": "PM_INST_FROM_DL3", 770fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss." 771fc143580SKajol Jain }, 772fc143580SKajol Jain { 773fc143580SKajol Jain "EventCode": "0x0E8140000000C040", 774fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL3", 775fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss." 776fc143580SKajol Jain }, 777fc143580SKajol Jain { 778fc143580SKajol Jain "EventCode": "0x0E8100000010C040", 779fc143580SKajol Jain "EventName": "PM_INST_FROM_DL3_ALL", 780fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload." 781fc143580SKajol Jain }, 782fc143580SKajol Jain { 783fc143580SKajol Jain "EventCode": "0x0E8140000020C040", 784fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL3_ALL", 785fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload." 786fc143580SKajol Jain }, 787fc143580SKajol Jain { 788fc143580SKajol Jain "EventCode": "0x0E0240000000C040", 789fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2L3_SHR", 790fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss." 791fc143580SKajol Jain }, 792fc143580SKajol Jain { 793fc143580SKajol Jain "EventCode": "0x0E0240000020C040", 794fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2L3_SHR_ALL", 795fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload." 796fc143580SKajol Jain }, 797fc143580SKajol Jain { 798fc143580SKajol Jain "EventCode": "0x0E4240000000C040", 799fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2L3_MOD", 800fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss." 801fc143580SKajol Jain }, 802fc143580SKajol Jain { 803fc143580SKajol Jain "EventCode": "0x0E4240000020C040", 804fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2L3_MOD_ALL", 805fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload." 806fc143580SKajol Jain }, 807fc143580SKajol Jain { 808fc143580SKajol Jain "EventCode": "0x0E0300000000C040", 809fc143580SKajol Jain "EventName": "PM_INST_FROM_DL2L3", 810fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss." 811fc143580SKajol Jain }, 812fc143580SKajol Jain { 813fc143580SKajol Jain "EventCode": "0x0E0340000000C040", 814fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2L3", 815fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss." 816fc143580SKajol Jain }, 817fc143580SKajol Jain { 818fc143580SKajol Jain "EventCode": "0x0E0300000010C040", 819fc143580SKajol Jain "EventName": "PM_INST_FROM_DL2L3_ALL", 820fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload." 821fc143580SKajol Jain }, 822fc143580SKajol Jain { 823fc143580SKajol Jain "EventCode": "0x0E0340000020C040", 824fc143580SKajol Jain "EventName": "PM_DATA_FROM_DL2L3_ALL", 825fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload." 826fc143580SKajol Jain }, 827fc143580SKajol Jain { 828fc143580SKajol Jain "EventCode": "0x0F4100000000C040", 829fc143580SKajol Jain "EventName": "PM_INST_FROM_DMEM", 830fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss." 831fc143580SKajol Jain }, 832fc143580SKajol Jain { 833fc143580SKajol Jain "EventCode": "0x0F4040000000C040", 834fc143580SKajol Jain "EventName": "PM_DATA_FROM_DMEM", 835fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss." 836fc143580SKajol Jain }, 837fc143580SKajol Jain { 838fc143580SKajol Jain "EventCode": "0x0F4100000010C040", 839fc143580SKajol Jain "EventName": "PM_INST_FROM_DMEM_ALL", 840fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload." 841fc143580SKajol Jain }, 842fc143580SKajol Jain { 843fc143580SKajol Jain "EventCode": "0x0F4040000020C040", 844fc143580SKajol Jain "EventName": "PM_DATA_FROM_DMEM_ALL", 845fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload." 846fc143580SKajol Jain }, 847fc143580SKajol Jain { 848fc143580SKajol Jain "EventCode": "0x0F8040000000C040", 849fc143580SKajol Jain "EventName": "PM_DATA_FROM_D_OC_CACHE", 850fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss." 851fc143580SKajol Jain }, 852fc143580SKajol Jain { 853fc143580SKajol Jain "EventCode": "0x0F8040000020C040", 854fc143580SKajol Jain "EventName": "PM_DATA_FROM_D_OC_CACHE_ALL", 855fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss or prefetch reload." 856fc143580SKajol Jain }, 857fc143580SKajol Jain { 858fc143580SKajol Jain "EventCode": "0x0FC040000000C040", 859fc143580SKajol Jain "EventName": "PM_DATA_FROM_D_OC_MEM", 860fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss." 861fc143580SKajol Jain }, 862fc143580SKajol Jain { 863fc143580SKajol Jain "EventCode": "0x0FC040000020C040", 864fc143580SKajol Jain "EventName": "PM_DATA_FROM_D_OC_MEM_ALL", 865fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss or prefetch reload." 866fc143580SKajol Jain }, 867fc143580SKajol Jain { 868fc143580SKajol Jain "EventCode": "0x0F8100000000C040", 869fc143580SKajol Jain "EventName": "PM_INST_FROM_D_OC_ANY", 870fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss." 871fc143580SKajol Jain }, 872fc143580SKajol Jain { 873fc143580SKajol Jain "EventCode": "0x0F8140000000C040", 874fc143580SKajol Jain "EventName": "PM_DATA_FROM_D_OC_ANY", 875fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss." 876fc143580SKajol Jain }, 877fc143580SKajol Jain { 878fc143580SKajol Jain "EventCode": "0x0F8100000010C040", 879fc143580SKajol Jain "EventName": "PM_INST_FROM_D_OC_ANY_ALL", 880fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload." 881fc143580SKajol Jain }, 882fc143580SKajol Jain { 883fc143580SKajol Jain "EventCode": "0x0F8140000020C040", 884fc143580SKajol Jain "EventName": "PM_DATA_FROM_D_OC_ANY_ALL", 885fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload." 886fc143580SKajol Jain }, 887fc143580SKajol Jain { 888fc143580SKajol Jain "EventCode": "0x080B00000000C040", 889fc143580SKajol Jain "EventName": "PM_INST_FROM_ONCHIP_CACHE", 890fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss." 891fc143580SKajol Jain }, 892fc143580SKajol Jain { 893fc143580SKajol Jain "EventCode": "0x080B40000000C040", 894fc143580SKajol Jain "EventName": "PM_DATA_FROM_ONCHIP_CACHE", 895fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss." 896fc143580SKajol Jain }, 897fc143580SKajol Jain { 898fc143580SKajol Jain "EventCode": "0x080B00000010C040", 899fc143580SKajol Jain "EventName": "PM_INST_FROM_ONCHIP_CACHE_ALL", 900fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload." 901fc143580SKajol Jain }, 902fc143580SKajol Jain { 903fc143580SKajol Jain "EventCode": "0x080B40000020C040", 904fc143580SKajol Jain "EventName": "PM_DATA_FROM_ONCHIP_CACHE_ALL", 905fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload." 906fc143580SKajol Jain }, 907fc143580SKajol Jain { 908fc143580SKajol Jain "EventCode": "0x0C0B00000000C040", 909fc143580SKajol Jain "EventName": "PM_INST_FROM_OFFCHIP_CACHE", 910fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss." 911fc143580SKajol Jain }, 912fc143580SKajol Jain { 913fc143580SKajol Jain "EventCode": "0x0C0B40000000C040", 914fc143580SKajol Jain "EventName": "PM_DATA_FROM_OFFCHIP_CACHE", 915fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss." 916fc143580SKajol Jain }, 917fc143580SKajol Jain { 918fc143580SKajol Jain "EventCode": "0x0C0B00000010C040", 919fc143580SKajol Jain "EventName": "PM_INST_FROM_OFFCHIP_CACHE_ALL", 920fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload." 921fc143580SKajol Jain }, 922fc143580SKajol Jain { 923fc143580SKajol Jain "EventCode": "0x0C0B40000020C040", 924fc143580SKajol Jain "EventName": "PM_DATA_FROM_OFFCHIP_CACHE_ALL", 925fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload." 926fc143580SKajol Jain }, 927fc143580SKajol Jain { 928fc143580SKajol Jain "EventCode": "0x095900000000C040", 929fc143580SKajol Jain "EventName": "PM_INST_FROM_ANY_MEMORY", 930fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss." 931fc143580SKajol Jain }, 932fc143580SKajol Jain { 933fc143580SKajol Jain "EventCode": "0x095840000000C040", 934fc143580SKajol Jain "EventName": "PM_DATA_FROM_ANY_MEMORY", 935fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss." 936fc143580SKajol Jain }, 937fc143580SKajol Jain { 938fc143580SKajol Jain "EventCode": "0x095900000010C040", 939fc143580SKajol Jain "EventName": "PM_INST_FROM_ANY_MEMORY_ALL", 940fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload." 941fc143580SKajol Jain }, 942fc143580SKajol Jain { 943fc143580SKajol Jain "EventCode": "0x095840000020C040", 944fc143580SKajol Jain "EventName": "PM_DATA_FROM_ANY_MEMORY_ALL", 945fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload." 946fc143580SKajol Jain }, 947fc143580SKajol Jain { 948fc143580SKajol Jain "EventCode": "0x000300000000C142", 949fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L2", 950fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss for a marked instruction." 951fc143580SKajol Jain }, 952fc143580SKajol Jain { 953fc143580SKajol Jain "EventCode": "0x000340000000C142", 954fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L2", 955fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked instruction." 956fc143580SKajol Jain }, 957fc143580SKajol Jain { 958fc143580SKajol Jain "EventCode": "0x000300000010C142", 959fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L2_ALL", 960fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction." 961fc143580SKajol Jain }, 962fc143580SKajol Jain { 963fc143580SKajol Jain "EventCode": "0x000340000020C142", 964fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L2_ALL", 965fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction." 966fc143580SKajol Jain }, 967fc143580SKajol Jain { 968fc143580SKajol Jain "EventCode": "0x003F00000000C142", 969fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L1MISS", 970fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction." 971fc143580SKajol Jain }, 972fc143580SKajol Jain { 973fc143580SKajol Jain "EventCode": "0x003F40000000C142", 974fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L1MISS", 975fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction." 976fc143580SKajol Jain }, 977fc143580SKajol Jain { 978fc143580SKajol Jain "EventCode": "0x003F00000010C142", 979fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L1MISS_ALL", 980fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction." 981fc143580SKajol Jain }, 982fc143580SKajol Jain { 983fc143580SKajol Jain "EventCode": "0x003F40000020C142", 984fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L1MISS_ALL", 985fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction." 986fc143580SKajol Jain }, 987fc143580SKajol Jain { 988fc143580SKajol Jain "EventCode": "0x000040000000C142", 989fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT", 990fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction." 991fc143580SKajol Jain }, 992fc143580SKajol Jain { 993fc143580SKajol Jain "EventCode": "0x000040000020C142", 994fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL", 995fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction." 996fc143580SKajol Jain }, 997fc143580SKajol Jain { 998fc143580SKajol Jain "EventCode": "0x004040000000C142", 999fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L2_MEPF", 1000fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction." 1001fc143580SKajol Jain }, 1002fc143580SKajol Jain { 1003fc143580SKajol Jain "EventCode": "0x004040000020C142", 1004fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L2_MEPF_ALL", 1005fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction." 1006fc143580SKajol Jain }, 1007fc143580SKajol Jain { 1008fc143580SKajol Jain "EventCode": "0x008040000000C142", 1009fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT", 1010fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction." 1011fc143580SKajol Jain }, 1012fc143580SKajol Jain { 1013fc143580SKajol Jain "EventCode": "0x008040000020C142", 1014fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL", 1015fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction." 1016fc143580SKajol Jain }, 1017fc143580SKajol Jain { 1018fc143580SKajol Jain "EventCode": "0x00C040000000C142", 1019fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L2_OTHER_CONFLICT", 1020fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction." 1021fc143580SKajol Jain }, 1022fc143580SKajol Jain { 1023fc143580SKajol Jain "EventCode": "0x00C040000020C142", 1024fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL", 1025fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction." 1026fc143580SKajol Jain }, 1027fc143580SKajol Jain { 1028fc143580SKajol Jain "EventCode": "0x000380000000C142", 1029fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L2MISS", 1030fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction." 1031fc143580SKajol Jain }, 1032fc143580SKajol Jain { 1033fc143580SKajol Jain "EventCode": "0x0003C0000000C142", 10349eef4101SAthira Rajeev "EventName": "PM_MRK_DATA_FROM_L2MISS_DSRC", 1035fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction." 1036fc143580SKajol Jain }, 1037fc143580SKajol Jain { 1038fc143580SKajol Jain "EventCode": "0x000380000010C142", 1039fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L2MISS_ALL", 1040fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction." 1041fc143580SKajol Jain }, 1042fc143580SKajol Jain { 1043fc143580SKajol Jain "EventCode": "0x0003C0000020C142", 1044fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L2MISS_ALL", 1045fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction." 1046fc143580SKajol Jain }, 1047fc143580SKajol Jain { 1048fc143580SKajol Jain "EventCode": "0x010300000000C142", 1049fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L3", 1050fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss for a marked instruction." 1051fc143580SKajol Jain }, 1052fc143580SKajol Jain { 1053fc143580SKajol Jain "EventCode": "0x010340000000C142", 1054fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L3", 1055fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction." 1056fc143580SKajol Jain }, 1057fc143580SKajol Jain { 1058fc143580SKajol Jain "EventCode": "0x010300000010C142", 1059fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L3_ALL", 1060fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction." 1061fc143580SKajol Jain }, 1062fc143580SKajol Jain { 1063fc143580SKajol Jain "EventCode": "0x010340000020C142", 1064fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L3_ALL", 1065fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction." 1066fc143580SKajol Jain }, 1067fc143580SKajol Jain { 1068fc143580SKajol Jain "EventCode": "0x010040000000C142", 1069fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT", 1070fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction." 1071fc143580SKajol Jain }, 1072fc143580SKajol Jain { 1073fc143580SKajol Jain "EventCode": "0x010040000020C142", 1074fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL", 1075fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction." 1076fc143580SKajol Jain }, 1077fc143580SKajol Jain { 1078fc143580SKajol Jain "EventCode": "0x014040000000C142", 1079fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L3_MEPF", 1080fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction." 1081fc143580SKajol Jain }, 1082fc143580SKajol Jain { 1083fc143580SKajol Jain "EventCode": "0x014040000020C142", 1084fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L3_MEPF_ALL", 1085fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction." 1086fc143580SKajol Jain }, 1087fc143580SKajol Jain { 1088fc143580SKajol Jain "EventCode": "0x01C040000000C142", 1089fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L3_CONFLICT", 1090fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction." 1091fc143580SKajol Jain }, 1092fc143580SKajol Jain { 1093fc143580SKajol Jain "EventCode": "0x01C040000020C142", 1094fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L3_CONFLICT_ALL", 1095fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction." 1096fc143580SKajol Jain }, 1097fc143580SKajol Jain { 1098fc143580SKajol Jain "EventCode": "0x000780000000C142", 10999eef4101SAthira Rajeev "EventName": "PM_MRK_INST_FROM_L3MISS_DSRC", 1100fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction." 1101fc143580SKajol Jain }, 1102fc143580SKajol Jain { 1103fc143580SKajol Jain "EventCode": "0x0007C0000000C142", 11049eef4101SAthira Rajeev "EventName": "PM_MRK_DATA_FROM_L3MISS_DSRC", 1105fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction." 1106fc143580SKajol Jain }, 1107fc143580SKajol Jain { 1108fc143580SKajol Jain "EventCode": "0x000780000010C142", 1109fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L3MISS_ALL", 1110fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction." 1111fc143580SKajol Jain }, 1112fc143580SKajol Jain { 1113fc143580SKajol Jain "EventCode": "0x0007C0000020C142", 1114fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L3MISS_ALL", 1115fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction." 1116fc143580SKajol Jain }, 1117fc143580SKajol Jain { 1118fc143580SKajol Jain "EventCode": "0x080040000000C142", 1119fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_REGENT_SHR", 1120fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction." 1121fc143580SKajol Jain }, 1122fc143580SKajol Jain { 1123fc143580SKajol Jain "EventCode": "0x080040000020C142", 1124fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL", 1125fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1126fc143580SKajol Jain }, 1127fc143580SKajol Jain { 1128fc143580SKajol Jain "EventCode": "0x084040000000C142", 1129fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_REGENT_MOD", 1130fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction." 1131fc143580SKajol Jain }, 1132fc143580SKajol Jain { 1133fc143580SKajol Jain "EventCode": "0x084040000020C142", 1134fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL", 1135fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1136fc143580SKajol Jain }, 1137fc143580SKajol Jain { 1138fc143580SKajol Jain "EventCode": "0x080100000000C142", 1139fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L21_REGENT", 1140fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction." 1141fc143580SKajol Jain }, 1142fc143580SKajol Jain { 1143fc143580SKajol Jain "EventCode": "0x080140000000C142", 1144fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_REGENT", 1145fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction." 1146fc143580SKajol Jain }, 1147fc143580SKajol Jain { 1148fc143580SKajol Jain "EventCode": "0x080100000010C142", 1149fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L21_REGENT_ALL", 1150fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1151fc143580SKajol Jain }, 1152fc143580SKajol Jain { 1153fc143580SKajol Jain "EventCode": "0x080140000020C142", 1154fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_REGENT_ALL", 1155fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1156fc143580SKajol Jain }, 1157fc143580SKajol Jain { 1158fc143580SKajol Jain "EventCode": "0x088040000000C142", 1159fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_REGENT_SHR", 1160fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction." 1161fc143580SKajol Jain }, 1162fc143580SKajol Jain { 1163fc143580SKajol Jain "EventCode": "0x088040000020C142", 1164fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL", 1165fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1166fc143580SKajol Jain }, 1167fc143580SKajol Jain { 1168fc143580SKajol Jain "EventCode": "0x08C040000000C142", 1169fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_REGENT_MOD", 1170fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction." 1171fc143580SKajol Jain }, 1172fc143580SKajol Jain { 1173fc143580SKajol Jain "EventCode": "0x08C040000020C142", 1174fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL", 1175fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1176fc143580SKajol Jain }, 1177fc143580SKajol Jain { 1178fc143580SKajol Jain "EventCode": "0x088100000000C142", 1179fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L31_REGENT", 1180fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction." 1181fc143580SKajol Jain }, 1182fc143580SKajol Jain { 1183fc143580SKajol Jain "EventCode": "0x088140000000C142", 1184fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_REGENT", 1185fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction." 1186fc143580SKajol Jain }, 1187fc143580SKajol Jain { 1188fc143580SKajol Jain "EventCode": "0x088100000010C142", 1189fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L31_REGENT_ALL", 1190fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1191fc143580SKajol Jain }, 1192fc143580SKajol Jain { 1193fc143580SKajol Jain "EventCode": "0x088140000020C142", 1194fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_REGENT_ALL", 1195fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1196fc143580SKajol Jain }, 1197fc143580SKajol Jain { 1198fc143580SKajol Jain "EventCode": "0x080240000000C142", 1199fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3_SHR", 1200fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction." 1201fc143580SKajol Jain }, 1202fc143580SKajol Jain { 1203fc143580SKajol Jain "EventCode": "0x080240000020C142", 1204fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL", 1205fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1206fc143580SKajol Jain }, 1207fc143580SKajol Jain { 1208fc143580SKajol Jain "EventCode": "0x084240000000C142", 1209fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3_MOD", 1210fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction." 1211fc143580SKajol Jain }, 1212fc143580SKajol Jain { 1213fc143580SKajol Jain "EventCode": "0x084240000020C142", 1214fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL", 1215fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1216fc143580SKajol Jain }, 1217fc143580SKajol Jain { 1218fc143580SKajol Jain "EventCode": "0x080300000000C142", 1219fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_REGENT_L2L3", 1220fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction." 1221fc143580SKajol Jain }, 1222fc143580SKajol Jain { 1223fc143580SKajol Jain "EventCode": "0x080340000000C142", 1224fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3", 1225fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction." 1226fc143580SKajol Jain }, 1227fc143580SKajol Jain { 1228fc143580SKajol Jain "EventCode": "0x080300000010C142", 1229fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_REGENT_L2L3_ALL", 1230fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1231fc143580SKajol Jain }, 1232fc143580SKajol Jain { 1233fc143580SKajol Jain "EventCode": "0x080340000020C142", 1234fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3_ALL", 1235fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction." 1236fc143580SKajol Jain }, 1237fc143580SKajol Jain { 1238fc143580SKajol Jain "EventCode": "0x0A0040000000C142", 1239fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT_SHR", 1240fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction." 1241fc143580SKajol Jain }, 1242fc143580SKajol Jain { 1243fc143580SKajol Jain "EventCode": "0x0A0040000020C142", 1244fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL", 1245fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 1246fc143580SKajol Jain }, 1247fc143580SKajol Jain { 1248fc143580SKajol Jain "EventCode": "0x0A4040000000C142", 1249fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT_MOD", 1250fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction." 1251fc143580SKajol Jain }, 1252fc143580SKajol Jain { 1253fc143580SKajol Jain "EventCode": "0x0A4040000020C142", 1254fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL", 1255fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 1256fc143580SKajol Jain }, 1257fc143580SKajol Jain { 1258fc143580SKajol Jain "EventCode": "0x0A0100000000C142", 1259fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L21_NON_REGENT", 1260fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction." 1261fc143580SKajol Jain }, 1262fc143580SKajol Jain { 1263fc143580SKajol Jain "EventCode": "0x0A0140000000C142", 1264fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT", 1265fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction." 1266fc143580SKajol Jain }, 1267fc143580SKajol Jain { 1268fc143580SKajol Jain "EventCode": "0x0A0100000010C142", 1269fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L21_NON_REGENT_ALL", 1270fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 1271fc143580SKajol Jain }, 1272fc143580SKajol Jain { 1273fc143580SKajol Jain "EventCode": "0x0A0140000020C142", 1274fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT_ALL", 1275fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 1276fc143580SKajol Jain }, 1277fc143580SKajol Jain { 1278fc143580SKajol Jain "EventCode": "0x0A8040000000C142", 1279fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT_SHR", 1280fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction." 1281fc143580SKajol Jain }, 1282fc143580SKajol Jain { 1283fc143580SKajol Jain "EventCode": "0x0A8040000020C142", 1284fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL", 1285fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 1286fc143580SKajol Jain }, 1287fc143580SKajol Jain { 1288fc143580SKajol Jain "EventCode": "0x0AC040000000C142", 1289fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT_MOD", 1290fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction." 1291fc143580SKajol Jain }, 1292fc143580SKajol Jain { 1293fc143580SKajol Jain "EventCode": "0x0AC040000020C142", 1294fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL", 1295fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 1296fc143580SKajol Jain }, 1297fc143580SKajol Jain { 1298fc143580SKajol Jain "EventCode": "0x0A8100000000C142", 1299fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L31_NON_REGENT", 1300fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction." 1301fc143580SKajol Jain }, 1302fc143580SKajol Jain { 1303fc143580SKajol Jain "EventCode": "0x0A8140000000C142", 1304fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT", 1305fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction." 1306fc143580SKajol Jain }, 1307fc143580SKajol Jain { 1308fc143580SKajol Jain "EventCode": "0x0A8100000010C142", 1309fc143580SKajol Jain "EventName": "PM_MRK_INST_FROM_L31_NON_REGENT_ALL", 1310fc143580SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 1311fc143580SKajol Jain }, 1312fc143580SKajol Jain { 1313fc143580SKajol Jain "EventCode": "0x0A8140000020C142", 1314fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT_ALL", 1315fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 1316fc143580SKajol Jain }, 1317fc143580SKajol Jain { 1318fc143580SKajol Jain "EventCode": "0x0A0240000000C142", 1319fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR", 1320fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction." 1321fc143580SKajol Jain }, 1322fc143580SKajol Jain { 1323fc143580SKajol Jain "EventCode": "0x0A0240000020C142", 1324fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL", 1325fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 1326fc143580SKajol Jain }, 1327fc143580SKajol Jain { 1328fc143580SKajol Jain "EventCode": "0x0A4240000000C142", 1329fc143580SKajol Jain "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD", 1330fc143580SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction." 133123ba30b2SKajol Jain }, 133223ba30b2SKajol Jain { 133323ba30b2SKajol Jain "EventCode": "0x0A4240000020C142", 133423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL", 133523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 133623ba30b2SKajol Jain }, 133723ba30b2SKajol Jain { 133823ba30b2SKajol Jain "EventCode": "0x0A0300000000C142", 133923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_NON_REGENT_L2L3", 134023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction." 134123ba30b2SKajol Jain }, 134223ba30b2SKajol Jain { 134323ba30b2SKajol Jain "EventCode": "0x0A0340000000C142", 134423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3", 134523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction." 134623ba30b2SKajol Jain }, 134723ba30b2SKajol Jain { 134823ba30b2SKajol Jain "EventCode": "0x0A0300000010C142", 134923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL", 135023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 135123ba30b2SKajol Jain }, 135223ba30b2SKajol Jain { 135323ba30b2SKajol Jain "EventCode": "0x0A0340000020C142", 135423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL", 135523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction." 135623ba30b2SKajol Jain }, 135723ba30b2SKajol Jain { 135823ba30b2SKajol Jain "EventCode": "0x094100000000C142", 135923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_LMEM", 136023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory due to a demand miss for a marked instruction." 136123ba30b2SKajol Jain }, 136223ba30b2SKajol Jain { 136323ba30b2SKajol Jain "EventCode": "0x094040000000C142", 136423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_LMEM", 136523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss for a marked instruction." 136623ba30b2SKajol Jain }, 136723ba30b2SKajol Jain { 136823ba30b2SKajol Jain "EventCode": "0x094100000010C142", 136923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_LMEM_ALL", 137023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction." 137123ba30b2SKajol Jain }, 137223ba30b2SKajol Jain { 137323ba30b2SKajol Jain "EventCode": "0x094040000020C142", 137423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_LMEM_ALL", 137523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction." 137623ba30b2SKajol Jain }, 137723ba30b2SKajol Jain { 137823ba30b2SKajol Jain "EventCode": "0x098040000000C142", 137923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_L_OC_CACHE", 138023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss for a marked instruction." 138123ba30b2SKajol Jain }, 138223ba30b2SKajol Jain { 138323ba30b2SKajol Jain "EventCode": "0x098040000020C142", 138423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_L_OC_CACHE_ALL", 138523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss or prefetch reload for a marked instruction." 138623ba30b2SKajol Jain }, 138723ba30b2SKajol Jain { 138823ba30b2SKajol Jain "EventCode": "0x09C040000000C142", 138923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_L_OC_MEM", 139023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss for a marked instruction." 139123ba30b2SKajol Jain }, 139223ba30b2SKajol Jain { 139323ba30b2SKajol Jain "EventCode": "0x09C040000020C142", 139423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_L_OC_MEM_ALL", 139523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss or prefetch reload for a marked instruction." 139623ba30b2SKajol Jain }, 139723ba30b2SKajol Jain { 139823ba30b2SKajol Jain "EventCode": "0x098100000000C142", 139923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_L_OC_ANY", 140023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss for a marked instruction." 140123ba30b2SKajol Jain }, 140223ba30b2SKajol Jain { 140323ba30b2SKajol Jain "EventCode": "0x098140000000C142", 140423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_L_OC_ANY", 140523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss for a marked instruction." 140623ba30b2SKajol Jain }, 140723ba30b2SKajol Jain { 140823ba30b2SKajol Jain "EventCode": "0x098100000010C142", 140923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_L_OC_ANY_ALL", 141023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction." 141123ba30b2SKajol Jain }, 141223ba30b2SKajol Jain { 141323ba30b2SKajol Jain "EventCode": "0x098140000020C142", 141423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_L_OC_ANY_ALL", 141523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction." 141623ba30b2SKajol Jain }, 141723ba30b2SKajol Jain { 141823ba30b2SKajol Jain "EventCode": "0x0C0040000000C142", 141923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2_SHR", 142023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction." 142123ba30b2SKajol Jain }, 142223ba30b2SKajol Jain { 142323ba30b2SKajol Jain "EventCode": "0x0C0040000020C142", 142423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2_SHR_ALL", 142523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 142623ba30b2SKajol Jain }, 142723ba30b2SKajol Jain { 142823ba30b2SKajol Jain "EventCode": "0x0C4040000000C142", 142923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2_MOD", 143023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction." 143123ba30b2SKajol Jain }, 143223ba30b2SKajol Jain { 143323ba30b2SKajol Jain "EventCode": "0x0C4040000020C142", 143423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2_MOD_ALL", 143523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 143623ba30b2SKajol Jain }, 143723ba30b2SKajol Jain { 143823ba30b2SKajol Jain "EventCode": "0x0C0100000000C142", 143923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_RL2", 144023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction." 144123ba30b2SKajol Jain }, 144223ba30b2SKajol Jain { 144323ba30b2SKajol Jain "EventCode": "0x0C0140000000C142", 144423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2", 144523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction." 144623ba30b2SKajol Jain }, 144723ba30b2SKajol Jain { 144823ba30b2SKajol Jain "EventCode": "0x0C0100000010C142", 144923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_RL2_ALL", 145023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 145123ba30b2SKajol Jain }, 145223ba30b2SKajol Jain { 145323ba30b2SKajol Jain "EventCode": "0x0C0140000020C142", 145423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2_ALL", 145523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 145623ba30b2SKajol Jain }, 145723ba30b2SKajol Jain { 145823ba30b2SKajol Jain "EventCode": "0x0C8040000000C142", 145923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL3_SHR", 146023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction." 146123ba30b2SKajol Jain }, 146223ba30b2SKajol Jain { 146323ba30b2SKajol Jain "EventCode": "0x0C8040000020C142", 146423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL3_SHR_ALL", 146523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 146623ba30b2SKajol Jain }, 146723ba30b2SKajol Jain { 146823ba30b2SKajol Jain "EventCode": "0x0CC040000000C142", 146923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL3_MOD", 147023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction." 147123ba30b2SKajol Jain }, 147223ba30b2SKajol Jain { 147323ba30b2SKajol Jain "EventCode": "0x0CC040000020C142", 147423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL3_MOD_ALL", 147523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 147623ba30b2SKajol Jain }, 147723ba30b2SKajol Jain { 147823ba30b2SKajol Jain "EventCode": "0x0C8100000000C142", 147923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_RL3", 148023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction." 148123ba30b2SKajol Jain }, 148223ba30b2SKajol Jain { 148323ba30b2SKajol Jain "EventCode": "0x0C8140000000C142", 148423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL3", 148523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction." 148623ba30b2SKajol Jain }, 148723ba30b2SKajol Jain { 148823ba30b2SKajol Jain "EventCode": "0x0C8100000010C142", 148923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_RL3_ALL", 149023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 149123ba30b2SKajol Jain }, 149223ba30b2SKajol Jain { 149323ba30b2SKajol Jain "EventCode": "0x0C8140000020C142", 149423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL3_ALL", 149523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 149623ba30b2SKajol Jain }, 149723ba30b2SKajol Jain { 149823ba30b2SKajol Jain "EventCode": "0x0C0240000000C142", 149923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR", 150023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction." 150123ba30b2SKajol Jain }, 150223ba30b2SKajol Jain { 150323ba30b2SKajol Jain "EventCode": "0x0C0240000020C142", 150423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_ALL", 150523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 150623ba30b2SKajol Jain }, 150723ba30b2SKajol Jain { 150823ba30b2SKajol Jain "EventCode": "0x0C4240000000C142", 150923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD", 151023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction." 151123ba30b2SKajol Jain }, 151223ba30b2SKajol Jain { 151323ba30b2SKajol Jain "EventCode": "0x0C4240000020C142", 151423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_ALL", 151523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 151623ba30b2SKajol Jain }, 151723ba30b2SKajol Jain { 151823ba30b2SKajol Jain "EventCode": "0x0C0300000000C142", 151923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_RL2L3", 152023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction." 152123ba30b2SKajol Jain }, 152223ba30b2SKajol Jain { 152323ba30b2SKajol Jain "EventCode": "0x0C0340000000C142", 152423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2L3", 152523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction." 152623ba30b2SKajol Jain }, 152723ba30b2SKajol Jain { 152823ba30b2SKajol Jain "EventCode": "0x0C0300000010C142", 152923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_RL2L3_ALL", 153023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 153123ba30b2SKajol Jain }, 153223ba30b2SKajol Jain { 153323ba30b2SKajol Jain "EventCode": "0x0C0340000020C142", 153423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RL2L3_ALL", 153523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction." 153623ba30b2SKajol Jain }, 153723ba30b2SKajol Jain { 153823ba30b2SKajol Jain "EventCode": "0x0D4100000000C142", 153923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_RMEM", 154023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction." 154123ba30b2SKajol Jain }, 154223ba30b2SKajol Jain { 154323ba30b2SKajol Jain "EventCode": "0x0D4040000000C142", 154423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RMEM", 154523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction." 154623ba30b2SKajol Jain }, 154723ba30b2SKajol Jain { 154823ba30b2SKajol Jain "EventCode": "0x0D4100000010C142", 154923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_RMEM_ALL", 155023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction." 155123ba30b2SKajol Jain }, 155223ba30b2SKajol Jain { 155323ba30b2SKajol Jain "EventCode": "0x0D4040000020C142", 155423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_RMEM_ALL", 155523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction." 155623ba30b2SKajol Jain }, 155723ba30b2SKajol Jain { 155823ba30b2SKajol Jain "EventCode": "0x0D8040000000C142", 155923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_R_OC_CACHE", 156023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss for a marked instruction." 156123ba30b2SKajol Jain }, 156223ba30b2SKajol Jain { 156323ba30b2SKajol Jain "EventCode": "0x0D8040000020C142", 156423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_R_OC_CACHE_ALL", 156523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss or prefetch reload for a marked instruction." 156623ba30b2SKajol Jain }, 156723ba30b2SKajol Jain { 156823ba30b2SKajol Jain "EventCode": "0x0DC040000000C142", 156923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_R_OC_MEM", 157023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss for a marked instruction." 157123ba30b2SKajol Jain }, 157223ba30b2SKajol Jain { 157323ba30b2SKajol Jain "EventCode": "0x0DC040000020C142", 157423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_R_OC_MEM_ALL", 157523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss or prefetch reload for a marked instruction." 157623ba30b2SKajol Jain }, 157723ba30b2SKajol Jain { 157823ba30b2SKajol Jain "EventCode": "0x0D8100000000C142", 157923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_R_OC_ANY", 158023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss for a marked instruction." 158123ba30b2SKajol Jain }, 158223ba30b2SKajol Jain { 158323ba30b2SKajol Jain "EventCode": "0x0D8140000000C142", 158423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_R_OC_ANY", 158523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss for a marked instruction." 158623ba30b2SKajol Jain }, 158723ba30b2SKajol Jain { 158823ba30b2SKajol Jain "EventCode": "0x0D8100000010C142", 158923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_R_OC_ANY_ALL", 159023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction." 159123ba30b2SKajol Jain }, 159223ba30b2SKajol Jain { 159323ba30b2SKajol Jain "EventCode": "0x0D8140000020C142", 159423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_R_OC_ANY_ALL", 159523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction." 159623ba30b2SKajol Jain }, 159723ba30b2SKajol Jain { 159823ba30b2SKajol Jain "EventCode": "0x0E0040000000C142", 159923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2_SHR", 160023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction." 160123ba30b2SKajol Jain }, 160223ba30b2SKajol Jain { 160323ba30b2SKajol Jain "EventCode": "0x0E0040000020C142", 160423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2_SHR_ALL", 160523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 160623ba30b2SKajol Jain }, 160723ba30b2SKajol Jain { 160823ba30b2SKajol Jain "EventCode": "0x0E4040000000C142", 160923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2_MOD", 161023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction." 161123ba30b2SKajol Jain }, 161223ba30b2SKajol Jain { 161323ba30b2SKajol Jain "EventCode": "0x0E4040000020C142", 161423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2_MOD_ALL", 161523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 161623ba30b2SKajol Jain }, 161723ba30b2SKajol Jain { 161823ba30b2SKajol Jain "EventCode": "0x0E0100000000C142", 161923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_DL2", 162023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction." 162123ba30b2SKajol Jain }, 162223ba30b2SKajol Jain { 162323ba30b2SKajol Jain "EventCode": "0x0E0140000000C142", 162423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2", 162523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction." 162623ba30b2SKajol Jain }, 162723ba30b2SKajol Jain { 162823ba30b2SKajol Jain "EventCode": "0x0E0100000010C142", 162923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_DL2_ALL", 163023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 163123ba30b2SKajol Jain }, 163223ba30b2SKajol Jain { 163323ba30b2SKajol Jain "EventCode": "0x0E0140000020C142", 163423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2_ALL", 163523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 163623ba30b2SKajol Jain }, 163723ba30b2SKajol Jain { 163823ba30b2SKajol Jain "EventCode": "0x0E8040000000C142", 163923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL3_SHR", 164023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction." 164123ba30b2SKajol Jain }, 164223ba30b2SKajol Jain { 164323ba30b2SKajol Jain "EventCode": "0x0E8040000020C142", 164423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL3_SHR_ALL", 164523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 164623ba30b2SKajol Jain }, 164723ba30b2SKajol Jain { 164823ba30b2SKajol Jain "EventCode": "0x0EC040000000C142", 164923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL3_MOD", 165023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction." 165123ba30b2SKajol Jain }, 165223ba30b2SKajol Jain { 165323ba30b2SKajol Jain "EventCode": "0x0EC040000020C142", 165423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL3_MOD_ALL", 165523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 165623ba30b2SKajol Jain }, 165723ba30b2SKajol Jain { 165823ba30b2SKajol Jain "EventCode": "0x0E8100000000C142", 165923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_DL3", 166023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction." 166123ba30b2SKajol Jain }, 166223ba30b2SKajol Jain { 166323ba30b2SKajol Jain "EventCode": "0x0E8140000000C142", 166423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL3", 166523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction." 166623ba30b2SKajol Jain }, 166723ba30b2SKajol Jain { 166823ba30b2SKajol Jain "EventCode": "0x0E8100000010C142", 166923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_DL3_ALL", 167023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 167123ba30b2SKajol Jain }, 167223ba30b2SKajol Jain { 167323ba30b2SKajol Jain "EventCode": "0x0E8140000020C142", 167423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL3_ALL", 167523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 167623ba30b2SKajol Jain }, 167723ba30b2SKajol Jain { 167823ba30b2SKajol Jain "EventCode": "0x0E0240000000C142", 167923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR", 168023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction." 168123ba30b2SKajol Jain }, 168223ba30b2SKajol Jain { 168323ba30b2SKajol Jain "EventCode": "0x0E0240000020C142", 168423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR_ALL", 168523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 168623ba30b2SKajol Jain }, 168723ba30b2SKajol Jain { 168823ba30b2SKajol Jain "EventCode": "0x0E4240000000C142", 168923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD", 169023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction." 169123ba30b2SKajol Jain }, 169223ba30b2SKajol Jain { 169323ba30b2SKajol Jain "EventCode": "0x0E4240000020C142", 169423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD_ALL", 169523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 169623ba30b2SKajol Jain }, 169723ba30b2SKajol Jain { 169823ba30b2SKajol Jain "EventCode": "0x0E0300000000C142", 169923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_DL2L3", 170023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction." 170123ba30b2SKajol Jain }, 170223ba30b2SKajol Jain { 170323ba30b2SKajol Jain "EventCode": "0x0E0340000000C142", 170423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2L3", 170523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction." 170623ba30b2SKajol Jain }, 170723ba30b2SKajol Jain { 170823ba30b2SKajol Jain "EventCode": "0x0E0300000010C142", 170923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_DL2L3_ALL", 171023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 171123ba30b2SKajol Jain }, 171223ba30b2SKajol Jain { 171323ba30b2SKajol Jain "EventCode": "0x0E0340000020C142", 171423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DL2L3_ALL", 171523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction." 171623ba30b2SKajol Jain }, 171723ba30b2SKajol Jain { 171823ba30b2SKajol Jain "EventCode": "0x0F4100000000C142", 171923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_DMEM", 172023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction." 172123ba30b2SKajol Jain }, 172223ba30b2SKajol Jain { 172323ba30b2SKajol Jain "EventCode": "0x0F4040000000C142", 172423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DMEM", 172523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction." 172623ba30b2SKajol Jain }, 172723ba30b2SKajol Jain { 172823ba30b2SKajol Jain "EventCode": "0x0F4100000010C142", 172923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_DMEM_ALL", 173023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction." 173123ba30b2SKajol Jain }, 173223ba30b2SKajol Jain { 173323ba30b2SKajol Jain "EventCode": "0x0F4040000020C142", 173423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_DMEM_ALL", 173523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction." 173623ba30b2SKajol Jain }, 173723ba30b2SKajol Jain { 173823ba30b2SKajol Jain "EventCode": "0x0F8040000000C142", 173923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_D_OC_CACHE", 174023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss for a marked instruction." 174123ba30b2SKajol Jain }, 174223ba30b2SKajol Jain { 174323ba30b2SKajol Jain "EventCode": "0x0F8040000020C142", 174423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_D_OC_CACHE_ALL", 174523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss or prefetch reload for a marked instruction." 174623ba30b2SKajol Jain }, 174723ba30b2SKajol Jain { 174823ba30b2SKajol Jain "EventCode": "0x0FC040000000C142", 174923ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_D_OC_MEM", 175023ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss for a marked instruction." 175123ba30b2SKajol Jain }, 175223ba30b2SKajol Jain { 175323ba30b2SKajol Jain "EventCode": "0x0FC040000020C142", 175423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_D_OC_MEM_ALL", 175523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss or prefetch reload for a marked instruction." 175623ba30b2SKajol Jain }, 175723ba30b2SKajol Jain { 175823ba30b2SKajol Jain "EventCode": "0x0F8100000000C142", 175923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_D_OC_ANY", 176023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss for a marked instruction." 176123ba30b2SKajol Jain }, 176223ba30b2SKajol Jain { 176323ba30b2SKajol Jain "EventCode": "0x0F8140000000C142", 176423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_D_OC_ANY", 176523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss for a marked instruction." 176623ba30b2SKajol Jain }, 176723ba30b2SKajol Jain { 176823ba30b2SKajol Jain "EventCode": "0x0F8100000010C142", 176923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_D_OC_ANY_ALL", 177023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction." 177123ba30b2SKajol Jain }, 177223ba30b2SKajol Jain { 177323ba30b2SKajol Jain "EventCode": "0x0F8140000020C142", 177423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_D_OC_ANY_ALL", 177523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction." 177623ba30b2SKajol Jain }, 177723ba30b2SKajol Jain { 177823ba30b2SKajol Jain "EventCode": "0x080B00000000C142", 177923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_ONCHIP_CACHE", 178023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction." 178123ba30b2SKajol Jain }, 178223ba30b2SKajol Jain { 178323ba30b2SKajol Jain "EventCode": "0x080B40000000C142", 178423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_ONCHIP_CACHE", 178523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction." 178623ba30b2SKajol Jain }, 178723ba30b2SKajol Jain { 178823ba30b2SKajol Jain "EventCode": "0x080B00000010C142", 178923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_ONCHIP_CACHE_ALL", 179023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction." 179123ba30b2SKajol Jain }, 179223ba30b2SKajol Jain { 179323ba30b2SKajol Jain "EventCode": "0x080B40000020C142", 179423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL", 179523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction." 179623ba30b2SKajol Jain }, 179723ba30b2SKajol Jain { 179823ba30b2SKajol Jain "EventCode": "0x0C0B00000000C142", 179923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_OFFCHIP_CACHE", 180023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction." 180123ba30b2SKajol Jain }, 180223ba30b2SKajol Jain { 180323ba30b2SKajol Jain "EventCode": "0x0C0B40000000C142", 180423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_OFFCHIP_CACHE", 180523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction." 180623ba30b2SKajol Jain }, 180723ba30b2SKajol Jain { 180823ba30b2SKajol Jain "EventCode": "0x0C0B00000010C142", 180923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL", 181023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction." 181123ba30b2SKajol Jain }, 181223ba30b2SKajol Jain { 181323ba30b2SKajol Jain "EventCode": "0x0C0B40000020C142", 181423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL", 181523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction." 181623ba30b2SKajol Jain }, 181723ba30b2SKajol Jain { 181823ba30b2SKajol Jain "EventCode": "0x095900000000C142", 181923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_ANY_MEMORY", 182023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction." 182123ba30b2SKajol Jain }, 182223ba30b2SKajol Jain { 182323ba30b2SKajol Jain "EventCode": "0x095840000000C142", 182423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_ANY_MEMORY", 182523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction." 182623ba30b2SKajol Jain }, 182723ba30b2SKajol Jain { 182823ba30b2SKajol Jain "EventCode": "0x095900000010C142", 182923ba30b2SKajol Jain "EventName": "PM_MRK_INST_FROM_ANY_MEMORY_ALL", 183023ba30b2SKajol Jain "BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction." 183123ba30b2SKajol Jain }, 183223ba30b2SKajol Jain { 183323ba30b2SKajol Jain "EventCode": "0x095840000020C142", 183423ba30b2SKajol Jain "EventName": "PM_MRK_DATA_FROM_ANY_MEMORY_ALL", 183523ba30b2SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction." 1836fc143580SKajol Jain } 1837fc143580SKajol Jain] 1838