no\-divider (full) in projects: freebsd

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Searched +full:no +full:- +full:divider (Results 1 – 25 of 215) sorted by relevance

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/freebsd/sys/dev/clk/
H A D	clk_div.c	1 /- 17 ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 66 uint32_t divider; /* in natural form / member 82 clknode_div_table_get_divider(struct clknode_div_sc sc, uint32_t divider) in clknode_div_table_get_divider() argument 86 if (!(sc->div_flags & CLK_DIV_WITH_TABLE)) in clknode_div_table_get_divider() 87 return (divider); in clknode_div_table_get_divider() 89 for (table = sc->div_table; table->divider != 0; table++) in clknode_div_table_get_divider() 90 if (table->value == sc->divider) in clknode_div_table_get_divider() 91 return (table->divider); in clknode_div_table_get_divider() 97 clknode_div_table_get_value(struct clknode_div_sc sc, uint32_t divider) in clknode_div_table_get_value() argument [all …]
H A D	clk_div.h	`1 /- 17 ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 32 #define CLK_DIV_ZERO_BASED 0x0001 /* Zero based divider. / 37 uint32_t divider; member 42 uint32_t offset; / Divider register offset / 46 uint32_t f_width; / set to 0 for int divider / 47 int div_flags; / Divider-specific flags / 48 struct clk_div_table div_table; /* Divider table */`
H A D	clk_fixed.h	`1 /- 17 ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 33 * A fixed clock can represent several different real-world objects, including 34 * an oscillator with a fixed output frequency, a fixed divider (multiplier and 35 * divisor must both be > 0), or a phase-fractional divider within a PLL`
/freebsd/sys/arm64/qoriq/clk/
H A D	ls1028a_flexspi_clk.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 62 { .value = 0, .divider = 1, }, 63 { .value = 1, .divider = 2, }, 64 { .value = 2, .divider = 3, }, 65 { .value = 3, .divider = 4, }, 66 { .value = 4, .divider = 5, }, 67 { .value = 5, .divider = 6, }, 68 { .value = 6, .divider = 7, }, [all …]`
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A D	omap44xx-clocks.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-output-names = "extalt_clkin_ck"; 12 clock-frequency = <59000000>; 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 clock-output-names = "pad_clks_src_ck"; 19 clock-frequency = <12000000>; 23 #clock-cells = <0>; [all …]`
H A D	omap54xx-clocks.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-output-names = "pad_clks_src_ck"; 12 clock-frequency = <12000000>; 16 #clock-cells = <0>; 17 compatible = "ti,gate-clock"; 18 clock-output-names = "pad_clks_ck"; 20 ti,bit-shift = <8>; 25 #clock-cells = <0>; [all …]`
H A D	am33xx-clocks.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only 8 sys_clkin_ck: clock-sys-clkin-22@40 { 9 #clock-cells = <0>; 10 compatible = "ti,mux-clock"; 11 clock-output-names = "sys_clkin_ck"; 13 ti,bit-shift = <22>; 17 adc_tsc_fck: clock-adc-tsc-fck { 18 #clock-cells = <0>; 19 compatible = "fixed-factor-clock"; 20 clock-output-names = "adc_tsc_fck"; [all …]`
H A D	omap3430es1-clocks.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "ti,wait-gate-clock"; 13 ti,bit-shift = <0>; 17 #clock-cells = <0>; 18 compatible = "ti,divider-clock"; 20 ti,max-div = <7>; 22 ti,index-starts-at-one; 26 #clock-cells = <0>; 27 compatible = "fixed-factor-clock"; [all …]`
/freebsd/sys/arm/mv/clk/
H A D	a37x0_nb_periph_clk_driver.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 { .value = 1, .divider = 1 }, 51 { .value = 2, .divider = 2 }, 52 { .value = 3, .divider = 3 }, 53 { .value = 4, .divider = 4 }, 54 { .value = 5, .divider = 5 }, 55 { .value = 6, .divider = 6 }, 56 { .value = 0, .divider = 0 } [all …]`
H A D	periph_clk_d.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 53 * Register chain: mux (select proper TBG) -> div1 (first frequency divider) -> 54 * div2 (second frequency divider) -> mux (select divided freq. 55 * or xtal output) -> gate (enable or disable clock), which is also final node 70 dev_id = device_def->common_def.device_id; in a37x0_periph_d_register_full_clk_dd() 71 tbg_mux = &device_def->clk_def.full_dd.tbg_mux; in a37x0_periph_d_register_full_clk_dd() 72 div1 = &device_def->clk_def.full_dd.div1; in a37x0_periph_d_register_full_clk_dd() 73 div2 = &device_def->clk_def.full_dd.div2; in a37x0_periph_d_register_full_clk_dd() [all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A D	imx53-usbarmory.dts	`8 * This file is dual-licensed: you can use it either under the terms 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 47 /dts-v1/; 52 compatible = "inversepath,imx53-usbarmory", "fsl,imx53"; 57 stdout-path = &uart1; 66 compatible = "gpio-leds"; 67 pinctrl-names = "default"; 68 pinctrl-0 = <&pinctrl_led>; 70 led-user { 73 linux,default-trigger = "heartbeat"; [all …]`
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A D	exynos-dw-mshc.txt	7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific 13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210 15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412 17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7 23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 25 - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific 28 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface 30 ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. [all …]
/freebsd/usr.bin/sdiff/
H A D	sdiff.c	`68 static size_t line_width; /* width of a line (two columns and divider) / 91 { "suppress-common-lines", no_argument, NULL, 's' }, 95 { "diff-program", required_argument, NULL, DIFFPROG_OPT }, 98 { "ignore-file-name-case", no_argument, NULL, FCASE_IGNORE_OPT }, 99 { "no-ignore-fil 640 println(const char s1,const char divider,const char * s2) println() argument 892 enqueue(char * left,char divider,char * right) enqueue() argument [all...]`
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A D	nxp,sysctr-timer.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bai Ping <ping.bai@nxp.com> 22 - nxp,imx95-sysctr-timer 23 - nxp,sysctr-timer 34 clock-names: 37 nxp,no-divider: 38 description: if present, means there is no internal base clk divider. [all …]`
/freebsd/sys/dev/clk/rockchip/
H A D	rk_cru.h	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 /* Fixed factor multipier/divider. / 123 / Fractional rate multipier/divider. / 157 / Composite clock without mux (divider only). / 174 / Complex clock without divider (multiplexer only). / 194 / Complex clock without divider (multiplexer only in GRF). */`
/freebsd/sys/arm/nvidia/tegra124/
H A D	tegra124_clk_per.c	`1 /- 17 ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 38 #include <dt-bindings/clock/tegra124-car.h> 213 /* bank L -> 0-31 / 241 / bank H -> 32-63 / 270 / bank U -> 64-95 / 299 / bank V -> 96-127 / 325 / bank W -> 128-159/ 354 / bank X -> 160-191/ 374 #define DCF_HAVE_DIV 0x0400 / Block with divider */ [all …]`
/freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/
H A D	azoteq,iqs7211.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Jeff LaBundy <jeff@labundy.com> 13 The Azoteq IQS7210A, IQS7211A and IQS7211E trackpad and touchscreen control- 14 lers employ projected-capacitance sensing and can track two contacts. 21 - azoteq,iqs7210a 22 - azoteq,iqs7211a 23 - azoteq,iqs7211e 28 irq-gpios: [all …]`
/freebsd/sys/contrib/ncsw/Peripherals/FM/MAC/
H A D	fman_dtsec_mii_acc.c	2 * Copyright 2008-2013 Freescale Semiconductor Inc. 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 39 * dtsec_mii_get_div() - calculates the value of the dtsec mii divider 42 * This function calculates the dtsec mii clock divider that determines 46 * implicitly determines the divider value. 50 * shows the relations among dtsec_freq, MgmtClk, actual divider 84 iowrite32be(ioread32be(&regs->miimcfg) \| MIIMCFG_RESET_MGMT, in fman_dtsec_mii_reset() 85 &regs->miimcfg); in fman_dtsec_mii_reset() 86 iowrite32be(ioread32be(&regs->miimcfg) & ~MIIMCFG_RESET_MGMT, in fman_dtsec_mii_reset() 87 &regs->miimcfg); in fman_dtsec_mii_reset() [all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A D	tegra210_clk_per.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 39 #include <dt-bindings/clock/tegra210-car.h> 40 #include <dt-bindings/reset/tegra210-car.h> 308 /* bank L -> 0-31 / 332 / bank H -> 32-63 / 353 / bank U -> 64-95 / 378 / bank V -> 96-127 / 398 / bank W -> 128-159*/ [all …]`
H A D	tegra210_clk_pll.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 42 #include <dt-bindings/clock/tegra210-car.h> 71 #define PLL_FLAG_PDIV_POWER2 0x01 /* P Divider is 2^n / 113 / Post divider <-> register value mapping. / 115 uint32_t divider; / real divider / member 164 / Fractional divider (7.1) for PLL branch. / 179 / P divider (2^n). for PLL branch. / 192 / P divider (2^n). for PLL branch. */ [all …]`
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A D	baikal,bt1-ccu-div.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Baikal-T1 Clock Control Unit Dividers 11 - Serge Semin <fancer.lancer@gmail.com> 14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller 18 IP-blocks or to groups of blocks (clock domains). The transformation is done 19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The 21 individually reset by using the domain clocks divider configuration [all …]
H A D	baikal,bt1-ccu-pll.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/clock/baikal,bt1-cc [all...]`
/freebsd/sys/arm/ti/clk/
H A D	ti_divider_clock.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * Documentation/devicetree/bindings/clock/ti/divider.txt 74 { "ti,divider-clock", TI_DIVIDER_CLOCK }, 75 { "ti,composite-divider-clock", TI_COMPOSITE_DIVIDER_CLOCK }, 83 sc->clkdom = clkdom_create(sc->sc_dev); in register_clk() 84 if (sc->clkdom == NULL) { in register_clk() 85 DPRINTF(sc->sc_dev, "Failed to create clkdom\n"); in register_clk() 89 err = clknode_div_register(sc->clkdom, &sc->div_def); in register_clk() [all …]
/freebsd/sys/dev/iicbus/controller/vybrid/
H A D	vf_i2c.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 5 * Copyright (c) 2024 Pierre-Luc Drouin <pldrouin@pldrouin.net> 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 30 * Vybrid Family Inter-Integrated Circuit (I2C) 63 #define I2C_IBFD 0x1 /* I2C Bus Frequency Divider Register / 66 #define IBCR_IBIE (1 << 6) / I-Bus Interrupt Enable. / 78 #define IBSR_IBIF (1 << 1) / I-Bus Interrupt Flag. */ 87 #define READ1(_sc, _reg) bus_space_read_1(_sc->bst, _sc->bsh, _reg) 88 #define WRITE1(_sc, _reg, _val) bus_space_write_1(_sc->bst,\ [all …]
/freebsd/sys/arm/freescale/vybrid/
H A D	vf_ccm.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com> 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 61 #define CCM_CSCDR1 0x14 /* Serial Clock Divider Register 1 / 62 #define CCM_CSCDR2 0x18 / Serial Clock Divider Register 2 / 63 #define CCM_CSCDR3 0x1C / Serial Clock Divider Register 3 */ 178 PLL4 clock divider (before switching the clocks should be gated) 298 Divider to generate ESAI clock 346 { -1, 0 } [all …]

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