1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
53  * Register chain: mux (select proper TBG) -> div1 (first frequency divider) ->
54  * div2 (second frequency divider) -> mux (select divided freq.
55  * or xtal output) -> gate (enable or disable clock), which is also final node
70 	dev_id = device_def->common_def.device_id;  in a37x0_periph_d_register_full_clk_dd()
71 	tbg_mux = &device_def->clk_def.full_dd.tbg_mux;  in a37x0_periph_d_register_full_clk_dd()
72 	div1 = &device_def->clk_def.full_dd.div1;  in a37x0_periph_d_register_full_clk_dd()
73 	div2 = &device_def->clk_def.full_dd.div2;  in a37x0_periph_d_register_full_clk_dd()
74 	gate = &device_def->clk_def.full_dd.gate;  in a37x0_periph_d_register_full_clk_dd()
75 	clk_mux = &device_def->clk_def.full_dd.clk_mux;  in a37x0_periph_d_register_full_clk_dd()
77 	a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs,  in a37x0_periph_d_register_full_clk_dd()
78 	    device_def->common_def.tbg_cnt);  in a37x0_periph_d_register_full_clk_dd()
85 	a37x0_periph_set_props(&div1->clkdef, &tbg_mux->clkdef.name, 1);  in a37x0_periph_d_register_full_clk_dd()
91 	a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1);  in a37x0_periph_d_register_full_clk_dd()
97 	parent_names[0] = device_def->common_def.xtal;  in a37x0_periph_d_register_full_clk_dd()
98 	parent_names[1] = div2->clkdef.name;  in a37x0_periph_d_register_full_clk_dd()
100 	a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT);  in a37x0_periph_d_register_full_clk_dd()
106 	a37x0_periph_set_props(&gate->clkdef, &clk_mux->clkdef.name, 1);  in a37x0_periph_d_register_full_clk_dd()
118  * Register chain: mux (select proper TBG) -> div1 (first frequency divider) ->
119  * mux (select divided freq. or xtal output) -> gate (enable or disable clock),
134 	dev_id = device_def->common_def.device_id;  in a37x0_periph_d_register_full_clk()
135 	tbg_mux = &device_def->clk_def.full_d.tbg_mux;  in a37x0_periph_d_register_full_clk()
136 	div = &device_def->clk_def.full_d.div;  in a37x0_periph_d_register_full_clk()
137 	gate = &device_def->clk_def.full_d.gate;  in a37x0_periph_d_register_full_clk()
138 	clk_mux = &device_def->clk_def.full_d. clk_mux;  in a37x0_periph_d_register_full_clk()
140 	a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs,  in a37x0_periph_d_register_full_clk()
141 	    device_def->common_def.tbg_cnt);  in a37x0_periph_d_register_full_clk()
143 	    A37x0_INTERNAL_CLK_ID(device_def->common_def.device_id, MUX_POS));  in a37x0_periph_d_register_full_clk()
147 	a37x0_periph_set_props(&div->clkdef, &tbg_mux->clkdef.name, 1);  in a37x0_periph_d_register_full_clk()
149 	    A37x0_INTERNAL_CLK_ID(device_def->common_def.device_id, DIV1_POS));  in a37x0_periph_d_register_full_clk()
153 	parent_names[0] = device_def->common_def.xtal;  in a37x0_periph_d_register_full_clk()
154 	parent_names[1] = div->clkdef.name;  in a37x0_periph_d_register_full_clk()
156 	a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT);  in a37x0_periph_d_register_full_clk()
162 	a37x0_periph_set_props(&gate->clkdef, &clk_mux->clkdef.name, 1);  in a37x0_periph_d_register_full_clk()
174  * Register CPU clock. It consists of mux (select proper TBG) -> div (frequency
175  * divider) -> mux (choose divided or xtal output).
188 	dev_id = device_def->common_def.device_id;  in a37x0_periph_d_register_periph_cpu()
189 	tbg_mux = &device_def->clk_def.cpu.tbg_mux;  in a37x0_periph_d_register_periph_cpu()
190 	div = &device_def->clk_def.cpu.div;  in a37x0_periph_d_register_periph_cpu()
191 	clk_mux = &device_def->clk_def.cpu.clk_mux;  in a37x0_periph_d_register_periph_cpu()
193 	a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs,  in a37x0_periph_d_register_periph_cpu()
194 	    device_def->common_def.tbg_cnt);  in a37x0_periph_d_register_periph_cpu()
200 	a37x0_periph_set_props(&div->clkdef, &tbg_mux->clkdef.name, 1);  in a37x0_periph_d_register_periph_cpu()
206 	parent_names[0] = device_def->common_def.xtal;  in a37x0_periph_d_register_periph_cpu()
207 	parent_names[1] = div->clkdef.name;  in a37x0_periph_d_register_periph_cpu()
209 	a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT);  in a37x0_periph_d_register_periph_cpu()
219  * Register chain: mux (choose proper TBG) -> div1 (first frequency divider) ->
220  * div2 (second frequency divider) -> mux (choose divided or xtal output).
233 	dev_id = device_def->common_def.device_id;  in a37x0_periph_d_register_mdd()
234 	tbg_mux = &device_def->clk_def.mdd.tbg_mux;  in a37x0_periph_d_register_mdd()
235 	div1 = &device_def->clk_def.mdd.div1;  in a37x0_periph_d_register_mdd()
236 	div2 = &device_def->clk_def.mdd.div2;  in a37x0_periph_d_register_mdd()
237 	clk_mux = &device_def->clk_def.mdd.clk_mux;  in a37x0_periph_d_register_mdd()
239 	a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs,  in a37x0_periph_d_register_mdd()
240 	    device_def->common_def.tbg_cnt);  in a37x0_periph_d_register_mdd()
246 	a37x0_periph_set_props(&div1->clkdef, &tbg_mux->clkdef.name, 1);  in a37x0_periph_d_register_mdd()
252 	a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1);  in a37x0_periph_d_register_mdd()
259 	parent_names[0] = device_def->common_def.xtal;  in a37x0_periph_d_register_mdd()
260 	parent_names[1] = div2->clkdef.name;  in a37x0_periph_d_register_mdd()
262 	a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT);  in a37x0_periph_d_register_mdd()