1f21c469dSHubert Mazur /*-
24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause
3f21c469dSHubert Mazur *
4f21c469dSHubert Mazur * Copyright (c) 2021 Semihalf.
5f21c469dSHubert Mazur *
6f21c469dSHubert Mazur * Redistribution and use in source and binary forms, with or without
7f21c469dSHubert Mazur * modification, are permitted provided that the following conditions
8f21c469dSHubert Mazur * are met:
9f21c469dSHubert Mazur * 1. Redistributions of source code must retain the above copyright
10f21c469dSHubert Mazur * notice, this list of conditions and the following disclaimer.
11f21c469dSHubert Mazur * 2. Redistributions in binary form must reproduce the above copyright
12f21c469dSHubert Mazur * notice, this list of conditions and the following disclaimer in the
13f21c469dSHubert Mazur * documentation and/or other materials provided with the distribution.
14f21c469dSHubert Mazur *
15f21c469dSHubert Mazur * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16f21c469dSHubert Mazur * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17f21c469dSHubert Mazur * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18f21c469dSHubert Mazur * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19f21c469dSHubert Mazur * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20f21c469dSHubert Mazur * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21f21c469dSHubert Mazur * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22f21c469dSHubert Mazur * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23f21c469dSHubert Mazur * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24f21c469dSHubert Mazur * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25f21c469dSHubert Mazur * SUCH DAMAGE.
26f21c469dSHubert Mazur */
27f21c469dSHubert Mazur
28f21c469dSHubert Mazur #include <sys/param.h>
29f21c469dSHubert Mazur #include <sys/bus.h>
30f21c469dSHubert Mazur #include <sys/kernel.h>
31f21c469dSHubert Mazur #include <sys/module.h>
32f21c469dSHubert Mazur #include <sys/mutex.h>
33f21c469dSHubert Mazur #include <sys/rman.h>
34f21c469dSHubert Mazur #include <machine/bus.h>
35f21c469dSHubert Mazur
36f21c469dSHubert Mazur #include <dev/fdt/simplebus.h>
37f21c469dSHubert Mazur
38*be82b3a0SEmmanuel Vadot #include <dev/clk/clk.h>
39*be82b3a0SEmmanuel Vadot #include <dev/clk/clk_fixed.h>
40f21c469dSHubert Mazur
41f21c469dSHubert Mazur #include <dev/ofw/ofw_bus.h>
42f21c469dSHubert Mazur #include <dev/ofw/ofw_bus_subr.h>
43f21c469dSHubert Mazur
44f21c469dSHubert Mazur #include "clkdev_if.h"
45f21c469dSHubert Mazur #include "periph.h"
46f21c469dSHubert Mazur
47f21c469dSHubert Mazur #define NB_DEV_COUNT 17
48f21c469dSHubert Mazur
49f21c469dSHubert Mazur static struct clk_div_table a37x0_periph_clk_table_6 [] = {
50f21c469dSHubert Mazur { .value = 1, .divider = 1 },
51f21c469dSHubert Mazur { .value = 2, .divider = 2 },
52f21c469dSHubert Mazur { .value = 3, .divider = 3 },
53f21c469dSHubert Mazur { .value = 4, .divider = 4 },
54f21c469dSHubert Mazur { .value = 5, .divider = 5 },
55f21c469dSHubert Mazur { .value = 6, .divider = 6 },
56f21c469dSHubert Mazur { .value = 0, .divider = 0 }
57f21c469dSHubert Mazur };
58f21c469dSHubert Mazur
59f21c469dSHubert Mazur static struct clk_div_table a37x0_periph_clk_table_2 [] = {
60f21c469dSHubert Mazur { .value = 0, .divider = 1 },
61f21c469dSHubert Mazur { .value = 1, .divider = 2 },
62f21c469dSHubert Mazur { .value = 2, .divider = 4 },
63f21c469dSHubert Mazur { .value = 3, .divider = 1 }
64f21c469dSHubert Mazur };
65f21c469dSHubert Mazur
66f21c469dSHubert Mazur static struct a37x0_periph_clknode_def a37x0_nb_devices [] = {
67f21c469dSHubert Mazur CLK_FULL_DD("mmc", 0, 2, 0, 0, DIV_SEL2, DIV_SEL2, 16, 13,
68f21c469dSHubert Mazur "tbg_mux_mmc_50", "div1_mmc_51", "div2_mmc_52", "clk_mux_mmc_53"),
69f21c469dSHubert Mazur CLK_FULL_DD("sata_host", 1, 3, 2, 1, DIV_SEL2, DIV_SEL2, 10, 7,
70f21c469dSHubert Mazur "tbg_sata_host_mmc_55", "div1_sata_host_56", "div2_sata_host_57",
71f21c469dSHubert Mazur "clk_sata_host_mmc_58"),
72f21c469dSHubert Mazur CLK_FULL_DD("sec_at", 2, 6, 4, 2, DIV_SEL1, DIV_SEL1, 3, 0,
73f21c469dSHubert Mazur "tbg_mux_sec_at_60", "div1_sec_at_61", "div2_sec_at_62",
74f21c469dSHubert Mazur "clk_mux_sec_at_63"),
75f21c469dSHubert Mazur CLK_FULL_DD("sec_dap", 3, 7, 6, 3, DIV_SEL1, DIV_SEL1, 9, 6,
76f21c469dSHubert Mazur "tbg_mux_sec_dap_65", "div1_sec_dap_67", "div2_sec_dap_68",
77f21c469dSHubert Mazur "clk_mux_sec_dap_69"),
78f21c469dSHubert Mazur CLK_FULL_DD("tsecm", 4, 8, 8, 4, DIV_SEL1, DIV_SEL1, 15, 12,
79f21c469dSHubert Mazur "tbg_mux_tsecm_71", "div1_tsecm_72", "div2_tsecm_73",
80f21c469dSHubert Mazur "clk_mux_tsecm_74"),
81f21c469dSHubert Mazur CLK_FULL("setm_tmx", 5, 10, 10, 5, DIV_SEL1, 18,
82f21c469dSHubert Mazur a37x0_periph_clk_table_6, "tbg_mux_setm_tmx_76",
83f21c469dSHubert Mazur "div1_setm_tmx_77", "clk_mux_setm_tmx_78"),
84f21c469dSHubert Mazur CLK_FIXED("avs", 6, 11, 6, "mux_avs_80", "fixed1_avs_82"),
85f21c469dSHubert Mazur CLK_FULL_DD("pwm", 7, 13, 14, 8, DIV_SEL0, DIV_SEL0, 3, 0,
86f21c469dSHubert Mazur "tbg_mux_pwm_83", "div1_pwm_84", "div2_pwm_85", "clk_mux_pwm_86"),
87f21c469dSHubert Mazur CLK_FULL_DD("sqf", 8, 12, 12, 7, DIV_SEL1, DIV_SEL1, 27, 14,
88f21c469dSHubert Mazur "tbg_mux_sqf_88", "div1_sqf_89", "div2_sqf_90", "clk_mux_sqf_91"),
89f21c469dSHubert Mazur CLK_GATE("i2c_2", 9, 16, NULL),
90f21c469dSHubert Mazur CLK_GATE("i2c_1", 10, 17, NULL),
91f21c469dSHubert Mazur CLK_MUX_GATE_FIXED("ddr_phy", 11, 19, 10, "mux_ddr_phy_95",
92f21c469dSHubert Mazur "gate_ddr_phy_96", "fixed1_ddr_phy_97"),
93f21c469dSHubert Mazur CLK_FULL_DD("ddr_fclk", 12, 21, 16, 11, DIV_SEL0, DIV_SEL0, 15, 12,
94f21c469dSHubert Mazur "tbg_mux_ddr_fclk_99", "div1_ddr_fclk_100", "div2_ddr_fclk_101",
95f21c469dSHubert Mazur "clk_mux_ddr_fclk_102"),
96f21c469dSHubert Mazur CLK_FULL("trace", 13, 22, 18, 12, DIV_SEL0, 20,
97f21c469dSHubert Mazur a37x0_periph_clk_table_6, "tbg_mux_trace_104", "div1_trace_105",
98f21c469dSHubert Mazur "clk_mux_trace_106"),
99f21c469dSHubert Mazur CLK_FULL("counter", 14, 23, 20, 13, DIV_SEL0, 23,
100f21c469dSHubert Mazur a37x0_periph_clk_table_6, "tbg_mux_counter_108",
101f21c469dSHubert Mazur "div1_counter_109", "clk_mux_counter_110"),
102f21c469dSHubert Mazur CLK_FULL_DD("eip97", 15, 26, 24, 9, DIV_SEL2, DIV_SEL2, 22, 19,
103f21c469dSHubert Mazur "tbg_mux_eip97_112", "div1_eip97_113", "div2_eip97_114",
104f21c469dSHubert Mazur "clk_mux_eip97_115"),
105f21c469dSHubert Mazur CLK_CPU("cpu", 16, 22, 15, DIV_SEL0, 28, a37x0_periph_clk_table_2,
106f21c469dSHubert Mazur "tbg_mux_cpu_117", "div1_cpu_118"),
107f21c469dSHubert Mazur };
108f21c469dSHubert Mazur
109f21c469dSHubert Mazur static struct ofw_compat_data a37x0_periph_compat_data [] = {
110f21c469dSHubert Mazur { "marvell,armada-3700-periph-clock-nb", 1 },
111f21c469dSHubert Mazur { NULL, 0 }
112f21c469dSHubert Mazur };
113f21c469dSHubert Mazur
114f21c469dSHubert Mazur static int a37x0_nb_periph_clk_attach(device_t);
115f21c469dSHubert Mazur static int a37x0_nb_periph_clk_probe(device_t);
116f21c469dSHubert Mazur
117f21c469dSHubert Mazur static device_method_t a37x0_nb_periph_clk_methods[] = {
118f21c469dSHubert Mazur DEVMETHOD(clkdev_device_unlock, a37x0_periph_clk_device_unlock),
119f21c469dSHubert Mazur DEVMETHOD(clkdev_device_lock, a37x0_periph_clk_device_lock),
120f21c469dSHubert Mazur DEVMETHOD(clkdev_read_4, a37x0_periph_clk_read_4),
121f21c469dSHubert Mazur
122f21c469dSHubert Mazur DEVMETHOD(device_attach, a37x0_nb_periph_clk_attach),
123f21c469dSHubert Mazur DEVMETHOD(device_detach, a37x0_periph_clk_detach),
124f21c469dSHubert Mazur DEVMETHOD(device_probe, a37x0_nb_periph_clk_probe),
125f21c469dSHubert Mazur
126f21c469dSHubert Mazur DEVMETHOD_END
127f21c469dSHubert Mazur };
128f21c469dSHubert Mazur
129f21c469dSHubert Mazur static driver_t a37x0_nb_periph_driver = {
130f21c469dSHubert Mazur "a37x0_nb_periph_driver",
131f21c469dSHubert Mazur a37x0_nb_periph_clk_methods,
132f21c469dSHubert Mazur sizeof(struct a37x0_periph_clk_softc)
133f21c469dSHubert Mazur };
134f21c469dSHubert Mazur
135a3b866cbSJohn Baldwin EARLY_DRIVER_MODULE(a37x0_nb_periph, simplebus, a37x0_nb_periph_driver, 0, 0,
136a3b866cbSJohn Baldwin BUS_PASS_TIMER + BUS_PASS_ORDER_LATE);
137f21c469dSHubert Mazur
138f21c469dSHubert Mazur static int
a37x0_nb_periph_clk_attach(device_t dev)139f21c469dSHubert Mazur a37x0_nb_periph_clk_attach(device_t dev)
140f21c469dSHubert Mazur {
141f21c469dSHubert Mazur struct a37x0_periph_clk_softc *sc;
142f21c469dSHubert Mazur
143f21c469dSHubert Mazur sc = device_get_softc(dev);
144f21c469dSHubert Mazur sc->devices = a37x0_nb_devices;
145f21c469dSHubert Mazur sc->device_count = NB_DEV_COUNT;
146f21c469dSHubert Mazur
147f21c469dSHubert Mazur return (a37x0_periph_clk_attach(dev));
148f21c469dSHubert Mazur }
149f21c469dSHubert Mazur
150f21c469dSHubert Mazur static int
a37x0_nb_periph_clk_probe(device_t dev)151f21c469dSHubert Mazur a37x0_nb_periph_clk_probe(device_t dev)
152f21c469dSHubert Mazur {
153f21c469dSHubert Mazur
154f21c469dSHubert Mazur if (!ofw_bus_status_okay(dev))
155f21c469dSHubert Mazur return (ENXIO);
156f21c469dSHubert Mazur
157f21c469dSHubert Mazur if (!ofw_bus_search_compatible(dev,
158f21c469dSHubert Mazur a37x0_periph_compat_data)->ocd_data)
159f21c469dSHubert Mazur return (ENXIO);
160f21c469dSHubert Mazur
161f21c469dSHubert Mazur device_set_desc(dev, "marvell,armada-3700-nb-periph-clock");
162f21c469dSHubert Mazur
163f21c469dSHubert Mazur return (BUS_PROBE_DEFAULT);
164f21c469dSHubert Mazur }
165