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/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
18 is paired with a custom DMA engine (inventively named "Flash DMA") which
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H A Dst,stm32-fmc2-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
15 - st,stm32mp15-fmc2
16 - st,stm32mp1-fmc2-nfc
17 - st,stm32mp25-fmc2-nfc
28 - description: tx DMA channel
29 - description: rx DMA channel
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H A Dti,gpmc-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments GPMC NAND Flash controller.
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
14 GPMC NAND controller/Flash is represented as a child of the
20 - enum:
21 - ti,am64-nand
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H A Dintel,lgm-ebunand.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/intel,lgm-ebunand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel LGM SoC NAND Controller
10 - $ref: nand-controller.yaml
13 - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
17 const: intel,lgm-ebunand
22 reg-names:
24 - const: ebunand
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H A Dflctl-nand.txt1 FLCTL NAND controller
4 - compatible : "renesas,shmobile-flctl-sh7372"
5 - reg : Address range of the FLCTL
6 - interrupts : flste IRQ number
7 - nand-bus-width : bus width to NAND chip
10 - dmas: DMA specifier(s)
11 - dma-names: name for each DMA specifier. Valid names are
14 The DMA fields are not used yet in the driver but are listed here for
17 The device tree may optionally contain sub-nodes describing partitions of the
23 #address-cells = <1>;
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H A Datmel-nand.txt1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
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/linux/arch/mips/boot/dts/loongson/
H A Dloongson1c.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
6 /dts-v1/;
10 clkc: clock-controller@1fe78030 {
11 compatible = "loongson,ls1c-clk";
14 #clock-cells = <1>;
20 compatible = "loongson,ls1c-syscon", "syscon";
24 intc4: interrupt-controller@10a0 {
25 compatible = "loongson,ls1x-intc";
27 interrupt-controller;
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H A Dloongson1b.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
6 /dts-v1/;
10 cpu_opp_table: opp-table {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-44000000 {
15 opp-hz = /bits/ 64 <44000000>;
17 opp-47142000 {
18 opp-hz = /bits/ 64 <47142000>;
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/linux/drivers/mtd/nand/raw/atmel/
H A Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
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/linux/arch/arm/boot/dts/microchip/
H A Dat91-wb50n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-wb50n.dtsi - Device Tree include file for wb50n cpu module
12 model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
17 stdout-path = "serial0:115200n8";
38 clock-frequency = <32768>;
42 clock-frequency = <12000000>;
46 atmel,osc-bypass;
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
52 cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>;
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H A Dat91-kizbox3_common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox3.dts - Device Tree Include file for Overkiz Kizbox 3
12 /dts-v1/;
14 #include "sama5d2-pinfunc.h"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
17 #include <dt-bindings/pinctrl/at91.h>
18 #include <dt-bindings/pwm/pwm.h>
36 stdout-path = "serial1:115200n8";
41 clock-frequency = <32768>;
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H A Dat91-kizboxmini-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board
5 * Copyright (C) 2014-2018 Overkiz SAS
16 stdout-path = &dbgu;
25 clock-frequency = <12000000>;
29 clock-frequency = <32768>;
38 compatible = "gpio-keys";
40 key-prog {
44 wakeup-source;
47 key-reset {
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H A Dat91-som60.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-som60.dtsi - Device Tree file for the SOM60 module
16 stdout-path = &dbgu;
25 clock-frequency = <32768>;
29 clock-frequency = <12000000>;
107 bus-width = <8>;
115 bus-width = <4>;
120 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
124 atmel,use-dma-rx;
125 atmel,use-dma-tx;
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H A Dat91-sama5d4_xplained.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
14 compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5";
17 stdout-path = "serial0:115200n8";
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
37 atmel,use-dma-rx;
38 atmel,use-dma-tx;
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/linux/drivers/mtd/nand/raw/
H A Dlpc32xx_slc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * NXP LPC32XX NAND SLC driver
24 #include <linux/dma-mapping.h>
30 #define LPC32XX_MODNAME "lpc32xx-nand"
425 lpc32xx_xmit_dma(struct mtd_info * mtd,dma_addr_t dma,void * mem,int len,enum dma_transfer_direction dir) lpc32xx_xmit_dma() argument
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H A Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
211 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
213 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_rs_ecc()
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H A Dlpc32xx_mlc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for NAND MLC Controller in LPC32xx
10 * NAND Flash Controller Operation:
11 * - Read: Auto Decode
12 * - Write: Auto Encode
13 * - Tested Page Sizes: 2048, 4096
32 #include <linux/dma-mapping.h>
38 * MLC NAND controller register offsets
134 if (section >= nand_chip->ecc.steps) in lpc32xx_ooblayout_ecc()
135 return -ERANGE; in lpc32xx_ooblayout_ecc()
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H A Dcafe_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <linux/dma-mapping.h>
61 struct nand_chip nand; member
101 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
102 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
112 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", in cafe_device_ready()
124 if (cafe->usedma) in cafe_write_buf()
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len); in cafe_write_buf()
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); in cafe_write_buf()
129 cafe->datalen += len; in cafe_write_buf()
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H A Dstm32_fmc2_nand.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
37 /* Max requests done for a 8k nand page size */
256 struct stm32_fmc2_nand nand; member
295 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); in stm32_fmc2_nfc_timings_init()
296 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); in stm32_fmc2_nfc_timings_init() local
297 struct stm32_fmc2_timings *timings = &nand->timings; in stm32_fmc2_nfc_timings_init()
301 regmap_update_bits(nfc->regmap, FMC2_PCR, in stm32_fmc2_nfc_timings_init()
303 FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) | in stm32_fmc2_nfc_timings_init()
304 FIELD_PREP(FMC2_PCR_TAR, timings->tar)); in stm32_fmc2_nfc_timings_init()
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H A Dnuvoton-ma35d1-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/dma-mapping.h>
119 return -ERANGE; in ma35_ooblayout_ecc()
121 oob_region->length = chip->ecc.total; in ma35_ooblayout_ecc()
122 oob_region->offset = mtd->oobsize - oob_region->length; in ma35_ooblayout_ecc()
133 return -ERANGE; in ma35_ooblayout_free()
135 oob_region->length = mtd->oobsize - chip->ecc.total - 2; in ma35_ooblayout_free()
136 oob_region->offset = 2; in ma35_ooblayout_free()
148 struct ma35_nand_info *nand = nand_get_controller_data(chip); in ma35_clear_spare() local
152 writel(0xff, nand->regs + MA35_NFI_REG_NANDRA0); in ma35_clear_spare()
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
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/linux/drivers/mtd/nand/
H A Decc-realtek.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/dma-mapping.h>
8 #include <linux/mtd/nand.h>
16 * - BCH6 : Generate 10 ECC bytes from 512 data bytes plus 6 free bytes
17 * - BCH12 : Generate 20 ECC bytes from 512 data bytes plus 6 free bytes
19 * It can run for arbitrary NAND flash chips with different block and OOB sizes. Currently there
20 * are only two known devices in the wild that have NAND flash and make use of this ECC engine
28 * - BBI : Bad block indicator. The first two bytes of OOB. Protected by ECC!
29 * - tag : 6 User/free bytes. First tag "contains" 2 bytes BBI. Protected by ECC!
30 * - syndrome : ECC/parity bytes
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/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-evm-common.dtsi"
9 #include "dra74x-mmc-iodelay.dtsi"
13 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
20 evm_12v0: fixedregulator-evm_12v0 {
22 compatible = "regulator-fixed";
23 regulator-name = "evm_12v0";
24 regulator-min-microvolt = <12000000>;
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp157a-microgea-stm32mp1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
9 compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
16 reserved-memory {
17 #address-cells = <1>;
18 #size-cells = <1>;
22 compatible = "shared-dma-pool";
24 no-map;
28 compatible = "shared-dma-pool";
30 no-map;
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/linux/Documentation/devicetree/bindings/dma/
H A Dloongson,ls1b-apbdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/loongson,ls1b-apbdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1 APB DMA Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1 APB DMA controller provides 3 independent channels for
14 peripherals such as NAND, audio playback and capture.
19 - const: loongson,ls1b-apbdma
20 - items:
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