| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | mediatek,mt8196-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8196
27 - mediatek,mt8196-imp-iic-wrap-c
28 - mediatek,mt8196-imp-iic-wrap-e
29 - mediatek,mt8196-imp-iic-wrap-n
30 - mediatek,mt8196-imp-iic-wrap-w
31 - mediatek,mt8196-mdpsys0
32 - mediatek,mt8196-mdpsys1
33 - mediatek,mt8196-pericfg-ao
34 - mediatek,mt8196-pextp0cfg-ao
[all …]
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| H A D | mediatek,mt8196-sys-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
7 title: MediaTek System Clock Controller for MT8196
30 - mediatek,mt8196-apmixedsys
31 - mediatek,mt8196-armpll-b-pll-ctrl
32 - mediatek,mt8196-armpll-bl-pll-ctrl
33 - mediatek,mt8196-armpll-ll-pll-ctrl
34 - mediatek,mt8196-apmixedsys-gp2
35 - mediatek,mt8196-ccipll-pll-ctrl
36 - mediatek,mt8196-mfgpll-pll-ctrl
37 - mediatek,mt8196-mfgpll-sc0-pll-ctrl
[all …]
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | mediatek,mt8196-pinctrl.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8196-pinctrl.yaml#
7 title: MediaTek MT8196 Pin Controller
14 The MediaTek's MT8196 Pin controller is used to control SoC pins.
18 const: mediatek,mt8196-pinctrl
114 defined as macros in arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h
124 description: mt8196 pull down PUPD/R0/R1 type define value.
126 description: mt8196 pull down RSEL type si unit value(ohm).
133 "MTK_PUPD_SET_R1R0_11" define in mt8196.
137 value(ohm) "75000" & "5000" in mt8196.
143 description: mt8196 pull up PUPD/R0/R1 type define value.
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| /linux/drivers/clk/mediatek/ |
| H A D | Makefile | 153 obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \
154 clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
155 clk-mt8196-peri_ao.o
156 obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
157 obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
158 obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
159 obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
160 obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.…
161 clk-mt8196-ovl0.o clk-mt8196-ovl1.o
162 obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
[all …]
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| H A D | clk-mt8196-imp_iic_wrap.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
99 { .compatible = "mediatek,mt8196-imp-iic-wrap-c", .data = &impc_mcd },
100 { .compatible = "mediatek,mt8196-imp-iic-wrap-e", .data = &impe_mcd },
101 { .compatible = "mediatek,mt8196-imp-iic-wrap-n", .data = &impn_mcd },
102 { .compatible = "mediatek,mt8196-imp-iic-wrap-w", .data = &impw_mcd },
111 .name = "clk-mt8196-imp_iic_wrap",
117 MODULE_DESCRIPTION("MediaTek MT8196 I2C Wrapper clocks driver");
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| H A D | clk-mt8196-pextp.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
9 #include <dt-bindings/reset/mediatek,mt8196-resets.h>
114 { .compatible = "mediatek,mt8196-pextp0cfg-ao", .data = &pext_mcd },
115 { .compatible = "mediatek,mt8196-pextp1cfg-ao", .data = &pext1_mcd },
124 .name = "clk-mt8196-pextp",
130 MODULE_DESCRIPTION("MediaTek MT8196 PCIe transmit phy clocks driver");
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| H A D | clk-mt8196-ufs_ao.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
9 #include <dt-bindings/reset/mediatek,mt8196-resets.h>
92 { .compatible = "mediatek,mt8196-ufscfg-ao", .data = &ufsao_mcd },
101 .name = "clk-mt8196-ufs-ao",
107 MODULE_DESCRIPTION("MediaTek MT8196 ufs_ao clocks driver");
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| H A D | clk-mt8196-vdisp_ao.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
64 { .compatible = "mediatek,mt8196-vdisp-ao", .data = &mm_v_mcd },
73 .name = "clk-mt8196-vdisp-ao",
79 MODULE_DESCRIPTION("MediaTek MT8196 vdisp_ao clocks driver");
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| H A D | clk-mt8196-venc.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
218 { .compatible = "mediatek,mt8196-vencsys", .data = &ven1_mcd },
219 { .compatible = "mediatek,mt8196-vencsys-c1", .data = &ven2_mcd },
220 { .compatible = "mediatek,mt8196-vencsys-c2", .data = &ven_c2_mcd },
229 .name = "clk-mt8196-venc",
235 MODULE_DESCRIPTION("MediaTek MT8196 Video Encoders clocks driver");
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| H A D | clk-mt8196-vdec.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
236 { .compatible = "mediatek,mt8196-vdecsys", .data = &vde2_mcd },
237 { .compatible = "mediatek,mt8196-vdecsys-soc", .data = &vde1_mcd },
246 .name = "clk-mt8196-vdec",
252 MODULE_DESCRIPTION("MediaTek MT8196 Video Decoders clocks driver");
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| H A D | clk-mt8196-peri_ao.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
126 { .compatible = "mediatek,mt8196-pericfg-ao", .data = &peri_ao_mcd },
135 .name = "clk-mt8196-peri-ao",
140 MODULE_DESCRIPTION("MediaTek MT8196 pericfg_ao clock controller driver");
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| H A D | clk-mt8196-mdpsys.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
169 { .compatible = "mediatek,mt8196-mdpsys0", .data = &mdp_mcd },
170 { .compatible = "mediatek,mt8196-mdpsys1", .data = &mdp1_mcd },
179 .name = "clk-mt8196-mdpsys",
185 MODULE_DESCRIPTION("MediaTek MT8196 Multimedia Data Path clocks driver");
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| H A D | clk-mt8196-ovl1.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
138 { .name = "clk-mt8196-ovl1", .driver_data = (kernel_ulong_t)&ovl1_mcd },
147 .name = "clk-mt8196-ovl1",
153 MODULE_DESCRIPTION("MediaTek MT8196 ovl1 clocks driver");
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| H A D | clk-mt8196-ovl0.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
138 { .name = "clk-mt8196-ovl0", .driver_data = (kernel_ulong_t)&ovl_mcd },
147 .name = "clk-mt8196-ovl0",
153 MODULE_DESCRIPTION("MediaTek MT8196 ovl0 clocks driver");
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| H A D | clk-mt8196-disp0.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
154 { .name = "clk-mt8196-disp0", .driver_data = (kernel_ulong_t)&mm_mcd },
163 .name = "clk-mt8196-disp0",
169 MODULE_DESCRIPTION("MediaTek MT8196 disp0 clocks driver");
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| H A D | clk-mt8196-disp1.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
154 { .name = "clk-mt8196-disp1", .driver_data = (kernel_ulong_t)&mm1_mcd },
163 .name = "clk-mt8196-disp1",
169 MODULE_DESCRIPTION("MediaTek MT8196 disp1 clocks driver");
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| H A D | clk-mt8196-topckgen2.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
552 { .compatible = "mediatek,mt8196-topckgen-gp2", .data = &topck_desc },
561 .name = "clk-mt8196-topck2",
566 MODULE_DESCRIPTION("MediaTek MT8196 GP2 top clock generators driver");
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| H A D | clk-mt8196-topckgen.c | 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
969 { .compatible = "mediatek,mt8196-topckgen", .data = &topck_desc },
978 .name = "clk-mt8196-topck",
983 MODULE_DESCRIPTION("MediaTek MT8196 top clock generators driver");
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | mtk-sd.yaml | 28 - mediatek,mt8196-mmc
196 - mediatek,mt8196-mmc
243 - mediatek,mt8196-mmc
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| /linux/drivers/pinctrl/mediatek/ |
| H A D | Kconfig | 299 bool "MediaTek MT8196 pin control"
306 on MediaTek MT8196 SoC.
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| H A D | Makefile | 42 obj-$(CONFIG_PINCTRL_MT8196) += pinctrl-mt8196.o
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| /linux/Documentation/devicetree/bindings/regulator/ |
| H A D | mediatek,mt6873-dvfsrc-regulator.yaml | 24 - mediatek,mt8196-dvfsrc-regulator
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| /linux/drivers/mailbox/ |
| H A D | mtk-gpueb-mailbox.c | 3 * MediaTek GPUEB mailbox driver for SoCs such as the MT8196
303 { .compatible = "mediatek,mt8196-gpueb-mbox", .data = &mtk_gpueb_mbox_mt8196 },
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| /linux/Documentation/devicetree/bindings/pwm/ |
| H A D | mediatek,mt2712-pwm.yaml | 38 - mediatek,mt8196-pwm
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| /linux/drivers/cpufreq/ |
| H A D | mediatek-cpufreq-hw.c | 246 * In a cpufreq with hybrid DVFS, such as the MT8196, the first declared in mtk_cpu_resources_init()
425 { .compatible = "mediatek,mt8196-cpufreq-hw", .data = &cpufreq_mtk_mt8196_variant },
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