1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025 MediaTek Inc. 4 * Guangjie Song <guangjie.song@mediatek.com> 5 * Copyright (c) 2025 Collabora Ltd. 6 * Laura Nao <laura.nao@collabora.com> 7 */ 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h> 9 10 #include <linux/clk.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 17 #include "clk-mtk.h" 18 #include "clk-mux.h" 19 20 /* MUX SEL REG */ 21 #define CLK_CFG_UPDATE 0x0004 22 #define CLK_CFG_UPDATE1 0x0008 23 #define CLK_CFG_UPDATE2 0x000c 24 #define CLK_CFG_0 0x0010 25 #define CLK_CFG_0_SET 0x0014 26 #define CLK_CFG_0_CLR 0x0018 27 #define CLK_CFG_1 0x0020 28 #define CLK_CFG_1_SET 0x0024 29 #define CLK_CFG_1_CLR 0x0028 30 #define CLK_CFG_2 0x0030 31 #define CLK_CFG_2_SET 0x0034 32 #define CLK_CFG_2_CLR 0x0038 33 #define CLK_CFG_3 0x0040 34 #define CLK_CFG_3_SET 0x0044 35 #define CLK_CFG_3_CLR 0x0048 36 #define CLK_CFG_4 0x0050 37 #define CLK_CFG_4_SET 0x0054 38 #define CLK_CFG_4_CLR 0x0058 39 #define CLK_CFG_5 0x0060 40 #define CLK_CFG_5_SET 0x0064 41 #define CLK_CFG_5_CLR 0x0068 42 #define CLK_CFG_6 0x0070 43 #define CLK_CFG_6_SET 0x0074 44 #define CLK_CFG_6_CLR 0x0078 45 #define CLK_CFG_7 0x0080 46 #define CLK_CFG_7_SET 0x0084 47 #define CLK_CFG_7_CLR 0x0088 48 #define CLK_CFG_8 0x0090 49 #define CLK_CFG_8_SET 0x0094 50 #define CLK_CFG_8_CLR 0x0098 51 #define CLK_CFG_9 0x00a0 52 #define CLK_CFG_9_SET 0x00a4 53 #define CLK_CFG_9_CLR 0x00a8 54 #define CLK_CFG_10 0x00b0 55 #define CLK_CFG_10_SET 0x00b4 56 #define CLK_CFG_10_CLR 0x00b8 57 #define CLK_CFG_11 0x00c0 58 #define CLK_CFG_11_SET 0x00c4 59 #define CLK_CFG_11_CLR 0x00c8 60 #define CLK_CFG_12 0x00d0 61 #define CLK_CFG_12_SET 0x00d4 62 #define CLK_CFG_12_CLR 0x00d8 63 #define CLK_CFG_13 0x00e0 64 #define CLK_CFG_13_SET 0x00e4 65 #define CLK_CFG_13_CLR 0x00e8 66 #define CLK_CFG_14 0x00f0 67 #define CLK_CFG_14_SET 0x00f4 68 #define CLK_CFG_14_CLR 0x00f8 69 #define CLK_CFG_15 0x0100 70 #define CLK_CFG_15_SET 0x0104 71 #define CLK_CFG_15_CLR 0x0108 72 #define CLK_CFG_16 0x0110 73 #define CLK_CFG_16_SET 0x0114 74 #define CLK_CFG_16_CLR 0x0118 75 #define CLK_CFG_17 0x0120 76 #define CLK_CFG_17_SET 0x0124 77 #define CLK_CFG_17_CLR 0x0128 78 #define CLK_CFG_18 0x0130 79 #define CLK_CFG_18_SET 0x0134 80 #define CLK_CFG_18_CLR 0x0138 81 #define CLK_CFG_19 0x0140 82 #define CLK_CFG_19_SET 0x0144 83 #define CLK_CFG_19_CLR 0x0148 84 #define CLK_AUDDIV_0 0x020c 85 #define CLK_FENC_STATUS_MON_0 0x0270 86 #define CLK_FENC_STATUS_MON_1 0x0274 87 #define CLK_FENC_STATUS_MON_2 0x0278 88 89 /* MUX SHIFT */ 90 #define TOP_MUX_AXI_SHIFT 0 91 #define TOP_MUX_MEM_SUB_SHIFT 1 92 #define TOP_MUX_IO_NOC_SHIFT 2 93 #define TOP_MUX_PERI_AXI_SHIFT 3 94 #define TOP_MUX_UFS_PEXTP0_AXI_SHIFT 4 95 #define TOP_MUX_PEXTP1_USB_AXI_SHIFT 5 96 #define TOP_MUX_PERI_FMEM_SUB_SHIFT 6 97 #define TOP_MUX_UFS_PEXPT0_MEM_SUB_SHIFT 7 98 #define TOP_MUX_PEXTP1_USB_MEM_SUB_SHIFT 8 99 #define TOP_MUX_PERI_NOC_SHIFT 9 100 #define TOP_MUX_EMI_N_SHIFT 10 101 #define TOP_MUX_EMI_S_SHIFT 11 102 #define TOP_MUX_AP2CONN_HOST_SHIFT 14 103 #define TOP_MUX_ATB_SHIFT 15 104 #define TOP_MUX_CIRQ_SHIFT 16 105 #define TOP_MUX_PBUS_156M_SHIFT 17 106 #define TOP_MUX_EFUSE_SHIFT 20 107 #define TOP_MUX_MCU_L3GIC_SHIFT 21 108 #define TOP_MUX_MCU_INFRA_SHIFT 22 109 #define TOP_MUX_DSP_SHIFT 23 110 #define TOP_MUX_MFG_REF_SHIFT 24 111 #define TOP_MUX_MFG_EB_SHIFT 26 112 #define TOP_MUX_UART_SHIFT 27 113 #define TOP_MUX_SPI0_BCLK_SHIFT 28 114 #define TOP_MUX_SPI1_BCLK_SHIFT 29 115 #define TOP_MUX_SPI2_BCLK_SHIFT 30 116 #define TOP_MUX_SPI3_BCLK_SHIFT 0 117 #define TOP_MUX_SPI4_BCLK_SHIFT 1 118 #define TOP_MUX_SPI5_BCLK_SHIFT 2 119 #define TOP_MUX_SPI6_BCLK_SHIFT 3 120 #define TOP_MUX_SPI7_BCLK_SHIFT 4 121 #define TOP_MUX_MSDC30_1_SHIFT 7 122 #define TOP_MUX_MSDC30_2_SHIFT 8 123 #define TOP_MUX_DISP_PWM_SHIFT 9 124 #define TOP_MUX_USB_TOP_1P_SHIFT 10 125 #define TOP_MUX_SSUSB_XHCI_1P_SHIFT 11 126 #define TOP_MUX_SSUSB_FMCNT_P1_SHIFT 12 127 #define TOP_MUX_I2C_PERI_SHIFT 13 128 #define TOP_MUX_I2C_EAST_SHIFT 14 129 #define TOP_MUX_I2C_WEST_SHIFT 15 130 #define TOP_MUX_I2C_NORTH_SHIFT 16 131 #define TOP_MUX_AES_UFSFDE_SHIFT 17 132 #define TOP_MUX_UFS_SHIFT 18 133 #define TOP_MUX_AUD_1_SHIFT 21 134 #define TOP_MUX_AUD_2_SHIFT 22 135 #define TOP_MUX_ADSP_SHIFT 23 136 #define TOP_MUX_ADSP_UARTHUB_B_SHIFT 24 137 #define TOP_MUX_DPMAIF_MAIN_SHIFT 25 138 #define TOP_MUX_PWM_SHIFT 26 139 #define TOP_MUX_MCUPM_SHIFT 27 140 #define TOP_MUX_SFLASH_SHIFT 28 141 #define TOP_MUX_IPSEAST_SHIFT 29 142 #define TOP_MUX_TL_SHIFT 0 143 #define TOP_MUX_TL_P1_SHIFT 1 144 #define TOP_MUX_TL_P2_SHIFT 2 145 #define TOP_MUX_EMI_INTERFACE_546_SHIFT 3 146 #define TOP_MUX_SDF_SHIFT 4 147 #define TOP_MUX_UARTHUB_BCLK_SHIFT 5 148 #define TOP_MUX_DPSW_CMP_26M_SHIFT 6 149 #define TOP_MUX_SMAPCK_SHIFT 7 150 #define TOP_MUX_SSR_PKA_SHIFT 8 151 #define TOP_MUX_SSR_DMA_SHIFT 9 152 #define TOP_MUX_SSR_KDF_SHIFT 10 153 #define TOP_MUX_SSR_RNG_SHIFT 11 154 #define TOP_MUX_SPU0_SHIFT 12 155 #define TOP_MUX_SPU1_SHIFT 13 156 #define TOP_MUX_DXCC_SHIFT 14 157 158 /* CKSTA REG */ 159 #define CKSTA_REG 0x01c8 160 #define CKSTA_REG1 0x01cc 161 #define CKSTA_REG2 0x01d0 162 163 /* DIVIDER REG */ 164 #define CLK_AUDDIV_2 0x0214 165 #define CLK_AUDDIV_3 0x0220 166 #define CLK_AUDDIV_4 0x0224 167 #define CLK_AUDDIV_5 0x0228 168 169 /* HW Voter REG */ 170 #define HWV_CG_0_SET 0x0000 171 #define HWV_CG_0_CLR 0x0004 172 #define HWV_CG_0_DONE 0x2c00 173 #define HWV_CG_1_SET 0x0008 174 #define HWV_CG_1_CLR 0x000c 175 #define HWV_CG_1_DONE 0x2c04 176 #define HWV_CG_2_SET 0x0010 177 #define HWV_CG_2_CLR 0x0014 178 #define HWV_CG_2_DONE 0x2c08 179 #define HWV_CG_3_SET 0x0018 180 #define HWV_CG_3_CLR 0x001c 181 #define HWV_CG_3_DONE 0x2c0c 182 #define HWV_CG_4_SET 0x0020 183 #define HWV_CG_4_CLR 0x0024 184 #define HWV_CG_4_DONE 0x2c10 185 #define HWV_CG_5_SET 0x0028 186 #define HWV_CG_5_CLR 0x002c 187 #define HWV_CG_5_DONE 0x2c14 188 #define HWV_CG_6_SET 0x0030 189 #define HWV_CG_6_CLR 0x0034 190 #define HWV_CG_6_DONE 0x2c18 191 #define HWV_CG_7_SET 0x0038 192 #define HWV_CG_7_CLR 0x003c 193 #define HWV_CG_7_DONE 0x2c1c 194 #define HWV_CG_8_SET 0x0040 195 #define HWV_CG_8_CLR 0x0044 196 #define HWV_CG_8_DONE 0x2c20 197 198 static const struct mtk_fixed_factor top_divs[] = { 199 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), 200 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), 201 FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll", 1, 8), 202 FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll", 1, 16), 203 FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll", 1, 32), 204 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), 205 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll", 1, 10), 206 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll", 1, 20), 207 FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll", 1, 40), 208 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6), 209 FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll", 1, 12), 210 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), 211 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll", 1, 14), 212 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll", 1, 28), 213 FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll", 1, 56), 214 FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9), 215 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4), 216 FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll", 1, 8), 217 FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll", 1, 16), 218 FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll", 1, 32), 219 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 220 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll", 1, 10), 221 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll", 1, 20), 222 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6), 223 FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll", 1, 12), 224 FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll", 1, 24), 225 FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll", 1, 48), 226 FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll", 1, 96), 227 FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13), 228 FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll", 1, 52), 229 FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll", 1, 104), 230 FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll", 1, 208), 231 FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll", 1, 416), 232 FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10", "univpll", 1, 130), 233 FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2), 234 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 235 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2), 236 FACTOR(CLK_TOP_OSC_D3, "osc_d3", "ulposc", 1, 3), 237 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4), 238 FACTOR(CLK_TOP_OSC_D5, "osc_d5", "ulposc", 1, 5), 239 FACTOR(CLK_TOP_OSC_D7, "osc_d7", "ulposc", 1, 7), 240 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8), 241 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10), 242 FACTOR(CLK_TOP_OSC_D14, "osc_d14", "ulposc", 1, 14), 243 FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20), 244 FACTOR(CLK_TOP_OSC_D32, "osc_d32", "ulposc", 1, 32), 245 FACTOR(CLK_TOP_OSC_D40, "osc_d40", "ulposc", 1, 40), 246 }; 247 248 static const char * const axi_parents[] = { 249 "clk26m", 250 "osc_d20", 251 "osc_d8", 252 "osc_d4", 253 "mainpll_d4_d4", 254 "mainpll_d7_d2" 255 }; 256 257 static const char * const mem_sub_parents[] = { 258 "clk26m", 259 "osc_d20", 260 "osc_d4", 261 "univpll_d4_d4", 262 "osc_d3", 263 "mainpll_d5_d2", 264 "mainpll_d4_d2", 265 "mainpll_d6", 266 "mainpll_d5", 267 "univpll_d5", 268 "mainpll_d4", 269 "mainpll_d3" 270 }; 271 272 static const char * const io_noc_parents[] = { 273 "clk26m", 274 "osc_d20", 275 "osc_d8", 276 "osc_d4", 277 "mainpll_d6_d2", 278 "mainpll_d9" 279 }; 280 281 static const char * const shared_axi_parents[] = { 282 "clk26m", 283 "mainpll_d7_d8", 284 "mainpll_d5_d8", 285 "osc_d8", 286 "mainpll_d7_d4", 287 "mainpll_d5_d4", 288 "mainpll_d4_d4", 289 "mainpll_d7_d2" 290 }; 291 292 static const char * const shared_sub_parents[] = { 293 "clk26m", 294 "mainpll_d5_d8", 295 "mainpll_d5_d4", 296 "osc_d4", 297 "univpll_d4_d4", 298 "mainpll_d5_d2", 299 "mainpll_d4_d2", 300 "mainpll_d6", 301 "mainpll_d5", 302 "univpll_d5", 303 "mainpll_d4" 304 }; 305 306 static const char * const p_noc_parents[] = { 307 "clk26m", 308 "mainpll_d5_d8", 309 "mainpll_d5_d4", 310 "osc_d4", 311 "univpll_d4_d4", 312 "mainpll_d5_d2", 313 "mainpll_d4_d2", 314 "mainpll_d6", 315 "mainpll_d5", 316 "univpll_d5", 317 "mainpll_d4", 318 "mainpll_d3" 319 }; 320 321 static const char * const emi_parents[] = { 322 "clk26m", 323 "osc_d4", 324 "mainpll_d5_d8", 325 "mainpll_d5_d4", 326 "mainpll_d4_d4", 327 "emipll1_ck" 328 }; 329 330 static const char * const ap2conn_host_parents[] = { 331 "clk26m", 332 "mainpll_d7_d4" 333 }; 334 335 static const char * const atb_parents[] = { 336 "clk26m", 337 "mainpll_d5_d2", 338 "mainpll_d4_d2", 339 "mainpll_d6" 340 }; 341 342 static const char * const cirq_parents[] = { 343 "clk26m", 344 "osc_d20", 345 "mainpll_d7_d4" 346 }; 347 348 static const char * const pbus_156m_parents[] = { 349 "clk26m", 350 "mainpll_d7_d2", 351 "osc_d2", 352 "mainpll_d7" 353 }; 354 355 static const char * const efuse_parents[] = { 356 "clk26m", 357 "osc_d20" 358 }; 359 360 static const char * const mcu_l3gic_parents[] = { 361 "clk26m", 362 "osc_d8", 363 "mainpll_d4_d4", 364 "mainpll_d7_d2" 365 }; 366 367 static const char * const mcu_infra_parents[] = { 368 "clk26m", 369 "osc_d20", 370 "mainpll_d7_d2", 371 "mainpll_d5_d2", 372 "mainpll_d4_d2", 373 "mainpll_d9", 374 "mainpll_d6" 375 }; 376 377 static const char * const dsp_parents[] = { 378 "clk26m", 379 "osc_d5", 380 "osc_d4", 381 "osc_d3", 382 "univpll_d6_d2", 383 "osc_d2", 384 "univpll_d5", 385 "osc" 386 }; 387 388 static const char * const mfg_ref_parents[] = { 389 "clk26m", 390 "mainpll_d7_d2" 391 }; 392 393 static const char * const mfg_eb_parents[] = { 394 "clk26m", 395 "mainpll_d7_d2", 396 "mainpll_d6_d2", 397 "mainpll_d5_d2" 398 }; 399 400 static const char * const uart_parents[] = { 401 "clk26m", 402 "univpll_d6_d8", 403 "univpll_d6_d4", 404 "univpll_d6_d2" 405 }; 406 407 static const char * const spi_b_parents[] = { 408 "clk26m", 409 "univpll_d6_d4", 410 "univpll_d5_d4", 411 "mainpll_d4_d4", 412 "univpll_d4_d4", 413 "mainpll_d6_d2", 414 "univpll_192m", 415 "univpll_d6_d2" 416 }; 417 418 static const char * const msdc30_parents[] = { 419 "clk26m", 420 "univpll_d6_d4", 421 "mainpll_d6_d2", 422 "univpll_d6_d2", 423 "msdcpll_d2" 424 }; 425 426 static const char * const disp_pwm_parents[] = { 427 "clk26m", 428 "osc_d32", 429 "osc_d8", 430 "univpll_d6_d4", 431 "univpll_d5_d4", 432 "osc_d4", 433 "mainpll_d4_d4" 434 }; 435 436 static const char * const usb_1p_parents[] = { 437 "clk26m", 438 "univpll_d5_d4" 439 }; 440 441 static const char * const usb_fmcnt_p1_parents[] = { 442 "clk26m", 443 "univpll_192m_d4" 444 }; 445 446 static const char * const i2c_parents[] = { 447 "clk26m", 448 "mainpll_d4_d8", 449 "univpll_d5_d4", 450 "mainpll_d4_d4", 451 "univpll_d5_d2" 452 }; 453 454 static const char * const aes_ufsfde_parents[] = { 455 "clk26m", 456 "mainpll_d4_d4", 457 "univpll_d6_d2", 458 "mainpll_d4_d2", 459 "univpll_d6", 460 "mainpll_d4" 461 }; 462 463 static const char * const ufs_parents[] = { 464 "clk26m", 465 "mainpll_d4_d4", 466 "univpll_d6_d2", 467 "mainpll_d4_d2", 468 "univpll_d6", 469 "mainpll_d5", 470 "univpll_d5" 471 }; 472 473 static const char * const aud_1_parents[] = { 474 "clk26m", 475 "vlp_apll1" 476 }; 477 478 static const char * const aud_2_parents[] = { 479 "clk26m", 480 "vlp_apll2" 481 }; 482 483 static const char * const adsp_parents[] = { 484 "clk26m", 485 "adsppll" 486 }; 487 488 static const char * const adsp_uarthub_b_parents[] = { 489 "clk26m", 490 "univpll_d6_d4", 491 "univpll_d6_d2" 492 }; 493 494 static const char * const dpmaif_main_parents[] = { 495 "clk26m", 496 "univpll_d4_d4", 497 "univpll_d5_d2", 498 "mainpll_d4_d2", 499 "univpll_d4_d2", 500 "mainpll_d6", 501 "univpll_d6", 502 "mainpll_d5", 503 "univpll_d5" 504 }; 505 506 static const char * const pwm_parents[] = { 507 "clk26m", 508 "mainpll_d7_d4", 509 "univpll_d4_d8" 510 }; 511 512 static const char * const mcupm_parents[] = { 513 "clk26m", 514 "mainpll_d7_d2", 515 "mainpll_d6_d2", 516 "univpll_d6_d2", 517 "mainpll_d5_d2" 518 }; 519 520 static const char * const ipseast_parents[] = { 521 "clk26m", 522 "mainpll_d6", 523 "mainpll_d5", 524 "mainpll_d4", 525 "mainpll_d3" 526 }; 527 528 static const char * const tl_parents[] = { 529 "clk26m", 530 "mainpll_d7_d4", 531 "mainpll_d4_d4", 532 "mainpll_d5_d2" 533 }; 534 535 static const char * const md_emi_parents[] = { 536 "clk26m", 537 "mainpll_d4" 538 }; 539 540 static const char * const sdf_parents[] = { 541 "clk26m", 542 "mainpll_d5_d2", 543 "mainpll_d4_d2", 544 "mainpll_d6", 545 "mainpll_d4", 546 "univpll_d4" 547 }; 548 549 static const char * const uarthub_b_parents[] = { 550 "clk26m", 551 "univpll_d6_d4", 552 "univpll_d6_d2" 553 }; 554 555 static const char * const dpsw_cmp_26m_parents[] = { 556 "clk26m", 557 "osc_d20" 558 }; 559 560 static const char * const smapparents[] = { 561 "clk26m", 562 "mainpll_d4_d8" 563 }; 564 565 static const char * const ssr_parents[] = { 566 "clk26m", 567 "mainpll_d4_d4", 568 "mainpll_d4_d2", 569 "mainpll_d7", 570 "mainpll_d6", 571 "mainpll_d5" 572 }; 573 574 static const char * const ssr_kdf_parents[] = { 575 "clk26m", 576 "mainpll_d4_d4", 577 "mainpll_d4_d2", 578 "mainpll_d7" 579 }; 580 581 static const char * const ssr_rng_parents[] = { 582 "clk26m", 583 "mainpll_d4_d4", 584 "mainpll_d5_d2", 585 "mainpll_d4_d2" 586 }; 587 588 static const char * const spu_parents[] = { 589 "clk26m", 590 "mainpll_d4_d4", 591 "mainpll_d4_d2", 592 "mainpll_d7", 593 "mainpll_d6", 594 "mainpll_d5" 595 }; 596 597 static const char * const dxcc_parents[] = { 598 "clk26m", 599 "mainpll_d4_d8", 600 "mainpll_d4_d4", 601 "mainpll_d4_d2" 602 }; 603 604 static const char * const apll_m_parents[] = { 605 "aud_1", 606 "aud_2" 607 }; 608 609 static const char * const sflash_parents[] = { 610 "clk26m", 611 "mainpll_d7_d8", 612 "univpll_d6_d8" 613 }; 614 615 static const struct mtk_mux top_muxes[] = { 616 /* CLK_CFG_0 */ 617 MUX_CLR_SET_UPD(CLK_TOP_AXI, "axi", 618 axi_parents, CLK_CFG_0, CLK_CFG_0_SET, 619 CLK_CFG_0_CLR, 0, 3, 620 CLK_CFG_UPDATE, TOP_MUX_AXI_SHIFT), 621 MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB, "mem_sub", 622 mem_sub_parents, CLK_CFG_0, CLK_CFG_0_SET, 623 CLK_CFG_0_CLR, 8, 4, 624 CLK_CFG_UPDATE, TOP_MUX_MEM_SUB_SHIFT), 625 MUX_CLR_SET_UPD(CLK_TOP_IO_NOC, "io_noc", 626 io_noc_parents, CLK_CFG_0, CLK_CFG_0_SET, 627 CLK_CFG_0_CLR, 16, 3, 628 CLK_CFG_UPDATE, TOP_MUX_IO_NOC_SHIFT), 629 MUX_CLR_SET_UPD(CLK_TOP_P_AXI, "p_axi", 630 shared_axi_parents, CLK_CFG_0, CLK_CFG_0_SET, 631 CLK_CFG_0_CLR, 24, 3, 632 CLK_CFG_UPDATE, TOP_MUX_PERI_AXI_SHIFT), 633 /* CLK_CFG_1 */ 634 MUX_CLR_SET_UPD(CLK_TOP_UFS_PEXTP0_AXI, "ufs_pextp0_axi", 635 shared_axi_parents, CLK_CFG_1, CLK_CFG_1_SET, 636 CLK_CFG_1_CLR, 0, 3, 637 CLK_CFG_UPDATE, TOP_MUX_UFS_PEXTP0_AXI_SHIFT), 638 MUX_CLR_SET_UPD(CLK_TOP_PEXTP1_USB_AXI, "pextp1_usb_axi", 639 shared_axi_parents, CLK_CFG_1, CLK_CFG_1_SET, 640 CLK_CFG_1_CLR, 8, 3, 641 CLK_CFG_UPDATE, TOP_MUX_PEXTP1_USB_AXI_SHIFT), 642 MUX_CLR_SET_UPD(CLK_TOP_P_FMEM_SUB, "p_fmem_sub", 643 shared_sub_parents, CLK_CFG_1, CLK_CFG_1_SET, 644 CLK_CFG_1_CLR, 16, 4, 645 CLK_CFG_UPDATE, TOP_MUX_PERI_FMEM_SUB_SHIFT), 646 MUX_CLR_SET_UPD(CLK_TOP_PEXPT0_MEM_SUB, "ufs_pexpt0_mem_sub", 647 shared_sub_parents, CLK_CFG_1, CLK_CFG_1_SET, 648 CLK_CFG_1_CLR, 24, 4, 649 CLK_CFG_UPDATE, TOP_MUX_UFS_PEXPT0_MEM_SUB_SHIFT), 650 /* CLK_CFG_2 */ 651 MUX_CLR_SET_UPD(CLK_TOP_PEXTP1_USB_MEM_SUB, "pextp1_usb_mem_sub", 652 shared_sub_parents, CLK_CFG_2, CLK_CFG_2_SET, 653 CLK_CFG_2_CLR, 0, 4, 654 CLK_CFG_UPDATE, TOP_MUX_PEXTP1_USB_MEM_SUB_SHIFT), 655 MUX_CLR_SET_UPD(CLK_TOP_P_NOC, "p_noc", 656 p_noc_parents, CLK_CFG_2, CLK_CFG_2_SET, 657 CLK_CFG_2_CLR, 8, 4, 658 CLK_CFG_UPDATE, TOP_MUX_PERI_NOC_SHIFT), 659 MUX_CLR_SET_UPD(CLK_TOP_EMI_N, "emi_n", 660 emi_parents, CLK_CFG_2, CLK_CFG_2_SET, 661 CLK_CFG_2_CLR, 16, 3, 662 CLK_CFG_UPDATE, TOP_MUX_EMI_N_SHIFT), 663 MUX_CLR_SET_UPD(CLK_TOP_EMI_S, "emi_s", 664 emi_parents, CLK_CFG_2, CLK_CFG_2_SET, 665 CLK_CFG_2_CLR, 24, 3, 666 CLK_CFG_UPDATE, TOP_MUX_EMI_S_SHIFT), 667 /* CLK_CFG_3 */ 668 MUX_CLR_SET_UPD(CLK_TOP_AP2CONN_HOST, "ap2conn_host", 669 ap2conn_host_parents, CLK_CFG_3, CLK_CFG_3_SET, 670 CLK_CFG_3_CLR, 16, 1, 671 CLK_CFG_UPDATE, TOP_MUX_AP2CONN_HOST_SHIFT), 672 MUX_CLR_SET_UPD(CLK_TOP_ATB, "atb", 673 atb_parents, CLK_CFG_3, CLK_CFG_3_SET, 674 CLK_CFG_3_CLR, 24, 2, 675 CLK_CFG_UPDATE, TOP_MUX_ATB_SHIFT), 676 /* CLK_CFG_4 */ 677 MUX_CLR_SET_UPD(CLK_TOP_CIRQ, "cirq", 678 cirq_parents, CLK_CFG_4, CLK_CFG_4_SET, 679 CLK_CFG_4_CLR, 0, 2, 680 CLK_CFG_UPDATE, TOP_MUX_CIRQ_SHIFT), 681 MUX_CLR_SET_UPD(CLK_TOP_PBUS_156M, "pbus_156m", 682 pbus_156m_parents, CLK_CFG_4, CLK_CFG_4_SET, 683 CLK_CFG_4_CLR, 8, 2, 684 CLK_CFG_UPDATE, TOP_MUX_PBUS_156M_SHIFT), 685 /* CLK_CFG_5 */ 686 MUX_CLR_SET_UPD(CLK_TOP_EFUSE, "efuse", 687 efuse_parents, CLK_CFG_5, CLK_CFG_5_SET, 688 CLK_CFG_5_CLR, 0, 1, 689 CLK_CFG_UPDATE, TOP_MUX_EFUSE_SHIFT), 690 MUX_CLR_SET_UPD(CLK_TOP_MCL3GIC, "mcu_l3gic", 691 mcu_l3gic_parents, CLK_CFG_5, CLK_CFG_5_SET, 692 CLK_CFG_5_CLR, 8, 2, 693 CLK_CFG_UPDATE, TOP_MUX_MCU_L3GIC_SHIFT), 694 MUX_CLR_SET_UPD(CLK_TOP_MCINFRA, "mcu_infra", 695 mcu_infra_parents, CLK_CFG_5, CLK_CFG_5_SET, 696 CLK_CFG_5_CLR, 16, 3, 697 CLK_CFG_UPDATE, TOP_MUX_MCU_INFRA_SHIFT), 698 MUX_CLR_SET_UPD(CLK_TOP_DSP, "dsp", 699 dsp_parents, CLK_CFG_5, CLK_CFG_5_SET, 700 CLK_CFG_5_CLR, 24, 3, 701 CLK_CFG_UPDATE, TOP_MUX_DSP_SHIFT), 702 /* CLK_CFG_6 */ 703 MUX_GATE_FENC_CLR_SET_UPD_FLAGS(CLK_TOP_MFG_REF, "mfg_ref", mfg_ref_parents, 704 NULL, ARRAY_SIZE(mfg_ref_parents), 705 CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 706 0, 1, 7, CLK_CFG_UPDATE, TOP_MUX_MFG_REF_SHIFT, 707 CLK_FENC_STATUS_MON_0, 7, CLK_IGNORE_UNUSED), 708 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_EB, "mfg_eb", 709 mfg_eb_parents, CLK_CFG_6, CLK_CFG_6_SET, 710 CLK_CFG_6_CLR, 16, 2, 711 23, CLK_CFG_UPDATE, TOP_MUX_MFG_EB_SHIFT), 712 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_UART, "uart", uart_parents, 713 CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 714 HWV_CG_3_DONE, HWV_CG_3_SET, HWV_CG_3_CLR, 715 24, 2, 31, CLK_CFG_UPDATE, TOP_MUX_UART_SHIFT, 716 CLK_FENC_STATUS_MON_0, 4), 717 /* CLK_CFG_7 */ 718 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI0_BCLK, "spi0_b", spi_b_parents, 719 CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 720 HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR, 721 0, 3, 7, CLK_CFG_UPDATE, TOP_MUX_SPI0_BCLK_SHIFT, 722 CLK_FENC_STATUS_MON_0, 3), 723 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI1_BCLK, "spi1_b", spi_b_parents, 724 CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 725 HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR, 726 8, 3, 15, CLK_CFG_UPDATE, TOP_MUX_SPI1_BCLK_SHIFT, 727 CLK_FENC_STATUS_MON_0, 2), 728 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI2_BCLK, "spi2_b", spi_b_parents, 729 CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 730 HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR, 731 16, 3, 23, CLK_CFG_UPDATE, TOP_MUX_SPI2_BCLK_SHIFT, 732 CLK_FENC_STATUS_MON_0, 1), 733 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI3_BCLK, "spi3_b", spi_b_parents, 734 CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 735 HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR, 736 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_SPI3_BCLK_SHIFT, 737 CLK_FENC_STATUS_MON_0, 0), 738 /* CLK_CFG_8 */ 739 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI4_BCLK, "spi4_b", spi_b_parents, 740 CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 741 HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR, 742 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_SPI4_BCLK_SHIFT, 743 CLK_FENC_STATUS_MON_1, 31), 744 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI5_BCLK, "spi5_b", spi_b_parents, 745 CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 746 HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR, 747 8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_SPI5_BCLK_SHIFT, 748 CLK_FENC_STATUS_MON_1, 30), 749 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI6_BCLK, "spi6_b", spi_b_parents, 750 CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 751 HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR, 752 16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_SPI6_BCLK_SHIFT, 753 CLK_FENC_STATUS_MON_1, 29), 754 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI7_BCLK, "spi7_b", spi_b_parents, 755 CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 756 HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR, 757 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_SPI7_BCLK_SHIFT, 758 CLK_FENC_STATUS_MON_1, 28), 759 /* CLK_CFG_9 */ 760 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1", msdc30_parents, 761 CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR, 762 16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_MSDC30_1_SHIFT, 763 CLK_FENC_STATUS_MON_1, 25), 764 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_MSDC30_2, "msdc30_2", msdc30_parents, 765 CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR, 766 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_MSDC30_2_SHIFT, 767 CLK_FENC_STATUS_MON_1, 24), 768 /* CLK_CFG_10 */ 769 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disp_pwm", disp_pwm_parents, 770 CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 771 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_DISP_PWM_SHIFT, 772 CLK_FENC_STATUS_MON_1, 23), 773 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_USB_TOP_1P, "usb_1p", usb_1p_parents, 774 CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 775 8, 1, 15, CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_1P_SHIFT, 776 CLK_FENC_STATUS_MON_1, 22), 777 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_USB_XHCI_1P, "usb_xhci_1p", usb_1p_parents, 778 CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 779 16, 1, 23, CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_1P_SHIFT, 780 CLK_FENC_STATUS_MON_1, 21), 781 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_USB_FMCNT_P1, "usb_fmcnt_p1", usb_fmcnt_p1_parents, 782 CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 783 24, 1, 31, CLK_CFG_UPDATE1, TOP_MUX_SSUSB_FMCNT_P1_SHIFT, 784 CLK_FENC_STATUS_MON_1, 20), 785 /* CLK_CFG_11 */ 786 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_I2C_P, "i2c_p", i2c_parents, 787 CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR, 788 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_I2C_PERI_SHIFT, 789 CLK_FENC_STATUS_MON_1, 19), 790 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_I2C_EAST, "i2c_east", i2c_parents, 791 CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR, 792 8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_I2C_EAST_SHIFT, 793 CLK_FENC_STATUS_MON_1, 18), 794 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_I2C_WEST, "i2c_west", i2c_parents, 795 CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR, 796 16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_I2C_WEST_SHIFT, 797 CLK_FENC_STATUS_MON_1, 17), 798 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_I2C_NORTH, "i2c_north", i2c_parents, 799 CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR, 800 HWV_CG_6_DONE, HWV_CG_6_SET, HWV_CG_6_CLR, 801 24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_I2C_NORTH_SHIFT, 802 CLK_FENC_STATUS_MON_1, 16), 803 /* CLK_CFG_12 */ 804 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_AES_UFSFDE, "aes_ufsfde", aes_ufsfde_parents, 805 CLK_CFG_12, CLK_CFG_12_SET, CLK_CFG_12_CLR, 806 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_AES_UFSFDE_SHIFT, 807 CLK_FENC_STATUS_MON_1, 15), 808 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_UFS, "ufs", ufs_parents, 809 CLK_CFG_12, CLK_CFG_12_SET, CLK_CFG_12_CLR, 810 8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_UFS_SHIFT, 811 CLK_FENC_STATUS_MON_1, 14), 812 /* CLK_CFG_13 */ 813 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1", aud_1_parents, 814 CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR, 815 0, 1, 7, CLK_CFG_UPDATE1, TOP_MUX_AUD_1_SHIFT, 816 CLK_FENC_STATUS_MON_1, 11), 817 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2", aud_2_parents, 818 CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR, 819 8, 1, 15, CLK_CFG_UPDATE1, TOP_MUX_AUD_2_SHIFT, 820 CLK_FENC_STATUS_MON_1, 10), 821 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_ADSP, "adsp", adsp_parents, 822 CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR, 823 16, 1, 23, CLK_CFG_UPDATE1, TOP_MUX_ADSP_SHIFT, 824 CLK_FENC_STATUS_MON_1, 9), 825 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_UARTHUB_B, "adsp_uarthub_b", 826 adsp_uarthub_b_parents, CLK_CFG_13, CLK_CFG_13_SET, 827 CLK_CFG_13_CLR, 24, 2, 31, 828 CLK_CFG_UPDATE1, TOP_MUX_ADSP_UARTHUB_B_SHIFT), 829 /* CLK_CFG_14 */ 830 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN, "dpmaif_main", dpmaif_main_parents, 831 CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR, 832 0, 4, 7, CLK_CFG_UPDATE1, TOP_MUX_DPMAIF_MAIN_SHIFT, 833 CLK_FENC_STATUS_MON_1, 7), 834 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_PWM, "pwm", pwm_parents, 835 CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR, 836 8, 2, 15, CLK_CFG_UPDATE1, TOP_MUX_PWM_SHIFT, 837 CLK_FENC_STATUS_MON_1, 6), 838 MUX_CLR_SET_UPD(CLK_TOP_MCUPM, "mcupm", 839 mcupm_parents, CLK_CFG_14, CLK_CFG_14_SET, 840 CLK_CFG_14_CLR, 16, 3, 841 CLK_CFG_UPDATE1, TOP_MUX_MCUPM_SHIFT), 842 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_SFLASH, "sflash", sflash_parents, 843 CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR, 844 24, 2, 31, CLK_CFG_UPDATE1, TOP_MUX_SFLASH_SHIFT, 845 CLK_FENC_STATUS_MON_1, 4), 846 /* CLK_CFG_15 */ 847 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_IPSEAST, "ipseast", ipseast_parents, 848 CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR, 849 0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_IPSEAST_SHIFT, 850 CLK_FENC_STATUS_MON_1, 3), 851 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_TL, "tl", tl_parents, 852 CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR, 853 16, 2, 23, CLK_CFG_UPDATE2, TOP_MUX_TL_SHIFT, 854 CLK_FENC_STATUS_MON_1, 1), 855 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_TL_P1, "tl_p1", tl_parents, 856 CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR, 857 24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_TL_P1_SHIFT, 858 CLK_FENC_STATUS_MON_1, 0), 859 /* CLK_CFG_16 */ 860 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_TL_P2, "tl_p2", tl_parents, 861 CLK_CFG_16, CLK_CFG_16_SET, CLK_CFG_16_CLR, 862 0, 2, 7, CLK_CFG_UPDATE2, TOP_MUX_TL_P2_SHIFT, 863 CLK_FENC_STATUS_MON_2, 31), 864 MUX_CLR_SET_UPD(CLK_TOP_EMI_INTERFACE_546, "emi_interface_546", 865 md_emi_parents, CLK_CFG_16, CLK_CFG_16_SET, 866 CLK_CFG_16_CLR, 8, 1, 867 CLK_CFG_UPDATE2, TOP_MUX_EMI_INTERFACE_546_SHIFT), 868 MUX_CLR_SET_UPD(CLK_TOP_SDF, "sdf", 869 sdf_parents, CLK_CFG_16, CLK_CFG_16_SET, 870 CLK_CFG_16_CLR, 16, 3, 871 CLK_CFG_UPDATE2, TOP_MUX_SDF_SHIFT), 872 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_UARTHUB_BCLK, "uarthub_b", uarthub_b_parents, 873 CLK_CFG_16, CLK_CFG_16_SET, CLK_CFG_16_CLR, 874 HWV_CG_7_DONE, HWV_CG_7_SET, HWV_CG_7_CLR, 875 24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_UARTHUB_BCLK_SHIFT, 876 CLK_FENC_STATUS_MON_2, 28), 877 /* CLK_CFG_17 */ 878 MUX_CLR_SET_UPD(CLK_TOP_DPSW_CMP_26M, "dpsw_cmp_26m", 879 dpsw_cmp_26m_parents, CLK_CFG_17, CLK_CFG_17_SET, 880 CLK_CFG_17_CLR, 0, 1, 881 CLK_CFG_UPDATE2, TOP_MUX_DPSW_CMP_26M_SHIFT), 882 MUX_CLR_SET_UPD(CLK_TOP_SMAP, "smap", 883 smapparents, CLK_CFG_17, CLK_CFG_17_SET, 884 CLK_CFG_17_CLR, 8, 1, 885 CLK_CFG_UPDATE2, TOP_MUX_SMAPCK_SHIFT), 886 MUX_CLR_SET_UPD(CLK_TOP_SSR_PKA, "ssr_pka", 887 ssr_parents, CLK_CFG_17, CLK_CFG_17_SET, 888 CLK_CFG_17_CLR, 16, 3, 889 CLK_CFG_UPDATE2, TOP_MUX_SSR_PKA_SHIFT), 890 MUX_CLR_SET_UPD(CLK_TOP_SSR_DMA, "ssr_dma", 891 ssr_parents, CLK_CFG_17, CLK_CFG_17_SET, 892 CLK_CFG_17_CLR, 24, 3, 893 CLK_CFG_UPDATE2, TOP_MUX_SSR_DMA_SHIFT), 894 /* CLK_CFG_18 */ 895 MUX_CLR_SET_UPD(CLK_TOP_SSR_KDF, "ssr_kdf", 896 ssr_kdf_parents, CLK_CFG_18, CLK_CFG_18_SET, 897 CLK_CFG_18_CLR, 0, 2, 898 CLK_CFG_UPDATE2, TOP_MUX_SSR_KDF_SHIFT), 899 MUX_CLR_SET_UPD(CLK_TOP_SSR_RNG, "ssr_rng", 900 ssr_rng_parents, CLK_CFG_18, CLK_CFG_18_SET, 901 CLK_CFG_18_CLR, 8, 2, 902 CLK_CFG_UPDATE2, TOP_MUX_SSR_RNG_SHIFT), 903 MUX_CLR_SET_UPD(CLK_TOP_SPU0, "spu0", 904 spu_parents, CLK_CFG_18, CLK_CFG_18_SET, 905 CLK_CFG_18_CLR, 16, 3, 906 CLK_CFG_UPDATE2, TOP_MUX_SPU0_SHIFT), 907 MUX_CLR_SET_UPD(CLK_TOP_SPU1, "spu1", 908 spu_parents, CLK_CFG_18, CLK_CFG_18_SET, 909 CLK_CFG_18_CLR, 24, 3, 910 CLK_CFG_UPDATE2, TOP_MUX_SPU1_SHIFT), 911 /* CLK_CFG_19 */ 912 MUX_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc", 913 dxcc_parents, CLK_CFG_19, CLK_CFG_19_SET, 914 CLK_CFG_19_CLR, 0, 2, 915 CLK_CFG_UPDATE2, TOP_MUX_DXCC_SHIFT), 916 }; 917 918 static const struct mtk_composite top_aud_divs[] = { 919 /* CLK_AUDDIV_2 */ 920 MUX_DIV_GATE(CLK_TOP_APLL_I2SIN0, "apll_i2sin0_m", apll_m_parents, 921 CLK_AUDDIV_0, 16, 1, CLK_AUDDIV_2, 0, 8, CLK_AUDDIV_0, 0), 922 MUX_DIV_GATE(CLK_TOP_APLL_I2SIN1, "apll_i2sin1_m", apll_m_parents, 923 CLK_AUDDIV_0, 17, 1, CLK_AUDDIV_2, 8, 8, CLK_AUDDIV_0, 1), 924 MUX_DIV_GATE(CLK_TOP_APLL_I2SIN2, "apll_i2sin2_m", apll_m_parents, 925 CLK_AUDDIV_0, 18, 1, CLK_AUDDIV_2, 16, 8, CLK_AUDDIV_0, 2), 926 MUX_DIV_GATE(CLK_TOP_APLL_I2SIN3, "apll_i2sin3_m", apll_m_parents, 927 CLK_AUDDIV_0, 19, 1, CLK_AUDDIV_2, 24, 8, CLK_AUDDIV_0, 3), 928 /* CLK_AUDDIV_3 */ 929 MUX_DIV_GATE(CLK_TOP_APLL_I2SIN4, "apll_i2sin4_m", apll_m_parents, 930 CLK_AUDDIV_0, 20, 1, CLK_AUDDIV_3, 0, 8, CLK_AUDDIV_0, 4), 931 MUX_DIV_GATE(CLK_TOP_APLL_I2SIN6, "apll_i2sin6_m", apll_m_parents, 932 CLK_AUDDIV_0, 21, 1, CLK_AUDDIV_3, 8, 8, CLK_AUDDIV_0, 5), 933 MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT0, "apll_i2sout0_m", apll_m_parents, 934 CLK_AUDDIV_0, 22, 1, CLK_AUDDIV_3, 16, 8, CLK_AUDDIV_0, 6), 935 MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT1, "apll_i2sout1_m", apll_m_parents, 936 CLK_AUDDIV_0, 23, 1, CLK_AUDDIV_3, 24, 8, CLK_AUDDIV_0, 7), 937 /* CLK_AUDDIV_4 */ 938 MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT2, "apll_i2sout2_m", apll_m_parents, 939 CLK_AUDDIV_0, 24, 1, CLK_AUDDIV_4, 0, 8, CLK_AUDDIV_0, 8), 940 MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT3, "apll_i2sout3_m", apll_m_parents, 941 CLK_AUDDIV_0, 25, 1, CLK_AUDDIV_4, 8, 8, CLK_AUDDIV_0, 9), 942 MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT4, "apll_i2sout4_m", apll_m_parents, 943 CLK_AUDDIV_0, 26, 1, CLK_AUDDIV_4, 16, 8, CLK_AUDDIV_0, 10), 944 MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT6, "apll_i2sout6_m", apll_m_parents, 945 CLK_AUDDIV_0, 27, 1, CLK_AUDDIV_4, 24, 8, CLK_AUDDIV_0, 11), 946 /* CLK_AUDDIV_5 */ 947 MUX_DIV_GATE(CLK_TOP_APLL_FMI2S, "apll_fmi2s_m", apll_m_parents, 948 CLK_AUDDIV_0, 28, 1, CLK_AUDDIV_5, 0, 8, CLK_AUDDIV_0, 12), 949 MUX(CLK_TOP_APLL_TDMOUT, "apll_tdmout_m", 950 apll_m_parents, CLK_AUDDIV_0, 29, 1), 951 DIV_GATE(CLK_TOP_APLL12_DIV_TDMOUT_M, "apll12_div_tdmout_m", 952 "apll_tdmout_m", CLK_AUDDIV_0, 953 13, CLK_AUDDIV_5, 8, 8), 954 DIV_GATE(CLK_TOP_APLL12_DIV_TDMOUT_B, "apll12_div_tdmout_b", 955 "apll_tdmout_m", CLK_AUDDIV_0, 956 14, CLK_AUDDIV_5, 8, 16), 957 }; 958 959 static const struct mtk_clk_desc topck_desc = { 960 .factor_clks = top_divs, 961 .num_factor_clks = ARRAY_SIZE(top_divs), 962 .mux_clks = top_muxes, 963 .num_mux_clks = ARRAY_SIZE(top_muxes), 964 .composite_clks = top_aud_divs, 965 .num_composite_clks = ARRAY_SIZE(top_aud_divs) 966 }; 967 968 static const struct of_device_id of_match_clk_mt8196_ck[] = { 969 { .compatible = "mediatek,mt8196-topckgen", .data = &topck_desc }, 970 { /* sentinel */ } 971 }; 972 MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_ck); 973 974 static struct platform_driver clk_mt8196_topck_drv = { 975 .probe = mtk_clk_simple_probe, 976 .remove = mtk_clk_simple_remove, 977 .driver = { 978 .name = "clk-mt8196-topck", 979 .of_match_table = of_match_clk_mt8196_ck, 980 }, 981 }; 982 983 MODULE_DESCRIPTION("MediaTek MT8196 top clock generators driver"); 984 module_platform_driver(clk_mt8196_topck_drv); 985 MODULE_LICENSE("GPL"); 986