1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025 MediaTek Inc. 4 * Guangjie Song <guangjie.song@mediatek.com> 5 * Copyright (c) 2025 Collabora Ltd. 6 * Laura Nao <laura.nao@collabora.com> 7 */ 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h> 9 10 #include <linux/clk-provider.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 15 #include "clk-gate.h" 16 #include "clk-mtk.h" 17 18 static const struct mtk_gate_regs mm0_cg_regs = { 19 .set_ofs = 0x104, 20 .clr_ofs = 0x108, 21 .sta_ofs = 0x100, 22 }; 23 24 static const struct mtk_gate_regs mm0_hwv_regs = { 25 .set_ofs = 0x0020, 26 .clr_ofs = 0x0024, 27 .sta_ofs = 0x2c10, 28 }; 29 30 static const struct mtk_gate_regs mm1_cg_regs = { 31 .set_ofs = 0x114, 32 .clr_ofs = 0x118, 33 .sta_ofs = 0x110, 34 }; 35 36 static const struct mtk_gate_regs mm1_hwv_regs = { 37 .set_ofs = 0x0028, 38 .clr_ofs = 0x002c, 39 .sta_ofs = 0x2c14, 40 }; 41 42 #define GATE_MM0(_id, _name, _parent, _shift) { \ 43 .id = _id, \ 44 .name = _name, \ 45 .parent_name = _parent, \ 46 .regs = &mm0_cg_regs, \ 47 .shift = _shift, \ 48 .flags = CLK_OPS_PARENT_ENABLE, \ 49 .ops = &mtk_clk_gate_ops_setclr,\ 50 } 51 52 #define GATE_HWV_MM0(_id, _name, _parent, _shift) { \ 53 .id = _id, \ 54 .name = _name, \ 55 .parent_name = _parent, \ 56 .regs = &mm0_cg_regs, \ 57 .hwv_regs = &mm0_hwv_regs, \ 58 .shift = _shift, \ 59 .ops = &mtk_clk_gate_hwv_ops_setclr, \ 60 .flags = CLK_OPS_PARENT_ENABLE \ 61 } 62 63 #define GATE_MM1(_id, _name, _parent, _shift) { \ 64 .id = _id, \ 65 .name = _name, \ 66 .parent_name = _parent, \ 67 .regs = &mm1_cg_regs, \ 68 .shift = _shift, \ 69 .flags = CLK_OPS_PARENT_ENABLE, \ 70 .ops = &mtk_clk_gate_ops_setclr,\ 71 } 72 73 #define GATE_HWV_MM1(_id, _name, _parent, _shift) { \ 74 .id = _id, \ 75 .name = _name, \ 76 .parent_name = _parent, \ 77 .regs = &mm1_cg_regs, \ 78 .hwv_regs = &mm1_hwv_regs, \ 79 .shift = _shift, \ 80 .ops = &mtk_clk_gate_hwv_ops_setclr, \ 81 .flags = CLK_OPS_PARENT_ENABLE, \ 82 } 83 84 static const struct mtk_gate mm_clks[] = { 85 /* MM0 */ 86 GATE_HWV_MM0(CLK_MM_CONFIG, "mm_config", "disp", 0), 87 GATE_HWV_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp", 1), 88 GATE_HWV_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp", 2), 89 GATE_HWV_MM0(CLK_MM_DISP_AAL1, "mm_disp_aal1", "disp", 3), 90 GATE_MM0(CLK_MM_DISP_C3D0, "mm_disp_c3d0", "disp", 4), 91 GATE_MM0(CLK_MM_DISP_C3D1, "mm_disp_c3d1", "disp", 5), 92 GATE_MM0(CLK_MM_DISP_C3D2, "mm_disp_c3d2", "disp", 6), 93 GATE_MM0(CLK_MM_DISP_C3D3, "mm_disp_c3d3", "disp", 7), 94 GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp", 8), 95 GATE_MM0(CLK_MM_DISP_CCORR1, "mm_disp_ccorr1", "disp", 9), 96 GATE_MM0(CLK_MM_DISP_CCORR2, "mm_disp_ccorr2", "disp", 10), 97 GATE_MM0(CLK_MM_DISP_CCORR3, "mm_disp_ccorr3", "disp", 11), 98 GATE_MM0(CLK_MM_DISP_CHIST0, "mm_disp_chist0", "disp", 12), 99 GATE_MM0(CLK_MM_DISP_CHIST1, "mm_disp_chist1", "disp", 13), 100 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp", 14), 101 GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "disp", 15), 102 GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp", 16), 103 GATE_MM0(CLK_MM_DISP_DITHER1, "mm_disp_dither1", "disp", 17), 104 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC0, "mm_disp_dli_async0", "disp", 18), 105 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC1, "mm_disp_dli_async1", "disp", 19), 106 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC2, "mm_disp_dli_async2", "disp", 20), 107 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC3, "mm_disp_dli_async3", "disp", 21), 108 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC4, "mm_disp_dli_async4", "disp", 22), 109 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC5, "mm_disp_dli_async5", "disp", 23), 110 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC6, "mm_disp_dli_async6", "disp", 24), 111 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC7, "mm_disp_dli_async7", "disp", 25), 112 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC8, "mm_disp_dli_async8", "disp", 26), 113 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC9, "mm_disp_dli_async9", "disp", 27), 114 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC10, "mm_disp_dli_async10", "disp", 28), 115 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC11, "mm_disp_dli_async11", "disp", 29), 116 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC12, "mm_disp_dli_async12", "disp", 30), 117 GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC13, "mm_disp_dli_async13", "disp", 31), 118 /* MM1 */ 119 GATE_HWV_MM1(CLK_MM_DISP_DLI_ASYNC14, "mm_disp_dli_async14", "disp", 0), 120 GATE_HWV_MM1(CLK_MM_DISP_DLI_ASYNC15, "mm_disp_dli_async15", "disp", 1), 121 GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC0, "mm_disp_dlo_async0", "disp", 2), 122 GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC1, "mm_disp_dlo_async1", "disp", 3), 123 GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC2, "mm_disp_dlo_async2", "disp", 4), 124 GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC3, "mm_disp_dlo_async3", "disp", 5), 125 GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC4, "mm_disp_dlo_async4", "disp", 6), 126 GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC5, "mm_disp_dlo_async5", "disp", 7), 127 GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC6, "mm_disp_dlo_async6", "disp", 8), 128 GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC7, "mm_disp_dlo_async7", "disp", 9), 129 GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC8, "mm_disp_dlo_async8", "disp", 10), 130 GATE_MM1(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp", 11), 131 GATE_MM1(CLK_MM_DISP_GAMMA1, "mm_disp_gamma1", "disp", 12), 132 GATE_MM1(CLK_MM_MDP_AAL0, "mm_mdp_aal0", "disp", 13), 133 GATE_MM1(CLK_MM_MDP_AAL1, "mm_mdp_aal1", "disp", 14), 134 GATE_HWV_MM1(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "disp", 15), 135 GATE_HWV_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp", 16), 136 GATE_HWV_MM1(CLK_MM_DISP_POSTMASK1, "mm_disp_postmask1", "disp", 17), 137 GATE_HWV_MM1(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "disp", 18), 138 GATE_HWV_MM1(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "disp", 19), 139 GATE_HWV_MM1(CLK_MM_DISP_SPR0, "mm_disp_spr0", "disp", 20), 140 GATE_MM1(CLK_MM_DISP_TDSHP0, "mm_disp_tdshp0", "disp", 21), 141 GATE_MM1(CLK_MM_DISP_TDSHP1, "mm_disp_tdshp1", "disp", 22), 142 GATE_HWV_MM1(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp", 23), 143 GATE_HWV_MM1(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp", 24), 144 GATE_HWV_MM1(CLK_MM_SMI_SUB_COMM0, "mm_ssc", "disp", 25), 145 GATE_HWV_MM1(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp", 26), 146 }; 147 148 static const struct mtk_clk_desc mm_mcd = { 149 .clks = mm_clks, 150 .num_clks = ARRAY_SIZE(mm_clks), 151 }; 152 153 static const struct platform_device_id clk_mt8196_disp0_id_table[] = { 154 { .name = "clk-mt8196-disp0", .driver_data = (kernel_ulong_t)&mm_mcd }, 155 { /* sentinel */ } 156 }; 157 MODULE_DEVICE_TABLE(platform, clk_mt8196_disp0_id_table); 158 159 static struct platform_driver clk_mt8196_disp0_drv = { 160 .probe = mtk_clk_pdev_probe, 161 .remove = mtk_clk_pdev_remove, 162 .driver = { 163 .name = "clk-mt8196-disp0", 164 }, 165 .id_table = clk_mt8196_disp0_id_table, 166 }; 167 module_platform_driver(clk_mt8196_disp0_drv); 168 169 MODULE_DESCRIPTION("MediaTek MT8196 disp0 clocks driver"); 170 MODULE_LICENSE("GPL"); 171