Home
last modified time | relevance | path

Searched +full:msi +full:- +full:map (Results 1 – 25 of 386) sorted by relevance

12345678910>>...16

/linux/Documentation/devicetree/bindings/pci/
H A Dpci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/pci-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Kishon Vijay Abraham I <kishon@kernel.org>
14 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 pattern: "^pcie-ep@"
20 iommu-map:
21 $ref: /schemas/types.yaml#/definitions/uint32-matrix
24 - description: Device ID (see msi-map) base
[all …]
H A Dxlnx,nwl-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
[all …]
H A Dxilinx-versal-cpm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
20 - xlnx,versal-cpm5-host1
21 - xlnx,versal-cpm5nc-host
[all …]
H A Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
26 the standard "reset-gpios" and "max-link-speed" properties appear on
38 - items:
39 - enum:
40 - apple,t8103-pcie
41 - apple,t8112-pcie
42 - apple,t6000-pcie
[all …]
H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim Quinlan <james.quinlan@broadcom.com>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm2712-pcie # Raspberry Pi 5
18 - brcm,bcm4908-pcie
19 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
[all …]
H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <jianjun.wang@mediatek.com>
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
[all …]
H A Damd,versal2-mdb-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/pci/snps,dw-pcie.yaml#
18 const: amd,versal2-mdb-host
22 - description: MDB System Level Control and Status Register (SLCR) Base
23 - description: configuration region
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
[all …]
/linux/drivers/pci/msi/
H A Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
14 #include "msi.h"
17 * pci_enable_msi() - Enable MSI interrupt mode on device
20 * Legacy device driver API to enable MSI interrupts mode on device and
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dxlnx,versal-net-cdx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 on run-time.
18 and a unique device ID (for MSI) corresponding to a requestor ID
20 are used to configure SMMU and GIC-ITS respectively.
22 iommu-map property is used to define the set of stream ids
25 The MSI writes are accompanied by sideband data (Device ID).
26 The msi-map property is used to associate the devices with the
[all …]
/linux/drivers/pci/endpoint/
H A Dpci-epc-core.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pci-epc.h>
14 #include <linux/pci-epf.h>
15 #include <linux/pci-ep-cfs.h>
29 * pci_epc_put() - release the PCI endpoint controller
39 module_put(epc->ops->owner); in pci_epc_put()
40 put_device(&epc->dev); in pci_epc_put()
45 * pci_epc_get() - get the PCI endpoint controller
53 int ret = -EINVAL; in pci_epc_get()
62 if (try_module_get(epc->ops->owner)) in pci_epc_get()
[all …]
/linux/virt/kvm/
H A Dirqchip.c1 // SPDX-License-Identifier: GPL-2.0-only
28 irq_rt = srcu_dereference_check(kvm->irq_routing, &kvm->irq_srcu, in kvm_irq_map_gsi()
29 lockdep_is_held(&kvm->irq_lock)); in kvm_irq_map_gsi()
30 if (irq_rt && gsi < irq_rt->nr_rt_entries) { in kvm_irq_map_gsi()
31 hlist_for_each_entry(e, &irq_rt->map[gsi], link) { in kvm_irq_map_gsi()
44 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); in kvm_irq_map_chip_pin()
45 return irq_rt->chip[irqchip][pin]; in kvm_irq_map_chip_pin()
48 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi) in kvm_send_userspace_msi() argument
52 if (!kvm_arch_irqchip_in_kernel(kvm) || (msi->flags & ~KVM_MSI_VALID_DEVID)) in kvm_send_userspace_msi()
53 return -EINVAL; in kvm_send_userspace_msi()
[all …]
/linux/kernel/irq/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/msi.h>
26 * struct msi_device_data - MSI per device data
27 * @properties: MSI properties which are interesting to drivers
28 * @mutex: Mutex protecting the MSI descriptor store
29 * @__domains: Internal data for per device MSI domains
40 * struct msi_ctrl - MSI internal management control structure
45 * than the range due to PCI/multi-MSI.
55 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
66 * msi_alloc_desc - Allocate an initialized msi_desc
[all …]
/linux/drivers/irqchip/
H A Dirq-gic-its-msi-parent.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
11 #include "irq-gic-its-msi-parent.h"
12 #include <linux/irqchip/irq-msi-lib.h>
27 ret = of_property_match_string(msi_node, "reg-names", "ns-translate"); in its_translate_frame_address()
42 int msi, msix, *count = data; in its_pci_msi_vec_count() local
44 msi = max(pci_msi_vec_count(pdev), 0); in its_pci_msi_vec_count()
46 *count += max(msi, msix); in its_pci_msi_vec_count()
68 return -EINVAL; in its_pci_msi_prepare()
73 * bound of how many other vectors could map to the same DevID. in its_pci_msi_prepare()
[all …]
/linux/drivers/pci/controller/plda/
H A Dpcie-plda-host.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/irqchip/irq-msi-lib.h>
16 #include <linux/msi.h>
18 #include <linux/pci-ecam.h>
21 #include "pcie-plda.h"
26 struct plda_pcie_rp *pcie = bus->sysdata; in plda_pcie_map_bus()
28 return pcie->config_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in plda_pcie_map_bus()
36 struct device *dev = port->dev; in plda_handle_msi()
37 struct plda_msi *msi = &port->msi; in plda_handle_msi() local
38 void __iomem *bridge_base_addr = port->bridge_addr; in plda_handle_msi()
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8641si-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
22 mcm-law@0 {
[all …]
/linux/include/linux/
H A Dpci-epc.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pci-epf.h>
17 UNKNOWN_INTERFACE = -1,
36 * struct pci_epc_map - information about EPC memory for mapping a RC PCI
38 * @pci_addr: start address of the RC PCI address range to map
65 * struct pci_epc_ops - set of function pointers for performing EPC operations
70 * into a controller memory window needed to map an RC PCI address
72 * @map_addr: ops to map CPU address to PCI address
74 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
76 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
[all …]
/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
15 #include <linux/irqchip/irq-msi-lib.h>
20 #include <linux/msi.h>
26 #include "pcie-mobiveil.h"
38 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
45 * mobiveil_pcie_map_bus - routine to get the configuration base of either
51 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
52 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
60 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dmorello-sdp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
6 /dts-v1/;
11 compatible = "arm,morello-sdp", "arm,morello";
18 stdout-path = "serial0:115200n8";
21 dpu_aclk: clock-350000000 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <350000000>;
26 clock-output-names = "aclk";
[all …]
/linux/arch/loongarch/boot/dts/
H A Dloongson-2k2000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
34 ref_100m: clock-ref-100m {
35 compatible = "fixed-clock";
[all …]
/linux/drivers/pci/controller/
H A Dpcie-xilinx-dma-pl.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/irqchip/irq-msi-lib.h>
14 #include <linux/msi.h>
19 #include "pcie-xilinx-common.h"
47 IMR(MSI) | \
77 /* Number of MSI IRQs */
86 * struct xilinx_pl_dma_variant - PL DMA PCIe variant information
102 * struct pl_dma_pcie - PCIe port information
112 * @msi: MSI information
127 struct xilinx_msi msi; member
[all …]
/linux/arch/powerpc/sysdev/
H A Dfsl_msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
11 #include <linux/msi.h>
24 #include <asm/ppc-pci.h>
39 #define msi_hwirq(msi, msir_index, intr_index) \ argument
40 ((msir_index) << (msi)->srs_shift | \
41 ((intr_index) << (msi)->ibs_shift))
63 * in the cascade interrupt. So, this MSI interrupt has been acked
71 struct fsl_msi *msi_data = irqd->domain->host_data; in fsl_msi_print_chip()
75 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK; in fsl_msi_print_chip()
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
[all …]
/linux/arch/powerpc/platforms/44x/
H A Dhsta_msi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MSI support for PPC4xx SoCs using High Speed Transfer Assist (HSTA) for
11 #include <linux/msi.h>
18 #include <asm/ppc-pci.h>
23 /* The ioremapped HSTA MSI IO space */
26 /* Physical address of HSTA MSI IO space */
45 /* We don't support MSI-X */ in hsta_setup_msi_irqs()
47 pr_debug("%s: MSI-X not supported.\n", __func__); in hsta_setup_msi_irqs()
48 return -EINVAL; in hsta_setup_msi_irqs()
51 msi_for_each_desc(entry, &dev->dev, MSI_DESC_NOTASSOCIATED) { in hsta_setup_msi_irqs()
[all …]

12345678910>>...16