Lines Matching +full:msi +full:- +full:map
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/irqchip/irq-msi-lib.h>
14 #include <linux/msi.h>
19 #include "pcie-xilinx-common.h"
47 IMR(MSI) | \
77 /* Number of MSI IRQs */
86 * struct xilinx_pl_dma_variant - PL DMA PCIe variant information
102 * struct pl_dma_pcie - PCIe port information
112 * @msi: MSI information
127 struct xilinx_msi msi; member
135 if (port->variant->version == QDMA) in pcie_read()
136 return readl(port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); in pcie_read()
138 return readl(port->reg_base + reg); in pcie_read()
143 if (port->variant->version == QDMA) in pcie_write()
144 writel(val, port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); in pcie_write()
146 writel(val, port->reg_base + reg); in pcie_write()
160 dev_dbg(port->dev, "Requester ID %lu\n", in xilinx_pl_dma_pcie_clear_err_interrupts()
170 struct pl_dma_pcie *port = bus->sysdata; in xilinx_pl_dma_pcie_valid_device()
181 * go down between the link-up check and the PIO request. in xilinx_pl_dma_pcie_valid_device()
195 struct pl_dma_pcie *port = bus->sysdata; in xilinx_pl_dma_pcie_map_bus()
200 if (port->variant->version == QDMA) in xilinx_pl_dma_pcie_map_bus()
201 return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in xilinx_pl_dma_pcie_map_bus()
203 return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in xilinx_pl_dma_pcie_map_bus()
217 phys_addr_t msi_addr = port->phys_reg_base; in xilinx_pl_dma_pcie_enable_msi()
229 mask = BIT(data->hwirq + XILINX_PCIE_DMA_IDRN_SHIFT); in xilinx_mask_intx_irq()
230 raw_spin_lock_irqsave(&port->lock, flags); in xilinx_mask_intx_irq()
233 raw_spin_unlock_irqrestore(&port->lock, flags); in xilinx_mask_intx_irq()
242 mask = BIT(data->hwirq + XILINX_PCIE_DMA_IDRN_SHIFT); in xilinx_unmask_intx_irq()
243 raw_spin_lock_irqsave(&port->lock, flags); in xilinx_unmask_intx_irq()
246 raw_spin_unlock_irqrestore(&port->lock, flags); in xilinx_unmask_intx_irq()
259 irq_set_chip_data(irq, domain->host_data); in xilinx_pl_dma_pcie_intx_map()
267 .map = xilinx_pl_dma_pcie_intx_map,
272 struct xilinx_msi *msi; in xilinx_pl_dma_pcie_msi_handler_high() local
277 msi = &port->msi; in xilinx_pl_dma_pcie_msi_handler_high()
283 virq = irq_find_mapping(msi->dev_domain, bit); in xilinx_pl_dma_pcie_msi_handler_high()
295 struct xilinx_msi *msi; in xilinx_pl_dma_pcie_msi_handler_low() local
299 msi = &port->msi; in xilinx_pl_dma_pcie_msi_handler_low()
304 virq = irq_find_mapping(msi->dev_domain, bit); in xilinx_pl_dma_pcie_msi_handler_low()
322 generic_handle_domain_irq(port->pldma_domain, i); in xilinx_pl_dma_pcie_event_flow()
355 struct device *dev = port->dev; in xilinx_pl_dma_pcie_intr_handler()
358 d = irq_domain_get_irq_data(port->pldma_domain, irq); in xilinx_pl_dma_pcie_intr_handler()
359 switch (d->hwirq) { in xilinx_pl_dma_pcie_intr_handler()
367 if (intr_cause[d->hwirq].str) in xilinx_pl_dma_pcie_intr_handler()
368 dev_warn(dev, "%s\n", intr_cause[d->hwirq].str); in xilinx_pl_dma_pcie_intr_handler()
370 dev_warn(dev, "Unknown IRQ %ld\n", d->hwirq); in xilinx_pl_dma_pcie_intr_handler()
387 .prefix = "pl_dma-",
393 phys_addr_t msi_addr = pcie->phys_reg_base; in xilinx_compose_msi_msg()
395 msg->address_lo = lower_32_bits(msi_addr); in xilinx_compose_msi_msg()
396 msg->address_hi = upper_32_bits(msi_addr); in xilinx_compose_msi_msg()
397 msg->data = data->hwirq; in xilinx_compose_msi_msg()
401 .name = "pl_dma:MSI",
408 struct pl_dma_pcie *pcie = domain->host_data; in xilinx_irq_domain_alloc()
409 struct xilinx_msi *msi = &pcie->msi; in xilinx_irq_domain_alloc() local
412 mutex_lock(&msi->lock); in xilinx_irq_domain_alloc()
413 bit = bitmap_find_free_region(msi->bitmap, XILINX_NUM_MSI_IRQS, in xilinx_irq_domain_alloc()
416 mutex_unlock(&msi->lock); in xilinx_irq_domain_alloc()
417 return -ENOSPC; in xilinx_irq_domain_alloc()
422 domain->host_data, handle_simple_irq, in xilinx_irq_domain_alloc()
425 mutex_unlock(&msi->lock); in xilinx_irq_domain_alloc()
435 struct xilinx_msi *msi = &pcie->msi; in xilinx_irq_domain_free() local
437 mutex_lock(&msi->lock); in xilinx_irq_domain_free()
438 bitmap_release_region(msi->bitmap, data->hwirq, in xilinx_irq_domain_free()
440 mutex_unlock(&msi->lock); in xilinx_irq_domain_free()
450 struct xilinx_msi *msi = &port->msi; in xilinx_pl_dma_pcie_free_irq_domains() local
452 if (port->intx_domain) { in xilinx_pl_dma_pcie_free_irq_domains()
453 irq_domain_remove(port->intx_domain); in xilinx_pl_dma_pcie_free_irq_domains()
454 port->intx_domain = NULL; in xilinx_pl_dma_pcie_free_irq_domains()
457 if (msi->dev_domain) { in xilinx_pl_dma_pcie_free_irq_domains()
458 irq_domain_remove(msi->dev_domain); in xilinx_pl_dma_pcie_free_irq_domains()
459 msi->dev_domain = NULL; in xilinx_pl_dma_pcie_free_irq_domains()
465 struct device *dev = port->dev; in xilinx_pl_dma_pcie_init_msi_irq_domain()
466 struct xilinx_msi *msi = &port->msi; in xilinx_pl_dma_pcie_init_msi_irq_domain() local
469 .fwnode = dev_fwnode(port->dev), in xilinx_pl_dma_pcie_init_msi_irq_domain()
475 msi->dev_domain = msi_create_parent_irq_domain(&info, &xilinx_msi_parent_ops); in xilinx_pl_dma_pcie_init_msi_irq_domain()
476 if (!msi->dev_domain) in xilinx_pl_dma_pcie_init_msi_irq_domain()
479 mutex_init(&msi->lock); in xilinx_pl_dma_pcie_init_msi_irq_domain()
480 msi->bitmap = kzalloc(size, GFP_KERNEL); in xilinx_pl_dma_pcie_init_msi_irq_domain()
481 if (!msi->bitmap) in xilinx_pl_dma_pcie_init_msi_irq_domain()
484 raw_spin_lock_init(&port->lock); in xilinx_pl_dma_pcie_init_msi_irq_domain()
491 dev_err(dev, "Failed to allocate MSI IRQ domains\n"); in xilinx_pl_dma_pcie_init_msi_irq_domain()
493 return -ENOMEM; in xilinx_pl_dma_pcie_init_msi_irq_domain()
512 generic_handle_domain_irq(port->intx_domain, i); in xilinx_pl_dma_pcie_intx_flow()
521 raw_spin_lock(&port->lock); in xilinx_pl_dma_pcie_mask_event_irq()
523 val &= ~BIT(d->hwirq); in xilinx_pl_dma_pcie_mask_event_irq()
525 raw_spin_unlock(&port->lock); in xilinx_pl_dma_pcie_mask_event_irq()
533 raw_spin_lock(&port->lock); in xilinx_pl_dma_pcie_unmask_event_irq()
535 val |= BIT(d->hwirq); in xilinx_pl_dma_pcie_unmask_event_irq()
537 raw_spin_unlock(&port->lock); in xilinx_pl_dma_pcie_unmask_event_irq()
541 .name = "pl_dma:RC-Event",
551 irq_set_chip_data(irq, domain->host_data); in xilinx_pl_dma_pcie_event_map()
558 .map = xilinx_pl_dma_pcie_event_map,
562 * xilinx_pl_dma_pcie_init_irq_domain - Initialize IRQ domain
569 struct device *dev = port->dev; in xilinx_pl_dma_pcie_init_irq_domain()
570 struct device_node *node = dev->of_node; in xilinx_pl_dma_pcie_init_irq_domain()
575 pcie_intc_node = of_get_child_by_name(node, "interrupt-controller"); in xilinx_pl_dma_pcie_init_irq_domain()
578 return -EINVAL; in xilinx_pl_dma_pcie_init_irq_domain()
581 port->pldma_domain = irq_domain_create_linear(of_fwnode_handle(pcie_intc_node), 32, in xilinx_pl_dma_pcie_init_irq_domain()
583 if (!port->pldma_domain) in xilinx_pl_dma_pcie_init_irq_domain()
584 return -ENOMEM; in xilinx_pl_dma_pcie_init_irq_domain()
586 irq_domain_update_bus_token(port->pldma_domain, DOMAIN_BUS_NEXUS); in xilinx_pl_dma_pcie_init_irq_domain()
588 port->intx_domain = irq_domain_create_linear(of_fwnode_handle(pcie_intc_node), PCI_NUM_INTX, in xilinx_pl_dma_pcie_init_irq_domain()
590 if (!port->intx_domain) { in xilinx_pl_dma_pcie_init_irq_domain()
592 return -ENOMEM; in xilinx_pl_dma_pcie_init_irq_domain()
595 irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); in xilinx_pl_dma_pcie_init_irq_domain()
599 irq_domain_remove(port->intx_domain); in xilinx_pl_dma_pcie_init_irq_domain()
600 return -ENOMEM; in xilinx_pl_dma_pcie_init_irq_domain()
604 raw_spin_lock_init(&port->lock); in xilinx_pl_dma_pcie_init_irq_domain()
611 struct device *dev = port->dev; in xilinx_pl_dma_pcie_setup_irq()
615 port->irq = platform_get_irq(pdev, 0); in xilinx_pl_dma_pcie_setup_irq()
616 if (port->irq < 0) in xilinx_pl_dma_pcie_setup_irq()
617 return port->irq; in xilinx_pl_dma_pcie_setup_irq()
625 irq = irq_create_mapping(port->pldma_domain, i); in xilinx_pl_dma_pcie_setup_irq()
627 dev_err(dev, "Failed to map interrupt\n"); in xilinx_pl_dma_pcie_setup_irq()
628 return -ENXIO; in xilinx_pl_dma_pcie_setup_irq()
641 port->intx_irq = irq_create_mapping(port->pldma_domain, in xilinx_pl_dma_pcie_setup_irq()
643 if (!port->intx_irq) { in xilinx_pl_dma_pcie_setup_irq()
644 dev_err(dev, "Failed to map INTx interrupt\n"); in xilinx_pl_dma_pcie_setup_irq()
645 return -ENXIO; in xilinx_pl_dma_pcie_setup_irq()
648 err = devm_request_irq(dev, port->intx_irq, xilinx_pl_dma_pcie_intx_flow, in xilinx_pl_dma_pcie_setup_irq()
651 dev_err(dev, "Failed to request INTx IRQ %d\n", port->intx_irq); in xilinx_pl_dma_pcie_setup_irq()
655 err = devm_request_irq(dev, port->irq, xilinx_pl_dma_pcie_event_flow, in xilinx_pl_dma_pcie_setup_irq()
658 dev_err(dev, "Failed to request event IRQ %d\n", port->irq); in xilinx_pl_dma_pcie_setup_irq()
668 dev_info(port->dev, "PCIe Link is UP\n"); in xilinx_pl_dma_pcie_init_port()
670 dev_info(port->dev, "PCIe Link is DOWN\n"); in xilinx_pl_dma_pcie_init_port()
681 /* Needed for MSI DECODE MODE */ in xilinx_pl_dma_pcie_init_port()
695 struct device *dev = port->dev; in xilinx_request_msi_irq()
699 port->msi.irq_msi0 = platform_get_irq_byname(pdev, "msi0"); in xilinx_request_msi_irq()
700 if (port->msi.irq_msi0 <= 0) in xilinx_request_msi_irq()
701 return port->msi.irq_msi0; in xilinx_request_msi_irq()
703 ret = devm_request_irq(dev, port->msi.irq_msi0, xilinx_pl_dma_pcie_msi_handler_low, in xilinx_request_msi_irq()
704 IRQF_SHARED | IRQF_NO_THREAD, "xlnx-pcie-dma-pl", in xilinx_request_msi_irq()
711 port->msi.irq_msi1 = platform_get_irq_byname(pdev, "msi1"); in xilinx_request_msi_irq()
712 if (port->msi.irq_msi1 <= 0) in xilinx_request_msi_irq()
713 return port->msi.irq_msi1; in xilinx_request_msi_irq()
715 ret = devm_request_irq(dev, port->msi.irq_msi1, xilinx_pl_dma_pcie_msi_handler_high, in xilinx_request_msi_irq()
716 IRQF_SHARED | IRQF_NO_THREAD, "xlnx-pcie-dma-pl", in xilinx_request_msi_irq()
729 struct device *dev = port->dev; in xilinx_pl_dma_pcie_parse_dt()
737 return -ENXIO; in xilinx_pl_dma_pcie_parse_dt()
739 port->phys_reg_base = res->start; in xilinx_pl_dma_pcie_parse_dt()
741 port->cfg = pci_ecam_create(dev, res, bus_range, &xilinx_pl_dma_pcie_ops); in xilinx_pl_dma_pcie_parse_dt()
742 if (IS_ERR(port->cfg)) in xilinx_pl_dma_pcie_parse_dt()
743 return PTR_ERR(port->cfg); in xilinx_pl_dma_pcie_parse_dt()
745 port->reg_base = port->cfg->win; in xilinx_pl_dma_pcie_parse_dt()
747 if (port->variant->version == QDMA) { in xilinx_pl_dma_pcie_parse_dt()
748 port->cfg_base = port->cfg->win; in xilinx_pl_dma_pcie_parse_dt()
750 port->reg_base = devm_ioremap_resource(dev, res); in xilinx_pl_dma_pcie_parse_dt()
751 if (IS_ERR(port->reg_base)) in xilinx_pl_dma_pcie_parse_dt()
752 return PTR_ERR(port->reg_base); in xilinx_pl_dma_pcie_parse_dt()
753 port->phys_reg_base = res->start; in xilinx_pl_dma_pcie_parse_dt()
758 pci_ecam_free(port->cfg); in xilinx_pl_dma_pcie_parse_dt()
767 struct device *dev = &pdev->dev; in xilinx_pl_dma_pcie_probe()
775 return -ENODEV; in xilinx_pl_dma_pcie_probe()
779 port->dev = dev; in xilinx_pl_dma_pcie_probe()
781 bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); in xilinx_pl_dma_pcie_probe()
783 return -ENODEV; in xilinx_pl_dma_pcie_probe()
785 port->variant = of_device_get_match_data(dev); in xilinx_pl_dma_pcie_probe()
787 err = xilinx_pl_dma_pcie_parse_dt(port, bus->res); in xilinx_pl_dma_pcie_probe()
801 bridge->sysdata = port; in xilinx_pl_dma_pcie_probe()
802 bridge->ops = &xilinx_pl_dma_pcie_ops.pci_ops; in xilinx_pl_dma_pcie_probe()
814 pci_ecam_free(port->cfg); in xilinx_pl_dma_pcie_probe()
828 .compatible = "xlnx,xdma-host-3.00",
832 .compatible = "xlnx,qdma-host-3.00",
840 .name = "xilinx-xdma-pcie",