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Searched +full:mpfs +full:- +full:clock (Results 1 – 21 of 21) sorted by relevance

/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
11 compatible = "microchip,mpfs";
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
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H A Dmpfs-polarberry.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
4 /dts-v1/;
6 #include "mpfs.dtsi"
7 #include "mpfs-polarberry-fabric.dtsi"
11 compatible = "sundance,polarberry", "microchip,mpfs";
19 stdout-path = "serial0:115200n8";
38 phy-mode = "sgmii";
39 phy-handle = <&phy0>;
44 phy-mode = "sgmii";
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H A Dmpfs-sev-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include "mpfs.dtsi"
7 #include "mpfs-sev-kit-fabric.dtsi"
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "Microchip PolarFire-SoC SEV Kit";
13 compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
25 stdout-path = "serial1:115200n8";
28 reserved-memory {
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H A Dmpfs-tysom-m.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2020-2022 - Aldec
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
9 /dts-v1/;
11 #include "mpfs.dtsi"
12 #include "mpfs-tysom-m-fabric.dtsi"
15 model = "Aldec TySOM-M-MPFS250T-REV2";
16 compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
31 stdout-path = "serial1:115200n8";
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H A Dmpfs-m100pfsevp.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
8 /dts-v1/;
10 #include "mpfs.dtsi"
11 #include "mpfs-m100pfs-fabric.dtsi"
15 compatible = "aries,m100pfsevp", "microchip,mpfs";
30 stdout-path = "serial1:115200n8";
63 pmic-irq-hog {
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/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,mpfs-clkcfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire Clock Control Module
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
17 user nodes by the CLKCFG node phandle and the clock index in the group, from
22 const: microchip,mpfs-clkcfg
26 - description: |
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H A Dmicrochip,mpfs-ccc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
10 - Conor Dooley <conor.dooley@microchip.com>
13 Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
24 - description: PLL0's control registers
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/linux/Documentation/devicetree/bindings/rtc/
H A Dmicrochip,mpfs-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/microchip,mpfs-rtc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip PolarFire Soc (MPFS) RTC
11 - $ref: rtc.yaml#
14 - Daire McNamara <daire.mcnamara@microchip.com>
19 - items:
20 - const: microchip,pic64gx-rtc
21 - const: microchip,mpfs-rtc
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/linux/Documentation/devicetree/bindings/spi/
H A Dmicrochip,mpfs-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Conor Dooley <conor.dooley@microchip.com>
19 - items:
20 - enum:
21 - microchip,mpfs-qspi
22 - microchip,pic64gx-qspi
23 - const: microchip,coreqspi-rtl-v2
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/linux/drivers/reset/
H A Dreset-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PolarFire SoC (MPFS) Peripheral Clock Reset Controller
16 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/microchip,mpfs-clock.h>
18 #include <soc/microchip/mpfs.h>
22 * defines in the dt to make things easier to configure - so this is accounting
44 * Peripheral clock resets
54 reg = readl(rst->base); in mpfs_assert()
56 writel(reg, rst->base); in mpfs_assert()
71 reg = readl(rst->base); in mpfs_deassert()
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/linux/drivers/clk/microchip/
H A Dclk-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PolarFire SoC MSS/core complex clock control
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/microchip,mpfs-clock.h>
12 #include <soc/microchip/mpfs.h>
34 * This clock ID is defined here, rather than the binding headers, as it is an
35 * internal clock only, and therefore has no consumers in other peripheral
84 * mpfs clk block while a software locked register is being written.
103 * The only two supported reference clock frequencies for the PolarFire SoC are
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H A Dclk-mpfs-ccc.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/microchip,mpfs-clock.h>
76 void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset; in mpfs_ccc_pll_recalc_rate()
77 void __iomem *ref_div_addr = ccc_hw->base + MPFS_CCC_REF_CR; in mpfs_ccc_pll_recalc_rate()
91 void __iomem *pll_cr_addr = ccc_hw->base + MPFS_CCC_PLL_CR; in mpfs_ccc_pll_get_parent()
167 char *name = devm_kasprintf(dev, GFP_KERNEL, "%s_out%u", parent->name, i); in mpfs_ccc_register_outputs()
170 return -ENOMEM; in mpfs_ccc_register_outputs()
172 out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0); in mpfs_ccc_register_outputs()
173 out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] + in mpfs_ccc_register_outputs()
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/linux/drivers/usb/musb/
H A Dmpfs.c1 // SPDX-License-Identifier: GPL-2.0
3 * PolarFire SoC (MPFS) MUSB Glue Layer
5 * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
11 #include <linux/dma-mapping.h>
61 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); in mpfs_musb_set_vbus()
64 musb->is_active = 1; in mpfs_musb_set_vbus()
65 musb->xceiv->otg->default_a = 1; in mpfs_musb_set_vbus()
66 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; in mpfs_musb_set_vbus()
70 musb->is_active = 0; in mpfs_musb_set_vbus()
73 * NOTE: skipping A_WAIT_VFALL -> A_IDLE and in mpfs_musb_set_vbus()
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/linux/Documentation/devicetree/bindings/mmc/
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - microchip,pic64gx-sd4hc
19 - mobileye,eyeq-sd4hc
20 - socionext,uniphier-sd4hc
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/linux/drivers/rtc/
H A Drtc-mpfs.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip MPFS RTC driver
5 * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved.
65 ctrl = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_start()
68 writel(ctrl, rtcdev->base + CONTROL_REG); in mpfs_rtc_start()
73 u32 val = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
77 writel(val, rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
83 (void)readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
91 time = readl(rtcdev->base + DATETIME_LOWER_REG); in mpfs_rtc_readtime()
92 time |= ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32; in mpfs_rtc_readtime()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 bool "Real Time Clock"
29 If you say yes here, the system time (wall clock) will be set using
39 clock, usually rtc0. Initialization is done when the system
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
46 system will need an external clock source (like an NTP server).
48 If the clock you specify here is not battery backed, it may still
57 If you say yes here, the system time (wall clock) will be stored
112 Say yes here if you want to use your system clock RTC through
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/linux/drivers/pci/controller/plda/
H A Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
21 #include <linux/pci-ecam.h>
26 #include "../pci-host-common.h"
27 #include "pcie-plda.h"
301 struct plda_msi *msi = &port->plda.msi; in mc_pcie_enable_msi()
316 writel_relaxed(lower_32_bits(msi->vector_phy), in mc_pcie_enable_msi()
318 writel_relaxed(upper_32_bits(msi->vector_phy), in mc_pcie_enable_msi()
329 u32 reg = readl_relaxed(port->ctrl_base_addr + PCIE_EVENT_INT); in pcie_events()
341 u32 reg = readl_relaxed(port->ctrl_base_addr + SEC_ERROR_INT); in sec_errors()
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/linux/drivers/i2c/busses/
H A Di2c-microchip-corei2c.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018-2022 Microchip Corporation. All rights reserved.
93 * struct mchp_corei2c_dev - Microchip CoreI2C device private data
97 * @i2c_clk: clock reference for i2c input clock
103 * @bus_clk_rate: current i2c bus clock rate
131 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_disable()
134 writeb(ctrl, idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_disable()
139 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_enable()
142 writeb(ctrl, idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_enable()
153 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_stop()
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/linux/include/linux/mlx5/
H A Ddriver.h2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
39 #include <linux/pci-tph.h>
229 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
389 #define MLX5_24BIT_MASK ((1 << 24) - 1)
601 struct mlx5_mpfs *mpfs; member
775 struct mlx5_clock *clock; member
886 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
892 return ioread32be(&dev->iseg->fw_rev) & 0xffff; in fw_rev_maj()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dmain.c2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
54 #include "lib/mpfs.h"
62 #include "lib/clock.h"
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
91 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
197 fw_initializing = ioread32be(&dev->iseg->initializing); in wait_fw_init()
203 return -ETIMEDOUT; in wait_fw_init()
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/linux/drivers/net/ethernet/cadence/
H A Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
23 #include <linux/dma-mapping.h>
37 #include <linux/firmware/xlnx-zynqmp.h>
61 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
72 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
88 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
127 switch (bp->hw_dma_cap) { in macb_dma_desc_get_size()
152 switch (bp->hw_dma_cap) { in macb_adj_dma_desc_idx()
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