/linux/arch/riscv/boot/dts/microchip/ |
H A D | mpfs.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 8 #address-cells = <2>; 9 #size-cells = <2>; 11 compatible = "microchip,mpfs"; 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <1000000>; [all …]
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H A D | mpfs-icicle-kit-fabric.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 5 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", 6 "microchip,mpfs"; 9 compatible = "microchip,corepwm-rtl-v4"; 11 microchip,sync-update-mask = /bits/ 32 <0>; 12 #pwm-cells = <3>; 18 compatible = "microchip,corei2c-rtl-v7"; 20 #address-cells = <1>; 21 #size-cells = <0>; [all …]
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H A D | mpfs-beaglev-fire.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 6 #include <dt-bindings/gpio/gpio.h> 7 #include "mpfs.dtsi" 8 #include "mpfs-beaglev-fire-fabric.dtsi" 10 /* Clock frequency (in Hz) of MTIMER */ 14 #address-cells = <2>; 15 #size-cells = <2>; 16 model = "BeagleBoard BeagleV-Fire"; [all …]
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H A D | mpfs-polarberry.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2022 Microchip Technology Inc */ 4 /dts-v1/; 6 #include "mpfs.dtsi" 7 #include "mpfs-polarberry-fabric.dtsi" 11 compatible = "sundance,polarberry", "microchip,mpfs"; 19 stdout-path = "serial0:115200n8"; 38 phy-mode = "sgmii"; 39 phy-handle = <&phy0>; 44 phy-mode = "sgmii"; [all …]
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H A D | mpfs-sev-kit.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 /dts-v1/; 6 #include "mpfs.dtsi" 7 #include "mpfs-sev-kit-fabric.dtsi" 10 #address-cells = <2>; 11 #size-cells = <2>; 12 model = "Microchip PolarFire-SoC SEV Kit"; 13 compatible = "microchip,mpfs-sev-kit", "microchip,mpfs"; 25 stdout-path = "serial1:115200n8"; 28 reserved-memory { [all …]
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H A D | mpfs-tysom-m.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * Original all-in-one devicetree: 4 * Copyright (C) 2020-2022 - Aldec 6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com> 9 /dts-v1/; 11 #include "mpfs.dtsi" 12 #include "mpfs-tysom-m-fabric.dtsi" 15 model = "Aldec TySOM-M-MPFS250T-REV2"; 16 compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs"; 31 stdout-path = "serial1:115200n8"; [all …]
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H A D | mpfs-m100pfsevp.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * Original all-in-one devicetree: 4 * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de> 6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com> 8 /dts-v1/; 10 #include "mpfs.dtsi" 11 #include "mpfs-m100pfs-fabric.dtsi" 15 compatible = "aries,m100pfsevp", "microchip,mpfs"; 30 stdout-path = "serial1:115200n8"; 63 pmic-irq-hog { [all …]
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/linux/Documentation/devicetree/bindings/clock/ |
H A D | microchip,mpfs-clkcfg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip PolarFire Clock Control Module 10 - Daire McNamara <daire.mcnamara@microchip.com> 13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller, 17 user nodes by the CLKCFG node phandle and the clock index in the group, from 22 const: microchip,mpfs-clkcfg 26 - description: | [all …]
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H A D | microchip,mpfs-ccc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry 10 - Conor Dooley <conor.dooley@microchip.com> 13 Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of 16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html 20 const: microchip,mpfs-ccc 24 - description: PLL0's control registers [all …]
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/linux/Documentation/devicetree/bindings/rtc/ |
H A D | microchip,mpfs-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/rtc/microchip,mpfs-rtc.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Microchip PolarFire Soc (MPFS) RTC 11 - $ref: rtc.yaml# 14 - Daire McNamara <daire.mcnamara@microchip.com> 19 - items: 20 - const: microchip,pic64gx-rtc 21 - const: microchip,mpfs-rtc [all …]
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/linux/Documentation/devicetree/bindings/spi/ |
H A D | microchip,mpfs-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 14 - Conor Dooley <conor.dooley@microchip.com> 19 - items: 20 - enum: 21 - microchip,mpfs-qspi 22 - microchip,pic64gx-qspi 23 - const: microchip,coreqspi-rtl-v2 [all …]
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/linux/drivers/reset/ |
H A D | reset-mpfs.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * PolarFire SoC (MPFS) Peripheral Clock Reset Controller 16 #include <linux/reset-controller.h> 17 #include <dt-bindings/clock/microchip,mpfs-clock.h> 18 #include <soc/microchip/mpfs.h> 22 * defines in the dt to make things easier to configure - so this is accounting 44 * Peripheral clock resets 54 reg = readl(rst->base); in mpfs_assert() 56 writel(reg, rst->base); in mpfs_assert() 71 reg = readl(rst->base); in mpfs_deassert() [all …]
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/linux/drivers/clk/microchip/ |
H A D | clk-mpfs.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * PolarFire SoC MSS/core complex clock control 5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. 7 #include <linux/clk-provider.h> 11 #include <dt-bindings/clock/microchip,mpfs-clock.h> 12 #include <soc/microchip/mpfs.h> 34 * This clock ID is defined here, rather than the binding headers, as it is an 35 * internal clock only, and therefore has no consumers in other peripheral 84 * mpfs clk block while a software locked register is being written. 103 * The only two supported reference clock frequencies for the PolarFire SoC are [all …]
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H A D | clk-mpfs-ccc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/clk-provider.h> 12 #include <dt-bindings/clock/microchip,mpfs-clock.h> 76 void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset; in mpfs_ccc_pll_recalc_rate() 77 void __iomem *ref_div_addr = ccc_hw->base + MPFS_CCC_REF_CR; in mpfs_ccc_pll_recalc_rate() 91 void __iomem *pll_cr_addr = ccc_hw->base + MPFS_CCC_PLL_CR; in mpfs_ccc_pll_get_parent() 167 char *name = devm_kasprintf(dev, GFP_KERNEL, "%s_out%u", parent->name, i); in mpfs_ccc_register_outputs() 170 return -ENOMEM; in mpfs_ccc_register_outputs() 172 out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0); in mpfs_ccc_register_outputs() 173 out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] + in mpfs_ccc_register_outputs() [all …]
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/linux/drivers/rtc/ |
H A D | rtc-mpfs.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Microchip MPFS RTC driver 5 * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved. 65 ctrl = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_start() 68 writel(ctrl, rtcdev->base + CONTROL_REG); in mpfs_rtc_start() 73 u32 val = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq() 77 writel(val, rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq() 83 (void)readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq() 91 time = readl(rtcdev->base + DATETIME_LOWER_REG); in mpfs_rtc_readtime() 92 time |= ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32; in mpfs_rtc_readtime() [all …]
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H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 14 bool "Real Time Clock" 29 If you say yes here, the system time (wall clock) will be set using 39 clock, usually rtc0. Initialization is done when the system 44 This clock should be battery-backed, so that it reads the correct 45 time when the system boots from a power-off state. Otherwise, your 46 system will need an external clock source (like an NTP server). 48 If the clock you specify here is not battery backed, it may still 57 If you say yes here, the system time (wall clock) will be stored 112 Say yes here if you want to use your system clock RTC through [all …]
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/linux/Documentation/devicetree/bindings/net/ |
H A D | cdns,macb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Claudiu Beznea <claudiu.beznea@microchip.com> 16 - items: 17 - enum: 18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC 19 - const: cdns,emac # Generic 21 - items: [all …]
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/linux/drivers/spi/ |
H A D | spi-microchip-core.c | 1 // SPDX-License-Identifier: (GPL-2.0) 5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries 107 u32 clk_gen; /* divider for spi output clock generated by the controller */ 118 return readl(spi->regs + reg); in mchp_corespi_read() 123 writel(val, spi->regs + reg); in mchp_corespi_write() 145 spi->rx_len -= spi->n_bytes; in mchp_corespi_read_fifo() 147 if (!spi->rx_buf) in mchp_corespi_read_fifo() 150 if (spi->n_bytes == 4) in mchp_corespi_read_fifo() 151 *((u32 *)spi->rx_buf) = data; in mchp_corespi_read_fifo() 152 else if (spi->n_bytes == 2) in mchp_corespi_read_fifo() [all …]
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/linux/drivers/i2c/busses/ |
H A D | i2c-microchip-corei2c.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (c) 2018-2022 Microchip Corporation. All rights reserved. 91 * struct mchp_corei2c_dev - Microchip CoreI2C device private data 95 * @i2c_clk: clock reference for i2c input clock 101 * @bus_clk_rate: current i2c bus clock rate 129 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_disable() 132 writeb(ctrl, idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_disable() 137 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_enable() 140 writeb(ctrl, idev->base + CORE_I2C_CTRL); in mchp_corei2c_core_enable() 151 u8 ctrl = readb(idev->base + CORE_I2C_CTRL); in mchp_corei2c_stop() [all …]
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/linux/include/linux/mlx5/ |
H A D | driver.h | 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 14 * - Redistributions of source code must retain the above 18 * - Redistributions in binary form must reproduce the above 227 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ 385 #define MLX5_24BIT_MASK ((1 << 24) - 1) 597 struct mlx5_mpfs *mpfs; member 792 struct mlx5_clock clock; member 900 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 906 return ioread32be(&dev->iseg->fw_rev) & 0xffff; in fw_rev_maj() 911 return ioread32be(&dev->iseg->fw_rev) >> 16; in fw_rev_min() [all …]
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/linux/ |
H A D | MAINTAINERS | 5 --------------------------------------------------- 21 W: *Web-page* with status/info 23 B: URI for where to file *bugs*. A web-page with detailed bug 28 patches to the given subsystem. This is either an in-tree file, 29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst 46 N: [^a-z]tegra all files whose path contains tegra 64 ---------------- 83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS) 85 L: linux-scsi@vger.kernel.org 88 F: drivers/scsi/3w-* [all …]
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/linux/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
H A D | counters.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 13 - `Overview`_ 14 - `Groups`_ 15 - `Types`_ 16 - `Descriptions`_ 27 ---------------------------------------- 29 ---------------------------------------- ---------------------------------------- | 32 | ------------------- --------------- | | ------------------- --------------- | | 34 | ------------------- --------------- | | ------------------- --------------- | | 36 | ------------------- | | ------------------- | | [all …]
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/linux/drivers/net/ethernet/cadence/ |
H A D | macb_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2004-2006 Atmel Corporation 10 #include <linux/clk-provider.h> 25 #include <linux/dma-mapping.h> 40 #include <linux/firmware/xlnx-zynqmp.h> 58 * (bp)->rx_ring_size) 64 * (bp)->tx_ring_size) 67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4) 78 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -… 94 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) [all …]
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