106efe648SMasahiro Yamada# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 206efe648SMasahiro Yamada%YAML 1.2 306efe648SMasahiro Yamada--- 406efe648SMasahiro Yamada$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml# 506efe648SMasahiro Yamada$schema: http://devicetree.org/meta-schemas/core.yaml# 606efe648SMasahiro Yamada 706efe648SMasahiro Yamadatitle: Cadence SD/SDIO/eMMC Host Controller (SD4HC) 806efe648SMasahiro Yamada 906efe648SMasahiro Yamadamaintainers: 1006efe648SMasahiro Yamada - Masahiro Yamada <yamada.masahiro@socionext.com> 1106efe648SMasahiro Yamada 1206efe648SMasahiro Yamadaproperties: 1306efe648SMasahiro Yamada compatible: 1406efe648SMasahiro Yamada items: 1506efe648SMasahiro Yamada - enum: 16*82e4726bSBrad Larson - amd,pensando-elba-sd4hc 1784723eecSKrzysztof Kozlowski - microchip,mpfs-sd4hc 1806efe648SMasahiro Yamada - socionext,uniphier-sd4hc 1906efe648SMasahiro Yamada - const: cdns,sd4hc 2006efe648SMasahiro Yamada 2106efe648SMasahiro Yamada reg: 22*82e4726bSBrad Larson minItems: 1 23*82e4726bSBrad Larson maxItems: 2 2406efe648SMasahiro Yamada 2506efe648SMasahiro Yamada interrupts: 2606efe648SMasahiro Yamada maxItems: 1 2706efe648SMasahiro Yamada 2806efe648SMasahiro Yamada clocks: 2906efe648SMasahiro Yamada maxItems: 1 3006efe648SMasahiro Yamada 31cb7f0901SKunihiko Hayashi resets: 32cb7f0901SKunihiko Hayashi maxItems: 1 33cb7f0901SKunihiko Hayashi 3406efe648SMasahiro Yamada # PHY DLL input delays: 3506efe648SMasahiro Yamada # They are used to delay the data valid window, and align the window to 3606efe648SMasahiro Yamada # sampling clock. The delay starts from 5ns (for delay parameter equal to 0) 3706efe648SMasahiro Yamada # and it is increased by 2.5ns in each step. 3806efe648SMasahiro Yamada 3906efe648SMasahiro Yamada cdns,phy-input-delay-sd-highspeed: 4006efe648SMasahiro Yamada description: Value of the delay in the input path for SD high-speed timing 411e52a7e6SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 423d21a460SRob Herring minimum: 0 433d21a460SRob Herring maximum: 0x1f 4406efe648SMasahiro Yamada 4506efe648SMasahiro Yamada cdns,phy-input-delay-legacy: 4606efe648SMasahiro Yamada description: Value of the delay in the input path for legacy timing 471e52a7e6SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 483d21a460SRob Herring minimum: 0 493d21a460SRob Herring maximum: 0x1f 5006efe648SMasahiro Yamada 5106efe648SMasahiro Yamada cdns,phy-input-delay-sd-uhs-sdr12: 5206efe648SMasahiro Yamada description: Value of the delay in the input path for SD UHS SDR12 timing 531e52a7e6SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 543d21a460SRob Herring minimum: 0 553d21a460SRob Herring maximum: 0x1f 5606efe648SMasahiro Yamada 5706efe648SMasahiro Yamada cdns,phy-input-delay-sd-uhs-sdr25: 5806efe648SMasahiro Yamada description: Value of the delay in the input path for SD UHS SDR25 timing 591e52a7e6SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 603d21a460SRob Herring minimum: 0 613d21a460SRob Herring maximum: 0x1f 6206efe648SMasahiro Yamada 6306efe648SMasahiro Yamada cdns,phy-input-delay-sd-uhs-sdr50: 6406efe648SMasahiro Yamada description: Value of the delay in the input path for SD UHS SDR50 timing 651e52a7e6SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 663d21a460SRob Herring minimum: 0 673d21a460SRob Herring maximum: 0x1f 6806efe648SMasahiro Yamada 6906efe648SMasahiro Yamada cdns,phy-input-delay-sd-uhs-ddr50: 7006efe648SMasahiro Yamada description: Value of the delay in the input path for SD UHS DDR50 timing 711e52a7e6SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 723d21a460SRob Herring minimum: 0 733d21a460SRob Herring maximum: 0x1f 7406efe648SMasahiro Yamada 7506efe648SMasahiro Yamada cdns,phy-input-delay-mmc-highspeed: 7606efe648SMasahiro Yamada description: Value of the delay in the input path for MMC high-speed timing 771e52a7e6SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 783d21a460SRob Herring minimum: 0 793d21a460SRob Herring maximum: 0x1f 8006efe648SMasahiro Yamada 8106efe648SMasahiro Yamada cdns,phy-input-delay-mmc-ddr: 8206efe648SMasahiro Yamada description: Value of the delay in the input path for eMMC high-speed DDR timing 8306efe648SMasahiro Yamada 8406efe648SMasahiro Yamada # PHY DLL clock delays: 8506efe648SMasahiro Yamada # Each delay property represents the fraction of the clock period. 8606efe648SMasahiro Yamada # The approximate delay value will be 8706efe648SMasahiro Yamada # (<delay property value>/128)*sdmclk_clock_period. 881e52a7e6SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 893d21a460SRob Herring minimum: 0 903d21a460SRob Herring maximum: 0x1f 9106efe648SMasahiro Yamada 9206efe648SMasahiro Yamada cdns,phy-dll-delay-sdclk: 9306efe648SMasahiro Yamada description: | 9406efe648SMasahiro Yamada Value of the delay introduced on the sdclk output for all modes except 9506efe648SMasahiro Yamada HS200, HS400 and HS400_ES. 961e52a7e6SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 973d21a460SRob Herring minimum: 0 983d21a460SRob Herring maximum: 0x7f 9906efe648SMasahiro Yamada 10006efe648SMasahiro Yamada cdns,phy-dll-delay-sdclk-hsmmc: 10106efe648SMasahiro Yamada description: | 10206efe648SMasahiro Yamada Value of the delay introduced on the sdclk output for HS200, HS400 and 10306efe648SMasahiro Yamada HS400_ES speed modes. 1041e52a7e6SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 1053d21a460SRob Herring minimum: 0 1063d21a460SRob Herring maximum: 0x7f 10706efe648SMasahiro Yamada 10806efe648SMasahiro Yamada cdns,phy-dll-delay-strobe: 10906efe648SMasahiro Yamada description: | 11006efe648SMasahiro Yamada Value of the delay introduced on the dat_strobe input used in 11106efe648SMasahiro Yamada HS400 / HS400_ES speed modes. 1121e52a7e6SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 1133d21a460SRob Herring minimum: 0 1143d21a460SRob Herring maximum: 0x7f 11506efe648SMasahiro Yamada 11606efe648SMasahiro Yamadarequired: 11706efe648SMasahiro Yamada - compatible 11806efe648SMasahiro Yamada - reg 11906efe648SMasahiro Yamada - interrupts 12006efe648SMasahiro Yamada - clocks 12106efe648SMasahiro Yamada 122*82e4726bSBrad LarsonallOf: 123*82e4726bSBrad Larson - $ref: mmc-controller.yaml 124*82e4726bSBrad Larson - if: 125*82e4726bSBrad Larson properties: 126*82e4726bSBrad Larson compatible: 127*82e4726bSBrad Larson contains: 128*82e4726bSBrad Larson const: amd,pensando-elba-sd4hc 129*82e4726bSBrad Larson then: 130*82e4726bSBrad Larson properties: 131*82e4726bSBrad Larson reg: 132*82e4726bSBrad Larson items: 133*82e4726bSBrad Larson - description: Host controller registers 134*82e4726bSBrad Larson - description: Elba byte-lane enable register for writes 135*82e4726bSBrad Larson required: 136*82e4726bSBrad Larson - resets 137*82e4726bSBrad Larson else: 138*82e4726bSBrad Larson properties: 139*82e4726bSBrad Larson reg: 140*82e4726bSBrad Larson maxItems: 1 141*82e4726bSBrad Larson 1426fdc6e23SRob HerringunevaluatedProperties: false 1436fdc6e23SRob Herring 14406efe648SMasahiro Yamadaexamples: 14506efe648SMasahiro Yamada - | 14606efe648SMasahiro Yamada emmc: mmc@5a000000 { 14706efe648SMasahiro Yamada compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 14806efe648SMasahiro Yamada reg = <0x5a000000 0x400>; 14906efe648SMasahiro Yamada interrupts = <0 78 4>; 15006efe648SMasahiro Yamada clocks = <&clk 4>; 15106efe648SMasahiro Yamada bus-width = <8>; 15206efe648SMasahiro Yamada mmc-ddr-1_8v; 15306efe648SMasahiro Yamada mmc-hs200-1_8v; 15406efe648SMasahiro Yamada mmc-hs400-1_8v; 15506efe648SMasahiro Yamada cdns,phy-dll-delay-sdclk = <0>; 15606efe648SMasahiro Yamada }; 157