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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsocionext,uniphier-clock.yaml27 - description: Media I/O (MIO) clock, SD clock
29 - socionext,uniphier-ld4-mio-clock
30 - socionext,uniphier-pro4-mio-clock
31 - socionext,uniphier-sld8-mio-clock
34 - socionext,uniphier-ld11-mio-clock
H A Dxlnx,zynqmp-clk.txt33 order to provide an optional (E)MIO clock source:
H A Dzynq-7000.txt33 order to provide an optional (E)MIO clock source.
/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dsocionext,uniphier-reset.yaml27 - description: Media I/O (MIO) reset, SD reset
29 - socionext,uniphier-ld4-mio-reset
30 - socionext,uniphier-pro4-mio-reset
31 - socionext,uniphier-sld8-mio-reset
34 - socionext,uniphier-ld11-mio-reset
/freebsd/sys/contrib/device-tree/Bindings/soc/socionext/
H A Dsocionext,uniphier-mioctrl.yaml7 title: Socionext UniPhier media I/O block (MIO) controller
15 SD/eMMC, and MIO-DMAC.
55 compatible = "socionext,uniphier-ld11-mio-clock";
60 compatible = "socionext,uniphier-ld11-mio-reset";
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dsocionext,uniphier-mio-dmac.yaml4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
21 const: socionext,uniphier-mio-dmac
56 compatible = "socionext,uniphier-mio-dmac";
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dxlnx,zynqmp-pinctrl.yaml49 pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
57 - pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
265 pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
289 This will internally disable the tri-state for MIO pins.
293 Selects the drive strength for MIO pins, in mA.
H A Dnvidia,tegra20-pinmux.yaml62 gmi_int, hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio,
H A Dnvidia,tegra30-pinmux.txt99 i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, invalid, kbc, mio, nand,
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBundle.h87 /// for (MIBundleOperands MIO(MI); MIO.isValid(); ++MIO) {
88 /// if (!MIO->isReg())
/freebsd/sys/contrib/device-tree/include/dt-bindings/pinctrl/
H A Dpinctrl-zynq.h3 * MIO pin configuration defines for Xilinx Zynq
H A Dpinctrl-zynqmp.h3 * MIO pin configuration defines for Xilinx ZynqMP
/freebsd/sys/contrib/device-tree/src/arm/socionext/
H A Duniphier-ld4.dtsi216 compatible = "socionext,uniphier-ld4-mio-clock";
221 compatible = "socionext,uniphier-ld4-mio-reset";
243 compatible = "socionext,uniphier-mio-dmac";
H A Duniphier-sld8.dtsi220 compatible = "socionext,uniphier-sld8-mio-clock";
225 compatible = "socionext,uniphier-sld8-mio-reset";
247 compatible = "socionext,uniphier-mio-dmac";
H A Duniphier-pro4.dtsi250 compatible = "socionext,uniphier-pro4-mio-clock";
255 compatible = "socionext,uniphier-pro4-mio-reset";
277 compatible = "socionext,uniphier-mio-dmac";
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-sm-k26-revA.dts144 &qspi { /* MIO 0-5 - U143 */
251 xlnx,mio-bank = <0>;
346 "", "", "", /* 75 - 77, MIO end and EMIO start */
H A Dzynqmp-sck-kv-g-revB.dts18 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
114 xlnx,mio-bank = <1>;
H A Dzynqmp-sck-kv-g-revA.dts23 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
134 xlnx,mio-bank = <1>;
H A Dzynqmp-zcu100-revC.dts160 "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
501 xlnx,mio-bank = <0>;
509 xlnx,mio-bank = <0>;
H A Dzynqmp-sck-kv-g-revB.dtso80 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
154 xlnx,mio-bank = <1>;
H A Dzynqmp-sck-kv-g-revA.dtso73 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
153 xlnx,mio-bank = <1>;
H A Dzynqmp-zc1751-xm015-dc1.dts393 xlnx,mio-bank = <0>;
405 xlnx,mio-bank = <1>;
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Darasan,sdhci.txt64 - xlnx,mio-bank: When specified, this will indicate the MIO bank number in
H A Darasan,sdhci.yaml156 xlnx,mio-bank:
161 The MIO bank number in which the command and data lines are configured.
/freebsd/sys/arm/xilinx/
H A Dzy7_gpio.c34 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are

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