1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1 4 * 5 * (C) Copyright 2015 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11/dts-v1/; 12 13#include "zynqmp.dtsi" 14#include "zynqmp-clk-ccf.dtsi" 15#include <dt-bindings/phy/phy.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 18 19/ { 20 model = "ZynqMP zc1751-xm015-dc1 RevA"; 21 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 i2c0 = &i2c1; 26 mmc0 = &sdhci0; 27 mmc1 = &sdhci1; 28 rtc0 = &rtc; 29 serial0 = &uart0; 30 spi0 = &qspi; 31 usb0 = &usb0; 32 }; 33 34 chosen { 35 bootargs = "earlycon"; 36 stdout-path = "serial0:115200n8"; 37 }; 38 39 memory@0 { 40 device_type = "memory"; 41 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 42 }; 43 44 clock_si5338_0: clk27 { /* u55 SI5338-GM */ 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <27000000>; 48 }; 49 50 clock_si5338_2: clk26 { 51 compatible = "fixed-clock"; 52 #clock-cells = <0>; 53 clock-frequency = <26000000>; 54 }; 55 56 clock_si5338_3: clk150 { 57 compatible = "fixed-clock"; 58 #clock-cells = <0>; 59 clock-frequency = <150000000>; 60 }; 61}; 62 63&fpd_dma_chan1 { 64 status = "okay"; 65}; 66 67&fpd_dma_chan2 { 68 status = "okay"; 69}; 70 71&fpd_dma_chan3 { 72 status = "okay"; 73}; 74 75&fpd_dma_chan4 { 76 status = "okay"; 77}; 78 79&fpd_dma_chan5 { 80 status = "okay"; 81}; 82 83&fpd_dma_chan6 { 84 status = "okay"; 85}; 86 87&fpd_dma_chan7 { 88 status = "okay"; 89}; 90 91&fpd_dma_chan8 { 92 status = "okay"; 93}; 94 95&gem3 { 96 status = "okay"; 97 phy-handle = <&phy0>; 98 phy-mode = "rgmii-id"; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_gem3_default>; 101 mdio: mdio { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 phy0: ethernet-phy@0 { 105 reg = <0>; 106 }; 107 }; 108}; 109 110&gpio { 111 status = "okay"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_gpio_default>; 114}; 115 116&gpu { 117 status = "okay"; 118}; 119 120&i2c1 { 121 status = "okay"; 122 clock-frequency = <400000>; 123 pinctrl-names = "default", "gpio"; 124 pinctrl-0 = <&pinctrl_i2c1_default>; 125 pinctrl-1 = <&pinctrl_i2c1_gpio>; 126 scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 127 sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 128 129 eeprom: eeprom@55 { 130 compatible = "atmel,24c64"; /* 24AA64 */ 131 reg = <0x55>; 132 }; 133}; 134 135&pinctrl0 { 136 status = "okay"; 137 pinctrl_i2c1_default: i2c1-default { 138 mux { 139 groups = "i2c1_9_grp"; 140 function = "i2c1"; 141 }; 142 143 conf { 144 groups = "i2c1_9_grp"; 145 bias-pull-up; 146 slew-rate = <SLEW_RATE_SLOW>; 147 power-source = <IO_STANDARD_LVCMOS18>; 148 }; 149 }; 150 151 pinctrl_i2c1_gpio: i2c1-gpio { 152 mux { 153 groups = "gpio0_36_grp", "gpio0_37_grp"; 154 function = "gpio0"; 155 }; 156 157 conf { 158 groups = "gpio0_36_grp", "gpio0_37_grp"; 159 slew-rate = <SLEW_RATE_SLOW>; 160 power-source = <IO_STANDARD_LVCMOS18>; 161 }; 162 }; 163 164 pinctrl_uart0_default: uart0-default { 165 mux { 166 groups = "uart0_8_grp"; 167 function = "uart0"; 168 }; 169 170 conf { 171 groups = "uart0_8_grp"; 172 slew-rate = <SLEW_RATE_SLOW>; 173 power-source = <IO_STANDARD_LVCMOS18>; 174 }; 175 176 conf-rx { 177 pins = "MIO34"; 178 bias-high-impedance; 179 }; 180 181 conf-tx { 182 pins = "MIO35"; 183 bias-disable; 184 }; 185 }; 186 187 pinctrl_usb0_default: usb0-default { 188 mux { 189 groups = "usb0_0_grp"; 190 function = "usb0"; 191 }; 192 193 conf { 194 groups = "usb0_0_grp"; 195 power-source = <IO_STANDARD_LVCMOS18>; 196 }; 197 198 conf-rx { 199 pins = "MIO52", "MIO53", "MIO55"; 200 bias-high-impedance; 201 drive-strength = <12>; 202 slew-rate = <SLEW_RATE_FAST>; 203 }; 204 205 conf-tx { 206 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 207 "MIO60", "MIO61", "MIO62", "MIO63"; 208 bias-disable; 209 drive-strength = <4>; 210 slew-rate = <SLEW_RATE_SLOW>; 211 }; 212 }; 213 214 pinctrl_gem3_default: gem3-default { 215 mux { 216 function = "ethernet3"; 217 groups = "ethernet3_0_grp"; 218 }; 219 220 conf { 221 groups = "ethernet3_0_grp"; 222 slew-rate = <SLEW_RATE_SLOW>; 223 power-source = <IO_STANDARD_LVCMOS18>; 224 }; 225 226 conf-rx { 227 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 228 "MIO75"; 229 bias-high-impedance; 230 low-power-disable; 231 }; 232 233 conf-tx { 234 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 235 "MIO69"; 236 bias-disable; 237 low-power-enable; 238 }; 239 240 mux-mdio { 241 function = "mdio3"; 242 groups = "mdio3_0_grp"; 243 }; 244 245 conf-mdio { 246 groups = "mdio3_0_grp"; 247 slew-rate = <SLEW_RATE_SLOW>; 248 power-source = <IO_STANDARD_LVCMOS18>; 249 bias-disable; 250 }; 251 }; 252 253 pinctrl_sdhci0_default: sdhci0-default { 254 mux { 255 groups = "sdio0_0_grp"; 256 function = "sdio0"; 257 }; 258 259 conf { 260 groups = "sdio0_0_grp"; 261 slew-rate = <SLEW_RATE_SLOW>; 262 power-source = <IO_STANDARD_LVCMOS18>; 263 bias-disable; 264 }; 265 266 mux-cd { 267 groups = "sdio0_cd_0_grp"; 268 function = "sdio0_cd"; 269 }; 270 271 conf-cd { 272 groups = "sdio0_cd_0_grp"; 273 bias-high-impedance; 274 bias-pull-up; 275 slew-rate = <SLEW_RATE_SLOW>; 276 power-source = <IO_STANDARD_LVCMOS18>; 277 }; 278 279 mux-wp { 280 groups = "sdio0_wp_0_grp"; 281 function = "sdio0_wp"; 282 }; 283 284 conf-wp { 285 groups = "sdio0_wp_0_grp"; 286 bias-high-impedance; 287 bias-pull-up; 288 slew-rate = <SLEW_RATE_SLOW>; 289 power-source = <IO_STANDARD_LVCMOS18>; 290 }; 291 }; 292 293 pinctrl_sdhci1_default: sdhci1-default { 294 mux { 295 groups = "sdio1_0_grp"; 296 function = "sdio1"; 297 }; 298 299 conf { 300 groups = "sdio1_0_grp"; 301 slew-rate = <SLEW_RATE_SLOW>; 302 power-source = <IO_STANDARD_LVCMOS18>; 303 bias-disable; 304 }; 305 306 mux-cd { 307 groups = "sdio1_cd_0_grp"; 308 function = "sdio1_cd"; 309 }; 310 311 conf-cd { 312 groups = "sdio1_cd_0_grp"; 313 bias-high-impedance; 314 bias-pull-up; 315 slew-rate = <SLEW_RATE_SLOW>; 316 power-source = <IO_STANDARD_LVCMOS18>; 317 }; 318 319 mux-wp { 320 groups = "sdio1_wp_0_grp"; 321 function = "sdio1_wp"; 322 }; 323 324 conf-wp { 325 groups = "sdio1_wp_0_grp"; 326 bias-high-impedance; 327 bias-pull-up; 328 slew-rate = <SLEW_RATE_SLOW>; 329 power-source = <IO_STANDARD_LVCMOS18>; 330 }; 331 }; 332 333 pinctrl_gpio_default: gpio-default { 334 mux { 335 function = "gpio0"; 336 groups = "gpio0_38_grp"; 337 }; 338 339 conf { 340 groups = "gpio0_38_grp"; 341 bias-disable; 342 slew-rate = <SLEW_RATE_SLOW>; 343 power-source = <IO_STANDARD_LVCMOS18>; 344 }; 345 }; 346}; 347 348&psgtr { 349 status = "okay"; 350 /* dp, usb3, sata */ 351 clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; 352 clock-names = "ref1", "ref2", "ref3"; 353}; 354 355&qspi { 356 status = "okay"; 357 flash@0 { 358 compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ 359 #address-cells = <1>; 360 #size-cells = <1>; 361 reg = <0x0>; 362 spi-tx-bus-width = <4>; 363 spi-rx-bus-width = <4>; 364 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 365 }; 366}; 367 368&rtc { 369 status = "okay"; 370}; 371 372&sata { 373 status = "okay"; 374 /* SATA phy OOB timing settings */ 375 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; 376 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; 377 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 378 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 379 ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; 380 ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; 381 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 382 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 383 phy-names = "sata-phy"; 384 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; 385}; 386 387/* eMMC */ 388&sdhci0 { 389 status = "okay"; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&pinctrl_sdhci0_default>; 392 bus-width = <8>; 393 xlnx,mio-bank = <0>; 394}; 395 396/* SD1 with level shifter */ 397&sdhci1 { 398 status = "okay"; 399 /* 400 * This property should be removed for supporting UHS mode 401 */ 402 no-1-8-v; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&pinctrl_sdhci1_default>; 405 xlnx,mio-bank = <1>; 406}; 407 408&uart0 { 409 status = "okay"; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pinctrl_uart0_default>; 412}; 413 414/* ULPI SMSC USB3320 */ 415&usb0 { 416 status = "okay"; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&pinctrl_usb0_default>; 419 phy-names = "usb3-phy"; 420 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 421}; 422 423&dwc3_0 { 424 status = "okay"; 425 dr_mode = "host"; 426 snps,usb3_lpm_capable; 427 maximum-speed = "super-speed"; 428}; 429 430&zynqmp_dpdma { 431 status = "okay"; 432}; 433 434&zynqmp_dpsub { 435 status = "okay"; 436 phy-names = "dp-phy0", "dp-phy1"; 437 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, 438 <&psgtr 0 PHY_TYPE_DP 1 1>; 439}; 440