1*354d7675SEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*354d7675SEmmanuel Vadot /* 3*354d7675SEmmanuel Vadot * MIO pin configuration defines for Xilinx Zynq 4*354d7675SEmmanuel Vadot * 5*354d7675SEmmanuel Vadot * Copyright (C) 2021 Xilinx, Inc. 6*354d7675SEmmanuel Vadot */ 7*354d7675SEmmanuel Vadot 8*354d7675SEmmanuel Vadot #ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H 9*354d7675SEmmanuel Vadot #define _DT_BINDINGS_PINCTRL_ZYNQ_H 10*354d7675SEmmanuel Vadot 11*354d7675SEmmanuel Vadot /* Configuration options for different power supplies */ 12*354d7675SEmmanuel Vadot #define IO_STANDARD_LVCMOS18 1 13*354d7675SEmmanuel Vadot #define IO_STANDARD_LVCMOS25 2 14*354d7675SEmmanuel Vadot #define IO_STANDARD_LVCMOS33 3 15*354d7675SEmmanuel Vadot #define IO_STANDARD_HSTL 4 16*354d7675SEmmanuel Vadot 17*354d7675SEmmanuel Vadot #endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */ 18