1*2eb4d8dcSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*2eb4d8dcSEmmanuel Vadot /* 3*2eb4d8dcSEmmanuel Vadot * MIO pin configuration defines for Xilinx ZynqMP 4*2eb4d8dcSEmmanuel Vadot * 5*2eb4d8dcSEmmanuel Vadot * Copyright (C) 2020 Xilinx, Inc. 6*2eb4d8dcSEmmanuel Vadot */ 7*2eb4d8dcSEmmanuel Vadot 8*2eb4d8dcSEmmanuel Vadot #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 9*2eb4d8dcSEmmanuel Vadot #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 10*2eb4d8dcSEmmanuel Vadot 11*2eb4d8dcSEmmanuel Vadot /* Bit value for different voltage levels */ 12*2eb4d8dcSEmmanuel Vadot #define IO_STANDARD_LVCMOS33 0 13*2eb4d8dcSEmmanuel Vadot #define IO_STANDARD_LVCMOS18 1 14*2eb4d8dcSEmmanuel Vadot 15*2eb4d8dcSEmmanuel Vadot /* Bit values for Slew Rates */ 16*2eb4d8dcSEmmanuel Vadot #define SLEW_RATE_FAST 0 17*2eb4d8dcSEmmanuel Vadot #define SLEW_RATE_SLOW 1 18*2eb4d8dcSEmmanuel Vadot 19*2eb4d8dcSEmmanuel Vadot #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 20