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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
[all …]
/linux/drivers/cpufreq/
H A Dimx6q-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
11 #include <linux/nvmem-consumer.h>
70 old_freq = clk_get_rate(clks[ARM].clk) / 1000; in imx6q_set_target()
83 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", in imx6q_set_target()
113 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change in imx6q_set_target()
116 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it in imx6q_set_target()
117 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it in imx6q_set_target()
118 * - Disable pll2_pfd2_396m_clk in imx6q_set_target()
129 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); in imx6q_set_target()
[all …]
H A Darmada-8k-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <linux/clk.h>
25 { .compatible = "marvell,ap806-cpu-clock" },
26 { .compatible = "marvell,ap807-cpu-clock" },
32 * Setup the opps list with the divider for the max frequency, that
45 static void __init armada_8k_get_sharing_cpus(struct clk *cur_clk, in armada_8k_get_sharing_cpus()
52 struct clk *clk; in armada_8k_get_sharing_cpus() local
60 clk = clk_get(cpu_dev, NULL); in armada_8k_get_sharing_cpus()
61 if (IS_ERR(clk)) { in armada_8k_get_sharing_cpus()
64 if (clk_is_match(clk, cur_clk)) in armada_8k_get_sharing_cpus()
[all …]
/linux/drivers/clocksource/
H A Dnomadik-mtu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
16 #include <linux/clk.h>
33 /* per-timer registers take 0..3 as argument */
41 #define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
66 static u32 nmdk_cycle; /* write-once */
79 return -readl(mtu_base + MTU_VAL(0)); in nomadik_read_sched_clock()
87 /* Clockevent device: use one-shot mode */
103 /* Timer: configure load and background-load, and fire it up */ in nmdk_clkevt_reset()
145 /* ClockSource: configure load and background-load, and fire it up */ in nmdk_clksrc_reset()
[all …]
H A Dasm9260_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
10 #include <linux/clk.h>
19 #define DRIVER_NAME "asm9260-timer"
23 * 0x0 - plain read write mode
24 * 0x4 - set mode, OR logic.
25 * 0x8 - clr mode, XOR logic.
26 * 0xc - togle mode.
48 * 1 - Timer Counter and Prescale Counter are enabled for counting
49 * 0 - counters are disabled */
[all …]
/linux/include/sound/sof/
H A Ddai-intel.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
58 /* DMIC max. four controllers for eight microphone channels */
61 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
67 uint32_t mclk_rate; /* mclk frequency in Hz */
68 uint32_t fsync_rate; /* fsync frequency in Hz */
69 uint32_t bclk_rate; /* bclk frequency in Hz */
93 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
97 uint32_t rate; member
101 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
105 uint32_t rate; member
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/linux/drivers/spi/
H A Dspi-bcm63xx-hsspi.c4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jonas.gorski@gmail.com>
13 #include <linux/clk.h>
17 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi-mem.h>
24 #include <linux/mtd/spi-nor.h>
124 if (bs->xfer_mode == HSSPI_XFER_MODE_AUTO) \
125 dev_dbg(&bs->pdev->dev, fmt, ##__VA_ARGS__); \
126 else if (bs->xfer_mode == HSSPI_XFER_MODE_PREPEND) \
127 dev_err(&bs->pdev->dev, fmt, ##__VA_ARGS__); \
[all …]
/linux/drivers/input/touchscreen/
H A Dlpc32xx_ts.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * LPC32xx built-in touchscreen driver
12 #include <linux/clk.h>
43 #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7)
44 #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4)
57 #define MOD_NAME "ts-lpc32xx"
60 __raw_readl((dev)->tsc_base + (reg))
62 __raw_writel((val), (dev)->tsc_base + (reg))
68 struct clk *clk; member
83 struct input_dev *input = tsc->dev; in lpc32xx_ts_interrupt()
[all …]
/linux/drivers/interconnect/qcom/
H A Dicc-rpm.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <linux/soc/qcom/smd-rpm.h>
11 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
12 #include <linux/clk.h>
13 #include <linux/interconnect-provider.h>
29 * struct rpm_clk_resource - RPM bus clock resource
41 * struct qcom_icc_provider - Qualcomm specific interconnect provider
47 * @ab_coeff: a percentage-based coefficient for compensating the AB calculations
48 * @ib_coeff: an inverse-percentage-based coefficient for compensating the IB calculations
49 * @bus_clk_rate: bus clock rate in Hz
[all …]
/linux/drivers/media/rc/img-ir/
H A Dimg-ir-hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2014 Imagination Technologies Ltd.
7 * This ties into the input subsystem using the RC-core. Protocol support is
14 #include <linux/clk.h>
18 #include <media/rc-core.h>
19 #include "img-ir.h"
63 /* functions for preprocessing timings, ensuring max is set */
68 if (range->max < range->min) in img_ir_timing_preprocess()
69 range->max = range->min; in img_ir_timing_preprocess()
72 range->min = (range->min*unit)/1000; in img_ir_timing_preprocess()
[all …]
/linux/sound/soc/codecs/
H A Dda7219.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * da7219.c - DA7219 ALSA SoC Codec Driver
11 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
26 #include <sound/soc-dapm.h>
33 #include "da7219-aad.h"
41 static const DECLARE_TLV_DB_SCALE(da7219_mic_gain_tlv, -600, 600, 0);
42 static const DECLARE_TLV_DB_SCALE(da7219_mixin_gain_tlv, -450, 150, 0);
43 static const DECLARE_TLV_DB_SCALE(da7219_adc_dig_gain_tlv, -8325, 75, 0);
44 static const DECLARE_TLV_DB_SCALE(da7219_alc_threshold_tlv, -9450, 150, 0);
[all …]
/linux/drivers/gpu/drm/pl111/
H A Dpl111_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
7 * Copyright (c) 2006-2008 Intel Corporation
12 #include <linux/clk.h>
14 #include <linux/dma-buf.h>
15 #include <linux/media-bus-format.h>
33 irq_stat = readl(priv->regs + CLCD_PL111_MIS); in pl111_irq()
39 drm_crtc_handle_vblank(&priv->pipe.crtc); in pl111_irq()
45 writel(irq_stat, priv->regs + CLCD_PL111_ICR); in pl111_irq()
54 struct drm_device *drm = pipe->crtc.dev; in pl111_mode_valid()
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
17 #include <linux/clk.h>
18 #include "clk.h"
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
57 if (rate == rate_table[i].rate) in rockchip_get_pll_settings()
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_determine_rate()
[all …]
/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on renesas-cpg-mssr.c
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/clk/renesas.h>
31 #include <linux/reset-controller.h>
36 #include <dt-bindings/clock/renesas-cpg-mssr.h>
38 #include "rzg2l-cpg.h"
78 * struct clk_hw_data - clock hardware data
94 * struct sd_mux_hw_data - SD MUX clock hardware data
[all …]
/linux/drivers/memory/tegra/
H A Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
10 #include <linux/clk/tegra.h>
14 #include <linux/interconnect-provider.h>
181 unsigned long rate; member
202 struct clk *clk; member
217 * a min/max clock rate, these rates are contained in this array.
221 /* protect shared rate-change code path */
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
[all …]
H A Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk/tegra.h>
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: regulator-pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
[all …]
/linux/drivers/clk/
H A Dclk-si544.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
39 /* Max freq depends on speed grade */
45 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
68 * struct clk_si544_muldiv - Multiplier/divider settings
73 * If ls_div_bits is non-zero, hs_div must be even
74 * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
87 return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, in si544_enable_output()
111 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); in si544_is_prepared()
125 err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); in si544_get_muldiv()
[all …]
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk/clk-conf.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
28 #include "clk.h"
78 unsigned long rate; member
107 #include <trace/events/clk.h>
[all …]
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
/linux/drivers/iio/adc/
H A Daspeed_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
79 * When the sampling rate is too high, the ADC may not have enough charging
81 * sampling rate for most use cases.
92 unsigned int min_sampling_rate; // Hz
93 unsigned int max_sampling_rate; // Hz
184 dev_warn(data->dev, "Couldn't find syscon node\n"); in aspeed_adc_set_trim_data()
185 return -EOPNOTSUPP; in aspeed_adc_set_trim_data()
190 dev_warn(data->dev, "Failed to get syscon regmap\n"); in aspeed_adc_set_trim_data()
[all …]
/linux/drivers/watchdog/
H A Dimgpdc_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * -----
25 * The following table shows how the user-configured timeout relates
26 * to the actual hardware timeout (watchdog clock @ 40000 Hz):
29 * -----------------------------------
37 * clock rate and achieve a finer timeout granularity.
40 #include <linux/clk.h>
84 struct clk *wdt_clk;
85 struct clk *sys_clk;
93 writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1); in pdc_wdt_keepalive()
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/linux/arch/mips/alchemy/common/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0
5 * Exposes all configurable internal clock sources to the clk framework.
8 * - Root source, usually 12MHz supplied by an external crystal
9 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
12 * - 6 clock dividers with:
18 * - up to 6 "internal" (fixed) consumers which:
24 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
25 * depends on board design and should be set by bootloader, read-only.
26 * - peripheral clock: half the rate of sysbus clock, source for a lot
27 * of peripheral blocks, read-only.
[all …]
/linux/drivers/devfreq/
H A Dtegra30-devfreq.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
76 * struct tegra_devfreq_device_config - configuration specific to an ACTMON
152 * struct tegra_devfreq_device - state specific to an ACTMON device
183 struct clk *clock;
186 struct clk *emc_clock;
220 return readl_relaxed(tegra->regs + offset); in actmon_readl()
225 writel_relaxed(val, tegra->regs + offset); in actmon_writel()
230 return readl_relaxed(dev->regs + offset); in device_readl()
236 writel_relaxed(val, dev->regs + offset); in device_writel()
[all …]

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