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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
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/linux/drivers/cpufreq/
H A Dsh-cpufreq.c4 * Copyright (C) 2002 - 2012 Paul Mundt
7 * Clock framework bits from arch/avr32/mach-at32ap/cpufreq.c
9 * Copyright (C) 2004-2007 Atmel Corporation
26 #include <linux/clk.h>
30 static DEFINE_PER_CPU(struct clk, sh_cpuclk);
45 struct cpufreq_policy *policy = target->policy; in __sh_cpufreq_target()
46 int cpu = policy->cpu; in __sh_cpufreq_target()
47 struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu); in __sh_cpufreq_target()
53 return -ENODEV; in __sh_cpufreq_target()
57 /* Convert target_freq from kHz to Hz */ in __sh_cpufreq_target()
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H A Darmada-8k-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <linux/clk.h>
25 { .compatible = "marvell,ap806-cpu-clock" },
26 { .compatible = "marvell,ap807-cpu-clock" },
32 * Setup the opps list with the divider for the max frequency, that
45 static void __init armada_8k_get_sharing_cpus(struct clk *cur_clk, in armada_8k_get_sharing_cpus()
52 struct clk *clk; in armada_8k_get_sharing_cpus() local
60 clk = clk_get(cpu_dev, NULL); in armada_8k_get_sharing_cpus()
61 if (IS_ERR(clk)) { in armada_8k_get_sharing_cpus()
64 if (clk_is_match(clk, cur_clk)) in armada_8k_get_sharing_cpus()
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/linux/drivers/clocksource/
H A Dnomadik-mtu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
16 #include <linux/clk.h>
33 /* per-timer registers take 0..3 as argument */
41 #define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
66 static u32 nmdk_cycle; /* write-once */
79 return -readl(mtu_base + MTU_VAL(0)); in nomadik_read_sched_clock()
87 /* Clockevent device: use one-shot mode */
103 /* Timer: configure load and background-load, and fire it up */ in nmdk_clkevt_reset()
145 /* ClockSource: configure load and background-load, and fire it up */ in nmdk_clksrc_reset()
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H A Dasm9260_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
10 #include <linux/clk.h>
19 #define DRIVER_NAME "asm9260-timer"
23 * 0x0 - plain read write mode
24 * 0x4 - set mode, OR logic.
25 * 0x8 - clr mode, XOR logic.
26 * 0xc - togle mode.
48 * 1 - Timer Counter and Prescale Counter are enabled for counting
49 * 0 - counters are disabled */
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H A Dtimer-vf-pit.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
8 #include <linux/clk.h>
56 static int __init pit_clocksource_init(unsigned long rate) in pit_clocksource_init() argument
58 /* set the max load value and start the clock source counter */ in pit_clocksource_init()
63 sched_clock_register(pit_read_sched_clock, 32, rate); in pit_clocksource_init()
64 return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate, in pit_clocksource_init()
79 __raw_writel(delta - 1, clkevt_base + PITLDVAL); in pit_set_next_event()
112 evt->event_handler(evt); in pit_timer_interrupt()
126 static int __init pit_clockevent_init(unsigned long rate, int irq) in pit_clockevent_init() argument
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/linux/Documentation/devicetree/bindings/iio/imu/
H A Dadi,adis16480.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandr
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/linux/include/sound/sof/
H A Ddai-intel.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
58 /* DMIC max. four controllers for eight microphone channels */
61 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
67 uint32_t mclk_rate; /* mclk frequency in Hz */
68 uint32_t fsync_rate; /* fsync frequency in Hz */
69 uint32_t bclk_rate; /* bclk frequency in Hz */
93 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
97 uint32_t rate; member
101 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
105 uint32_t rate; member
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/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8195.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/nvmem-consumer.h>
18 #include "phy-mtk-io.h"
19 #include "phy-mtk-hdmi.h"
20 #include "phy-mtk-hdm
210 mtk_hdmi_pll_calc(struct mtk_hdmi_phy * hdmi_phy,struct clk_hw * hw,unsigned long rate,unsigned long parent_rate) mtk_hdmi_pll_calc() argument
408 mtk_hdmi_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate) mtk_hdmi_pll_set_rate() argument
419 mtk_hdmi_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate) mtk_hdmi_pll_round_rate() argument
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/linux/drivers/input/touchscreen/
H A Dlpc32xx_ts.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * LPC32xx built-in touchscreen driver
12 #include <linux/clk.h>
43 #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7)
44 #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4)
57 #define MOD_NAME "ts-lpc32xx"
60 __raw_readl((dev)->tsc_base + (reg))
62 __raw_writel((val), (dev)->tsc_base + (reg))
68 struct clk *clk; member
83 struct input_dev *input = tsc->dev; in lpc32xx_ts_interrupt()
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/linux/drivers/interconnect/qcom/
H A Dicc-rpm.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <linux/soc/qcom/smd-rpm.h>
11 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
12 #include <linux/clk.h>
13 #include <linux/interconnect-provider.h>
29 * struct rpm_clk_resource - RPM bus clock resource
41 * struct qcom_icc_provider - Qualcomm specific interconnect provider
47 * @ab_coeff: a percentage-based coefficient for compensating the AB calculations
48 * @ib_coeff: an inverse-percentage-based coefficient for compensating the IB calculations
49 * @bus_clk_rate: bus clock rate in Hz
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/linux/drivers/media/rc/img-ir/
H A Dimg-ir-hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2014 Imagination Technologies Ltd.
7 * This ties into the input subsystem using the RC-core. Protocol support is
14 #include <linux/clk.h>
18 #include <media/rc-core.h>
19 #include "img-ir.h"
63 /* functions for preprocessing timings, ensuring max is set */
68 if (range->max < range->min) in img_ir_timing_preprocess()
69 range->max = range->min; in img_ir_timing_preprocess()
72 range->min = (range->min*unit)/1000; in img_ir_timing_preprocess()
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/linux/drivers/gpu/drm/pl111/
H A Dpl111_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
7 * Copyright (c) 2006-2008 Intel Corporation
12 #include <linux/clk.h>
14 #include <linux/dma-buf.h>
15 #include <linux/media-bus-format.h>
33 irq_stat = readl(priv->regs + CLCD_PL111_MIS); in pl111_irq()
39 drm_crtc_handle_vblank(&priv->pipe.crtc); in pl111_irq()
45 writel(irq_stat, priv->regs + CLCD_PL111_ICR); in pl111_irq()
54 struct drm_device *drm = pipe->crtc.dev; in pl111_mode_valid()
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
17 #include <linux/clk.h>
18 #include "clk.h"
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
57 if (rate == rate_table[i].rate) in rockchip_get_pll_settings()
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
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/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on renesas-cpg-mssr.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "rzg2l-cpg.h"
69 * struct clk_hw_data - clock hardware data
85 * struct sd_mux_hw_data - SD MUX clock hardware data
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: regulator-pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
[all …]
/linux/drivers/clk/
H A Dclk-si544.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
39 /* Max freq depends on speed grade */
45 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
68 * struct clk_si544_muldiv - Multiplier/divider settings
73 * If ls_div_bits is non-zero, hs_div must be even
74 * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
87 return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, in si544_enable_output()
111 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); in si544_is_prepared()
125 err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); in si544_get_muldiv()
[all …]
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
72 unsigned long rate; member
100 #include <trace/events/clk.h>
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
9 #include <linux/clk.h>
20 * The higher 16-bit of this register is used for write protection
87 struct clk *emmcclk;
99 unsigned long rate; in rockchip_emmc_phy_power() local
106 regmap_write(rk_phy->reg_base, in rockchip_emmc_phy_power()
107 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
111 regmap_write(rk_phy->reg_base, in rockchip_emmc_phy_power()
112 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
[all …]
/linux/drivers/mmc/host/
H A Drenesas_sdhi_core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
21 #include <linux/clk.h>
27 #include <linux/mmc/slot-gpio.h>
30 #include <linux/pinctrl/pinctrl-state.h>
95 struct mmc_host *mmc = host->mmc; in renesas_sdhi_clk_enable()
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/linux/drivers/memory/tegra/
H A Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk/tegra.h>
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
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/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
32 * FIFO max size chunk only
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
[all …]
/linux/drivers/iio/adc/
H A Daspeed_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
79 * When the sampling rate is too high, the ADC may not have enough charging
81 * sampling rate for most use cases.
92 unsigned int min_sampling_rate; // Hz
93 unsigned int max_sampling_rate; // Hz
184 dev_warn(data->dev, "Couldn't find syscon node\n"); in aspeed_adc_set_trim_data()
185 return -EOPNOTSUPP; in aspeed_adc_set_trim_data()
190 dev_warn(data->dev, "Failed to get syscon regmap\n"); in aspeed_adc_set_trim_data()
[all …]
/linux/sound/soc/ti/
H A Dj721e-evm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
7 #include <linux/clk.h>
17 #include "davinci-mcasp.h"
60 struct clk *target;
61 struct clk *parent[2];
71 unsigned int rate; member
100 {"CPB Stereo HP 1", NULL, "codec-1 AOUT1L"},
101 {"CPB Stereo HP 1", NULL, "codec-1 AOUT1R"},
102 {"CPB Stereo HP 2", NULL, "codec-1 AOUT2L"},
[all …]
/linux/drivers/watchdog/
H A Dimgpdc_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * -----
25 * The following table shows how the user-configured timeout relates
26 * to the actual hardware timeout (watchdog clock @ 40000 Hz):
29 * -----------------------------------
37 * clock rate and achieve a finer timeout granularity.
40 #include <linux/clk.h>
84 struct clk *wdt_clk;
85 struct clk *sys_clk;
93 writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1); in pdc_wdt_keepalive()
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