12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
230dd9e0cSJames Hogan /*
330dd9e0cSJames Hogan * ImgTec IR Hardware Decoder found in PowerDown Controller.
430dd9e0cSJames Hogan *
530dd9e0cSJames Hogan * Copyright 2010-2014 Imagination Technologies Ltd.
630dd9e0cSJames Hogan *
730dd9e0cSJames Hogan * This ties into the input subsystem using the RC-core. Protocol support is
830dd9e0cSJames Hogan * provided in separate modules which provide the parameters and scancode
930dd9e0cSJames Hogan * translation functions to set up the hardware decoder and interpret the
1030dd9e0cSJames Hogan * resulting input.
1130dd9e0cSJames Hogan */
1230dd9e0cSJames Hogan
1330dd9e0cSJames Hogan #include <linux/bitops.h>
1430dd9e0cSJames Hogan #include <linux/clk.h>
1530dd9e0cSJames Hogan #include <linux/interrupt.h>
1630dd9e0cSJames Hogan #include <linux/spinlock.h>
1730dd9e0cSJames Hogan #include <linux/timer.h>
1830dd9e0cSJames Hogan #include <media/rc-core.h>
1930dd9e0cSJames Hogan #include "img-ir.h"
2030dd9e0cSJames Hogan
2130dd9e0cSJames Hogan /* Decoders lock (only modified to preprocess them) */
2230dd9e0cSJames Hogan static DEFINE_SPINLOCK(img_ir_decoders_lock);
2330dd9e0cSJames Hogan
2430dd9e0cSJames Hogan static bool img_ir_decoders_preprocessed;
2530dd9e0cSJames Hogan static struct img_ir_decoder *img_ir_decoders[] = {
26635abb70SJames Hogan #ifdef CONFIG_IR_IMG_NEC
27635abb70SJames Hogan &img_ir_nec,
28635abb70SJames Hogan #endif
2969336533SJames Hogan #ifdef CONFIG_IR_IMG_JVC
3069336533SJames Hogan &img_ir_jvc,
3169336533SJames Hogan #endif
32e72b21abSJames Hogan #ifdef CONFIG_IR_IMG_SONY
33e72b21abSJames Hogan &img_ir_sony,
34e72b21abSJames Hogan #endif
353c11305eSJames Hogan #ifdef CONFIG_IR_IMG_SHARP
363c11305eSJames Hogan &img_ir_sharp,
373c11305eSJames Hogan #endif
3846b35083SJames Hogan #ifdef CONFIG_IR_IMG_SANYO
3946b35083SJames Hogan &img_ir_sanyo,
4046b35083SJames Hogan #endif
41aa7383dbSSifan Naeem #ifdef CONFIG_IR_IMG_RC5
42aa7383dbSSifan Naeem &img_ir_rc5,
43aa7383dbSSifan Naeem #endif
44cb9564e1SSifan Naeem #ifdef CONFIG_IR_IMG_RC6
45cb9564e1SSifan Naeem &img_ir_rc6,
46cb9564e1SSifan Naeem #endif
4730dd9e0cSJames Hogan NULL
4830dd9e0cSJames Hogan };
4930dd9e0cSJames Hogan
5030dd9e0cSJames Hogan #define IMG_IR_F_FILTER BIT(RC_FILTER_NORMAL) /* enable filtering */
5130dd9e0cSJames Hogan #define IMG_IR_F_WAKE BIT(RC_FILTER_WAKEUP) /* enable waking */
5230dd9e0cSJames Hogan
5330dd9e0cSJames Hogan /* code type quirks */
5430dd9e0cSJames Hogan
5530dd9e0cSJames Hogan #define IMG_IR_QUIRK_CODE_BROKEN 0x1 /* Decode is broken */
5630dd9e0cSJames Hogan #define IMG_IR_QUIRK_CODE_LEN_INCR 0x2 /* Bit length needs increment */
5702744c8cSSifan Naeem /*
5802744c8cSSifan Naeem * The decoder generates rapid interrupts without actually having
5902744c8cSSifan Naeem * received any new data after an incomplete IR code is decoded.
6002744c8cSSifan Naeem */
6102744c8cSSifan Naeem #define IMG_IR_QUIRK_CODE_IRQ 0x4
6230dd9e0cSJames Hogan
6330dd9e0cSJames Hogan /* functions for preprocessing timings, ensuring max is set */
6430dd9e0cSJames Hogan
img_ir_timing_preprocess(struct img_ir_timing_range * range,unsigned int unit)6530dd9e0cSJames Hogan static void img_ir_timing_preprocess(struct img_ir_timing_range *range,
6630dd9e0cSJames Hogan unsigned int unit)
6730dd9e0cSJames Hogan {
6830dd9e0cSJames Hogan if (range->max < range->min)
6930dd9e0cSJames Hogan range->max = range->min;
7030dd9e0cSJames Hogan if (unit) {
7130dd9e0cSJames Hogan /* multiply by unit and convert to microseconds */
7230dd9e0cSJames Hogan range->min = (range->min*unit)/1000;
7330dd9e0cSJames Hogan range->max = (range->max*unit + 999)/1000; /* round up */
7430dd9e0cSJames Hogan }
7530dd9e0cSJames Hogan }
7630dd9e0cSJames Hogan
img_ir_symbol_timing_preprocess(struct img_ir_symbol_timing * timing,unsigned int unit)7730dd9e0cSJames Hogan static void img_ir_symbol_timing_preprocess(struct img_ir_symbol_timing *timing,
7830dd9e0cSJames Hogan unsigned int unit)
7930dd9e0cSJames Hogan {
8030dd9e0cSJames Hogan img_ir_timing_preprocess(&timing->pulse, unit);
8130dd9e0cSJames Hogan img_ir_timing_preprocess(&timing->space, unit);
8230dd9e0cSJames Hogan }
8330dd9e0cSJames Hogan
img_ir_timings_preprocess(struct img_ir_timings * timings,unsigned int unit)8430dd9e0cSJames Hogan static void img_ir_timings_preprocess(struct img_ir_timings *timings,
8530dd9e0cSJames Hogan unsigned int unit)
8630dd9e0cSJames Hogan {
8730dd9e0cSJames Hogan img_ir_symbol_timing_preprocess(&timings->ldr, unit);
8830dd9e0cSJames Hogan img_ir_symbol_timing_preprocess(&timings->s00, unit);
8930dd9e0cSJames Hogan img_ir_symbol_timing_preprocess(&timings->s01, unit);
9030dd9e0cSJames Hogan img_ir_symbol_timing_preprocess(&timings->s10, unit);
9130dd9e0cSJames Hogan img_ir_symbol_timing_preprocess(&timings->s11, unit);
9230dd9e0cSJames Hogan /* default s10 and s11 to s00 and s01 if no leader */
9330dd9e0cSJames Hogan if (unit)
9430dd9e0cSJames Hogan /* multiply by unit and convert to microseconds (round up) */
9530dd9e0cSJames Hogan timings->ft.ft_min = (timings->ft.ft_min*unit + 999)/1000;
9630dd9e0cSJames Hogan }
9730dd9e0cSJames Hogan
9830dd9e0cSJames Hogan /* functions for filling empty fields with defaults */
9930dd9e0cSJames Hogan
img_ir_timing_defaults(struct img_ir_timing_range * range,struct img_ir_timing_range * defaults)10030dd9e0cSJames Hogan static void img_ir_timing_defaults(struct img_ir_timing_range *range,
10130dd9e0cSJames Hogan struct img_ir_timing_range *defaults)
10230dd9e0cSJames Hogan {
10330dd9e0cSJames Hogan if (!range->min)
10430dd9e0cSJames Hogan range->min = defaults->min;
10530dd9e0cSJames Hogan if (!range->max)
10630dd9e0cSJames Hogan range->max = defaults->max;
10730dd9e0cSJames Hogan }
10830dd9e0cSJames Hogan
img_ir_symbol_timing_defaults(struct img_ir_symbol_timing * timing,struct img_ir_symbol_timing * defaults)10930dd9e0cSJames Hogan static void img_ir_symbol_timing_defaults(struct img_ir_symbol_timing *timing,
11030dd9e0cSJames Hogan struct img_ir_symbol_timing *defaults)
11130dd9e0cSJames Hogan {
11230dd9e0cSJames Hogan img_ir_timing_defaults(&timing->pulse, &defaults->pulse);
11330dd9e0cSJames Hogan img_ir_timing_defaults(&timing->space, &defaults->space);
11430dd9e0cSJames Hogan }
11530dd9e0cSJames Hogan
img_ir_timings_defaults(struct img_ir_timings * timings,struct img_ir_timings * defaults)11630dd9e0cSJames Hogan static void img_ir_timings_defaults(struct img_ir_timings *timings,
11730dd9e0cSJames Hogan struct img_ir_timings *defaults)
11830dd9e0cSJames Hogan {
11930dd9e0cSJames Hogan img_ir_symbol_timing_defaults(&timings->ldr, &defaults->ldr);
12030dd9e0cSJames Hogan img_ir_symbol_timing_defaults(&timings->s00, &defaults->s00);
12130dd9e0cSJames Hogan img_ir_symbol_timing_defaults(&timings->s01, &defaults->s01);
12230dd9e0cSJames Hogan img_ir_symbol_timing_defaults(&timings->s10, &defaults->s10);
12330dd9e0cSJames Hogan img_ir_symbol_timing_defaults(&timings->s11, &defaults->s11);
12430dd9e0cSJames Hogan if (!timings->ft.ft_min)
12530dd9e0cSJames Hogan timings->ft.ft_min = defaults->ft.ft_min;
12630dd9e0cSJames Hogan }
12730dd9e0cSJames Hogan
12830dd9e0cSJames Hogan /* functions for converting timings to register values */
12930dd9e0cSJames Hogan
13030dd9e0cSJames Hogan /**
13130dd9e0cSJames Hogan * img_ir_control() - Convert control struct to control register value.
13230dd9e0cSJames Hogan * @control: Control data
13330dd9e0cSJames Hogan *
13430dd9e0cSJames Hogan * Returns: The control register value equivalent of @control.
13530dd9e0cSJames Hogan */
img_ir_control(const struct img_ir_control * control)13630dd9e0cSJames Hogan static u32 img_ir_control(const struct img_ir_control *control)
13730dd9e0cSJames Hogan {
13830dd9e0cSJames Hogan u32 ctrl = control->code_type << IMG_IR_CODETYPE_SHIFT;
13930dd9e0cSJames Hogan if (control->decoden)
14030dd9e0cSJames Hogan ctrl |= IMG_IR_DECODEN;
14130dd9e0cSJames Hogan if (control->hdrtog)
14230dd9e0cSJames Hogan ctrl |= IMG_IR_HDRTOG;
14330dd9e0cSJames Hogan if (control->ldrdec)
14430dd9e0cSJames Hogan ctrl |= IMG_IR_LDRDEC;
14530dd9e0cSJames Hogan if (control->decodinpol)
14630dd9e0cSJames Hogan ctrl |= IMG_IR_DECODINPOL;
14730dd9e0cSJames Hogan if (control->bitorien)
14830dd9e0cSJames Hogan ctrl |= IMG_IR_BITORIEN;
14930dd9e0cSJames Hogan if (control->d1validsel)
15030dd9e0cSJames Hogan ctrl |= IMG_IR_D1VALIDSEL;
15130dd9e0cSJames Hogan if (control->bitinv)
15230dd9e0cSJames Hogan ctrl |= IMG_IR_BITINV;
15330dd9e0cSJames Hogan if (control->decodend2)
15430dd9e0cSJames Hogan ctrl |= IMG_IR_DECODEND2;
15530dd9e0cSJames Hogan if (control->bitoriend2)
15630dd9e0cSJames Hogan ctrl |= IMG_IR_BITORIEND2;
15730dd9e0cSJames Hogan if (control->bitinvd2)
15830dd9e0cSJames Hogan ctrl |= IMG_IR_BITINVD2;
15930dd9e0cSJames Hogan return ctrl;
16030dd9e0cSJames Hogan }
16130dd9e0cSJames Hogan
16230dd9e0cSJames Hogan /**
16330dd9e0cSJames Hogan * img_ir_timing_range_convert() - Convert microsecond range.
16430dd9e0cSJames Hogan * @out: Output timing range in clock cycles with a shift.
16530dd9e0cSJames Hogan * @in: Input timing range in microseconds.
16630dd9e0cSJames Hogan * @tolerance: Tolerance as a fraction of 128 (roughly percent).
16730dd9e0cSJames Hogan * @clock_hz: IR clock rate in Hz.
16830dd9e0cSJames Hogan * @shift: Shift of output units.
16930dd9e0cSJames Hogan *
17030dd9e0cSJames Hogan * Converts min and max from microseconds to IR clock cycles, applies a
17130dd9e0cSJames Hogan * tolerance, and shifts for the register, rounding in the right direction.
17230dd9e0cSJames Hogan * Note that in and out can safely be the same object.
17330dd9e0cSJames Hogan */
img_ir_timing_range_convert(struct img_ir_timing_range * out,const struct img_ir_timing_range * in,unsigned int tolerance,unsigned long clock_hz,unsigned int shift)17430dd9e0cSJames Hogan static void img_ir_timing_range_convert(struct img_ir_timing_range *out,
17530dd9e0cSJames Hogan const struct img_ir_timing_range *in,
17630dd9e0cSJames Hogan unsigned int tolerance,
17730dd9e0cSJames Hogan unsigned long clock_hz,
17830dd9e0cSJames Hogan unsigned int shift)
17930dd9e0cSJames Hogan {
18030dd9e0cSJames Hogan unsigned int min = in->min;
18130dd9e0cSJames Hogan unsigned int max = in->max;
18230dd9e0cSJames Hogan /* add a tolerance */
18330dd9e0cSJames Hogan min = min - (min*tolerance >> 7);
18430dd9e0cSJames Hogan max = max + (max*tolerance >> 7);
18530dd9e0cSJames Hogan /* convert from microseconds into clock cycles */
18630dd9e0cSJames Hogan min = min*clock_hz / 1000000;
18730dd9e0cSJames Hogan max = (max*clock_hz + 999999) / 1000000; /* round up */
18830dd9e0cSJames Hogan /* apply shift and copy to output */
18930dd9e0cSJames Hogan out->min = min >> shift;
19030dd9e0cSJames Hogan out->max = (max + ((1 << shift) - 1)) >> shift; /* round up */
19130dd9e0cSJames Hogan }
19230dd9e0cSJames Hogan
19330dd9e0cSJames Hogan /**
19430dd9e0cSJames Hogan * img_ir_symbol_timing() - Convert symbol timing struct to register value.
19530dd9e0cSJames Hogan * @timing: Symbol timing data
19630dd9e0cSJames Hogan * @tolerance: Timing tolerance where 0-128 represents 0-100%
19730dd9e0cSJames Hogan * @clock_hz: Frequency of source clock in Hz
19830dd9e0cSJames Hogan * @pd_shift: Shift to apply to symbol period
19930dd9e0cSJames Hogan * @w_shift: Shift to apply to symbol width
20030dd9e0cSJames Hogan *
20130dd9e0cSJames Hogan * Returns: Symbol timing register value based on arguments.
20230dd9e0cSJames Hogan */
img_ir_symbol_timing(const struct img_ir_symbol_timing * timing,unsigned int tolerance,unsigned long clock_hz,unsigned int pd_shift,unsigned int w_shift)20330dd9e0cSJames Hogan static u32 img_ir_symbol_timing(const struct img_ir_symbol_timing *timing,
20430dd9e0cSJames Hogan unsigned int tolerance,
20530dd9e0cSJames Hogan unsigned long clock_hz,
20630dd9e0cSJames Hogan unsigned int pd_shift,
20730dd9e0cSJames Hogan unsigned int w_shift)
20830dd9e0cSJames Hogan {
20930dd9e0cSJames Hogan struct img_ir_timing_range hw_pulse, hw_period;
21030dd9e0cSJames Hogan /* we calculate period in hw_period, then convert in place */
21130dd9e0cSJames Hogan hw_period.min = timing->pulse.min + timing->space.min;
21230dd9e0cSJames Hogan hw_period.max = timing->pulse.max + timing->space.max;
21330dd9e0cSJames Hogan img_ir_timing_range_convert(&hw_period, &hw_period,
21430dd9e0cSJames Hogan tolerance, clock_hz, pd_shift);
21530dd9e0cSJames Hogan img_ir_timing_range_convert(&hw_pulse, &timing->pulse,
21630dd9e0cSJames Hogan tolerance, clock_hz, w_shift);
21730dd9e0cSJames Hogan /* construct register value */
21830dd9e0cSJames Hogan return (hw_period.max << IMG_IR_PD_MAX_SHIFT) |
21930dd9e0cSJames Hogan (hw_period.min << IMG_IR_PD_MIN_SHIFT) |
22030dd9e0cSJames Hogan (hw_pulse.max << IMG_IR_W_MAX_SHIFT) |
22130dd9e0cSJames Hogan (hw_pulse.min << IMG_IR_W_MIN_SHIFT);
22230dd9e0cSJames Hogan }
22330dd9e0cSJames Hogan
22430dd9e0cSJames Hogan /**
22530dd9e0cSJames Hogan * img_ir_free_timing() - Convert free time timing struct to register value.
22630dd9e0cSJames Hogan * @timing: Free symbol timing data
22730dd9e0cSJames Hogan * @clock_hz: Source clock frequency in Hz
22830dd9e0cSJames Hogan *
22930dd9e0cSJames Hogan * Returns: Free symbol timing register value.
23030dd9e0cSJames Hogan */
img_ir_free_timing(const struct img_ir_free_timing * timing,unsigned long clock_hz)23130dd9e0cSJames Hogan static u32 img_ir_free_timing(const struct img_ir_free_timing *timing,
23230dd9e0cSJames Hogan unsigned long clock_hz)
23330dd9e0cSJames Hogan {
23430dd9e0cSJames Hogan unsigned int minlen, maxlen, ft_min;
23530dd9e0cSJames Hogan /* minlen is only 5 bits, and round minlen to multiple of 2 */
23630dd9e0cSJames Hogan if (timing->minlen < 30)
23730dd9e0cSJames Hogan minlen = timing->minlen & -2;
23830dd9e0cSJames Hogan else
23930dd9e0cSJames Hogan minlen = 30;
24030dd9e0cSJames Hogan /* maxlen has maximum value of 48, and round maxlen to multiple of 2 */
24130dd9e0cSJames Hogan if (timing->maxlen < 48)
24230dd9e0cSJames Hogan maxlen = (timing->maxlen + 1) & -2;
24330dd9e0cSJames Hogan else
24430dd9e0cSJames Hogan maxlen = 48;
24530dd9e0cSJames Hogan /* convert and shift ft_min, rounding upwards */
24630dd9e0cSJames Hogan ft_min = (timing->ft_min*clock_hz + 999999) / 1000000;
24730dd9e0cSJames Hogan ft_min = (ft_min + 7) >> 3;
24830dd9e0cSJames Hogan /* construct register value */
249b9e28d1fSJames Hogan return (maxlen << IMG_IR_MAXLEN_SHIFT) |
250b9e28d1fSJames Hogan (minlen << IMG_IR_MINLEN_SHIFT) |
25130dd9e0cSJames Hogan (ft_min << IMG_IR_FT_MIN_SHIFT);
25230dd9e0cSJames Hogan }
25330dd9e0cSJames Hogan
25430dd9e0cSJames Hogan /**
25530dd9e0cSJames Hogan * img_ir_free_timing_dynamic() - Update free time register value.
25630dd9e0cSJames Hogan * @st_ft: Static free time register value from img_ir_free_timing.
25730dd9e0cSJames Hogan * @filter: Current filter which may additionally restrict min/max len.
25830dd9e0cSJames Hogan *
25930dd9e0cSJames Hogan * Returns: Updated free time register value based on the current filter.
26030dd9e0cSJames Hogan */
img_ir_free_timing_dynamic(u32 st_ft,struct img_ir_filter * filter)26130dd9e0cSJames Hogan static u32 img_ir_free_timing_dynamic(u32 st_ft, struct img_ir_filter *filter)
26230dd9e0cSJames Hogan {
26330dd9e0cSJames Hogan unsigned int minlen, maxlen, newminlen, newmaxlen;
26430dd9e0cSJames Hogan
26530dd9e0cSJames Hogan /* round minlen, maxlen to multiple of 2 */
26630dd9e0cSJames Hogan newminlen = filter->minlen & -2;
26730dd9e0cSJames Hogan newmaxlen = (filter->maxlen + 1) & -2;
26830dd9e0cSJames Hogan /* extract min/max len from register */
26930dd9e0cSJames Hogan minlen = (st_ft & IMG_IR_MINLEN) >> IMG_IR_MINLEN_SHIFT;
27030dd9e0cSJames Hogan maxlen = (st_ft & IMG_IR_MAXLEN) >> IMG_IR_MAXLEN_SHIFT;
27130dd9e0cSJames Hogan /* if the new values are more restrictive, update the register value */
27230dd9e0cSJames Hogan if (newminlen > minlen) {
27330dd9e0cSJames Hogan st_ft &= ~IMG_IR_MINLEN;
27430dd9e0cSJames Hogan st_ft |= newminlen << IMG_IR_MINLEN_SHIFT;
27530dd9e0cSJames Hogan }
27630dd9e0cSJames Hogan if (newmaxlen < maxlen) {
27730dd9e0cSJames Hogan st_ft &= ~IMG_IR_MAXLEN;
27830dd9e0cSJames Hogan st_ft |= newmaxlen << IMG_IR_MAXLEN_SHIFT;
27930dd9e0cSJames Hogan }
28030dd9e0cSJames Hogan return st_ft;
28130dd9e0cSJames Hogan }
28230dd9e0cSJames Hogan
28330dd9e0cSJames Hogan /**
28430dd9e0cSJames Hogan * img_ir_timings_convert() - Convert timings to register values
28530dd9e0cSJames Hogan * @regs: Output timing register values
28630dd9e0cSJames Hogan * @timings: Input timing data
28730dd9e0cSJames Hogan * @tolerance: Timing tolerance where 0-128 represents 0-100%
28830dd9e0cSJames Hogan * @clock_hz: Source clock frequency in Hz
28930dd9e0cSJames Hogan */
img_ir_timings_convert(struct img_ir_timing_regvals * regs,const struct img_ir_timings * timings,unsigned int tolerance,unsigned int clock_hz)29030dd9e0cSJames Hogan static void img_ir_timings_convert(struct img_ir_timing_regvals *regs,
29130dd9e0cSJames Hogan const struct img_ir_timings *timings,
29230dd9e0cSJames Hogan unsigned int tolerance,
29330dd9e0cSJames Hogan unsigned int clock_hz)
29430dd9e0cSJames Hogan {
29530dd9e0cSJames Hogan /* leader symbol timings are divided by 16 */
29630dd9e0cSJames Hogan regs->ldr = img_ir_symbol_timing(&timings->ldr, tolerance, clock_hz,
29730dd9e0cSJames Hogan 4, 4);
29830dd9e0cSJames Hogan /* other symbol timings, pd fields only are divided by 2 */
29930dd9e0cSJames Hogan regs->s00 = img_ir_symbol_timing(&timings->s00, tolerance, clock_hz,
30030dd9e0cSJames Hogan 1, 0);
30130dd9e0cSJames Hogan regs->s01 = img_ir_symbol_timing(&timings->s01, tolerance, clock_hz,
30230dd9e0cSJames Hogan 1, 0);
30330dd9e0cSJames Hogan regs->s10 = img_ir_symbol_timing(&timings->s10, tolerance, clock_hz,
30430dd9e0cSJames Hogan 1, 0);
30530dd9e0cSJames Hogan regs->s11 = img_ir_symbol_timing(&timings->s11, tolerance, clock_hz,
30630dd9e0cSJames Hogan 1, 0);
30730dd9e0cSJames Hogan regs->ft = img_ir_free_timing(&timings->ft, clock_hz);
30830dd9e0cSJames Hogan }
30930dd9e0cSJames Hogan
31030dd9e0cSJames Hogan /**
31130dd9e0cSJames Hogan * img_ir_decoder_preprocess() - Preprocess timings in decoder.
31230dd9e0cSJames Hogan * @decoder: Decoder to be preprocessed.
31330dd9e0cSJames Hogan *
31430dd9e0cSJames Hogan * Ensures that the symbol timing ranges are valid with respect to ordering, and
31530dd9e0cSJames Hogan * does some fixed conversion on them.
31630dd9e0cSJames Hogan */
img_ir_decoder_preprocess(struct img_ir_decoder * decoder)31730dd9e0cSJames Hogan static void img_ir_decoder_preprocess(struct img_ir_decoder *decoder)
31830dd9e0cSJames Hogan {
31930dd9e0cSJames Hogan /* default tolerance */
32030dd9e0cSJames Hogan if (!decoder->tolerance)
32130dd9e0cSJames Hogan decoder->tolerance = 10; /* percent */
32230dd9e0cSJames Hogan /* and convert tolerance to fraction out of 128 */
32330dd9e0cSJames Hogan decoder->tolerance = decoder->tolerance * 128 / 100;
32430dd9e0cSJames Hogan
32530dd9e0cSJames Hogan /* fill in implicit fields */
32630dd9e0cSJames Hogan img_ir_timings_preprocess(&decoder->timings, decoder->unit);
32730dd9e0cSJames Hogan
32830dd9e0cSJames Hogan /* do the same for repeat timings if applicable */
32930dd9e0cSJames Hogan if (decoder->repeat) {
33030dd9e0cSJames Hogan img_ir_timings_preprocess(&decoder->rtimings, decoder->unit);
33130dd9e0cSJames Hogan img_ir_timings_defaults(&decoder->rtimings, &decoder->timings);
33230dd9e0cSJames Hogan }
33330dd9e0cSJames Hogan }
33430dd9e0cSJames Hogan
33530dd9e0cSJames Hogan /**
33630dd9e0cSJames Hogan * img_ir_decoder_convert() - Generate internal timings in decoder.
33730dd9e0cSJames Hogan * @decoder: Decoder to be converted to internal timings.
33886850b9aSMauro Carvalho Chehab * @reg_timings: Timing register values.
33930dd9e0cSJames Hogan * @clock_hz: IR clock rate in Hz.
34030dd9e0cSJames Hogan *
34130dd9e0cSJames Hogan * Fills out the repeat timings and timing register values for a specific clock
34230dd9e0cSJames Hogan * rate.
34330dd9e0cSJames Hogan */
img_ir_decoder_convert(const struct img_ir_decoder * decoder,struct img_ir_reg_timings * reg_timings,unsigned int clock_hz)34430dd9e0cSJames Hogan static void img_ir_decoder_convert(const struct img_ir_decoder *decoder,
34530dd9e0cSJames Hogan struct img_ir_reg_timings *reg_timings,
34630dd9e0cSJames Hogan unsigned int clock_hz)
34730dd9e0cSJames Hogan {
34830dd9e0cSJames Hogan /* calculate control value */
34930dd9e0cSJames Hogan reg_timings->ctrl = img_ir_control(&decoder->control);
35030dd9e0cSJames Hogan
35130dd9e0cSJames Hogan /* fill in implicit fields and calculate register values */
35230dd9e0cSJames Hogan img_ir_timings_convert(®_timings->timings, &decoder->timings,
35330dd9e0cSJames Hogan decoder->tolerance, clock_hz);
35430dd9e0cSJames Hogan
35530dd9e0cSJames Hogan /* do the same for repeat timings if applicable */
35630dd9e0cSJames Hogan if (decoder->repeat)
35730dd9e0cSJames Hogan img_ir_timings_convert(®_timings->rtimings,
35830dd9e0cSJames Hogan &decoder->rtimings, decoder->tolerance,
35930dd9e0cSJames Hogan clock_hz);
36030dd9e0cSJames Hogan }
36130dd9e0cSJames Hogan
36230dd9e0cSJames Hogan /**
36330dd9e0cSJames Hogan * img_ir_write_timings() - Write timings to the hardware now
36430dd9e0cSJames Hogan * @priv: IR private data
36530dd9e0cSJames Hogan * @regs: Timing register values to write
36630dd9e0cSJames Hogan * @type: RC filter type (RC_FILTER_*)
36730dd9e0cSJames Hogan *
36830dd9e0cSJames Hogan * Write timing register values @regs to the hardware, taking into account the
36930dd9e0cSJames Hogan * current filter which may impose restrictions on the length of the expected
37030dd9e0cSJames Hogan * data.
37130dd9e0cSJames Hogan */
img_ir_write_timings(struct img_ir_priv * priv,struct img_ir_timing_regvals * regs,enum rc_filter_type type)37230dd9e0cSJames Hogan static void img_ir_write_timings(struct img_ir_priv *priv,
37330dd9e0cSJames Hogan struct img_ir_timing_regvals *regs,
37430dd9e0cSJames Hogan enum rc_filter_type type)
37530dd9e0cSJames Hogan {
37630dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
37730dd9e0cSJames Hogan
37830dd9e0cSJames Hogan /* filter may be more restrictive to minlen, maxlen */
37930dd9e0cSJames Hogan u32 ft = regs->ft;
38030dd9e0cSJames Hogan if (hw->flags & BIT(type))
38130dd9e0cSJames Hogan ft = img_ir_free_timing_dynamic(regs->ft, &hw->filters[type]);
38230dd9e0cSJames Hogan /* write to registers */
38330dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_LEAD_SYMB_TIMING, regs->ldr);
38430dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_S00_SYMB_TIMING, regs->s00);
38530dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_S01_SYMB_TIMING, regs->s01);
38630dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_S10_SYMB_TIMING, regs->s10);
38730dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_S11_SYMB_TIMING, regs->s11);
38830dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_FREE_SYMB_TIMING, ft);
38930dd9e0cSJames Hogan dev_dbg(priv->dev, "timings: ldr=%#x, s=[%#x, %#x, %#x, %#x], ft=%#x\n",
39030dd9e0cSJames Hogan regs->ldr, regs->s00, regs->s01, regs->s10, regs->s11, ft);
39130dd9e0cSJames Hogan }
39230dd9e0cSJames Hogan
img_ir_write_filter(struct img_ir_priv * priv,struct img_ir_filter * filter)39330dd9e0cSJames Hogan static void img_ir_write_filter(struct img_ir_priv *priv,
39430dd9e0cSJames Hogan struct img_ir_filter *filter)
39530dd9e0cSJames Hogan {
39630dd9e0cSJames Hogan if (filter) {
39730dd9e0cSJames Hogan dev_dbg(priv->dev, "IR filter=%016llx & %016llx\n",
39830dd9e0cSJames Hogan (unsigned long long)filter->data,
39930dd9e0cSJames Hogan (unsigned long long)filter->mask);
40030dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_LW, (u32)filter->data);
40130dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_UP, (u32)(filter->data
40230dd9e0cSJames Hogan >> 32));
40330dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, (u32)filter->mask);
40430dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, (u32)(filter->mask
40530dd9e0cSJames Hogan >> 32));
40630dd9e0cSJames Hogan } else {
40730dd9e0cSJames Hogan dev_dbg(priv->dev, "IR clearing filter\n");
40830dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, 0);
40930dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, 0);
41030dd9e0cSJames Hogan }
41130dd9e0cSJames Hogan }
41230dd9e0cSJames Hogan
41330dd9e0cSJames Hogan /* caller must have lock */
_img_ir_set_filter(struct img_ir_priv * priv,struct img_ir_filter * filter)41430dd9e0cSJames Hogan static void _img_ir_set_filter(struct img_ir_priv *priv,
41530dd9e0cSJames Hogan struct img_ir_filter *filter)
41630dd9e0cSJames Hogan {
41730dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
41830dd9e0cSJames Hogan u32 irq_en, irq_on;
41930dd9e0cSJames Hogan
42030dd9e0cSJames Hogan irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE);
42130dd9e0cSJames Hogan if (filter) {
42230dd9e0cSJames Hogan /* Only use the match interrupt */
42330dd9e0cSJames Hogan hw->filters[RC_FILTER_NORMAL] = *filter;
42430dd9e0cSJames Hogan hw->flags |= IMG_IR_F_FILTER;
42530dd9e0cSJames Hogan irq_on = IMG_IR_IRQ_DATA_MATCH;
42630dd9e0cSJames Hogan irq_en &= ~(IMG_IR_IRQ_DATA_VALID | IMG_IR_IRQ_DATA2_VALID);
42730dd9e0cSJames Hogan } else {
42830dd9e0cSJames Hogan /* Only use the valid interrupt */
42930dd9e0cSJames Hogan hw->flags &= ~IMG_IR_F_FILTER;
43030dd9e0cSJames Hogan irq_en &= ~IMG_IR_IRQ_DATA_MATCH;
43130dd9e0cSJames Hogan irq_on = IMG_IR_IRQ_DATA_VALID | IMG_IR_IRQ_DATA2_VALID;
43230dd9e0cSJames Hogan }
43330dd9e0cSJames Hogan irq_en |= irq_on;
43430dd9e0cSJames Hogan
43530dd9e0cSJames Hogan img_ir_write_filter(priv, filter);
43630dd9e0cSJames Hogan /* clear any interrupts we're enabling so we don't handle old ones */
43730dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_CLEAR, irq_on);
43830dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en);
43930dd9e0cSJames Hogan }
44030dd9e0cSJames Hogan
44130dd9e0cSJames Hogan /* caller must have lock */
_img_ir_set_wake_filter(struct img_ir_priv * priv,struct img_ir_filter * filter)44230dd9e0cSJames Hogan static void _img_ir_set_wake_filter(struct img_ir_priv *priv,
44330dd9e0cSJames Hogan struct img_ir_filter *filter)
44430dd9e0cSJames Hogan {
44530dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
44630dd9e0cSJames Hogan if (filter) {
44730dd9e0cSJames Hogan /* Enable wake, and copy filter for later */
44830dd9e0cSJames Hogan hw->filters[RC_FILTER_WAKEUP] = *filter;
44930dd9e0cSJames Hogan hw->flags |= IMG_IR_F_WAKE;
45030dd9e0cSJames Hogan } else {
45130dd9e0cSJames Hogan /* Disable wake */
45230dd9e0cSJames Hogan hw->flags &= ~IMG_IR_F_WAKE;
45330dd9e0cSJames Hogan }
45430dd9e0cSJames Hogan }
45530dd9e0cSJames Hogan
45630dd9e0cSJames Hogan /* Callback for setting scancode filter */
img_ir_set_filter(struct rc_dev * dev,enum rc_filter_type type,struct rc_scancode_filter * sc_filter)45730dd9e0cSJames Hogan static int img_ir_set_filter(struct rc_dev *dev, enum rc_filter_type type,
45830dd9e0cSJames Hogan struct rc_scancode_filter *sc_filter)
45930dd9e0cSJames Hogan {
46030dd9e0cSJames Hogan struct img_ir_priv *priv = dev->priv;
46130dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
46230dd9e0cSJames Hogan struct img_ir_filter filter, *filter_ptr = &filter;
46330dd9e0cSJames Hogan int ret = 0;
46430dd9e0cSJames Hogan
46530dd9e0cSJames Hogan dev_dbg(priv->dev, "IR scancode %sfilter=%08x & %08x\n",
46630dd9e0cSJames Hogan type == RC_FILTER_WAKEUP ? "wake " : "",
46730dd9e0cSJames Hogan sc_filter->data,
46830dd9e0cSJames Hogan sc_filter->mask);
46930dd9e0cSJames Hogan
47030dd9e0cSJames Hogan spin_lock_irq(&priv->lock);
47130dd9e0cSJames Hogan
47230dd9e0cSJames Hogan /* filtering can always be disabled */
47330dd9e0cSJames Hogan if (!sc_filter->mask) {
47430dd9e0cSJames Hogan filter_ptr = NULL;
47530dd9e0cSJames Hogan goto set_unlock;
47630dd9e0cSJames Hogan }
47730dd9e0cSJames Hogan
47830dd9e0cSJames Hogan /* current decoder must support scancode filtering */
47930dd9e0cSJames Hogan if (!hw->decoder || !hw->decoder->filter) {
48030dd9e0cSJames Hogan ret = -EINVAL;
48130dd9e0cSJames Hogan goto unlock;
48230dd9e0cSJames Hogan }
48330dd9e0cSJames Hogan
48430dd9e0cSJames Hogan /* convert scancode filter to raw filter */
48530dd9e0cSJames Hogan filter.minlen = 0;
48630dd9e0cSJames Hogan filter.maxlen = ~0;
4870751d33cSSean Young if (type == RC_FILTER_NORMAL) {
4880751d33cSSean Young /* guess scancode from protocol */
4890751d33cSSean Young ret = hw->decoder->filter(sc_filter, &filter,
4900751d33cSSean Young dev->enabled_protocols);
4910751d33cSSean Young } else {
4920751d33cSSean Young /* for wakeup user provided exact protocol variant */
4930751d33cSSean Young ret = hw->decoder->filter(sc_filter, &filter,
4940751d33cSSean Young 1ULL << dev->wakeup_protocol);
4950751d33cSSean Young }
49630dd9e0cSJames Hogan if (ret)
49730dd9e0cSJames Hogan goto unlock;
49830dd9e0cSJames Hogan dev_dbg(priv->dev, "IR raw %sfilter=%016llx & %016llx\n",
49930dd9e0cSJames Hogan type == RC_FILTER_WAKEUP ? "wake " : "",
50030dd9e0cSJames Hogan (unsigned long long)filter.data,
50130dd9e0cSJames Hogan (unsigned long long)filter.mask);
50230dd9e0cSJames Hogan
50330dd9e0cSJames Hogan set_unlock:
50430dd9e0cSJames Hogan /* apply raw filters */
50530dd9e0cSJames Hogan switch (type) {
50630dd9e0cSJames Hogan case RC_FILTER_NORMAL:
50730dd9e0cSJames Hogan _img_ir_set_filter(priv, filter_ptr);
50830dd9e0cSJames Hogan break;
50930dd9e0cSJames Hogan case RC_FILTER_WAKEUP:
51030dd9e0cSJames Hogan _img_ir_set_wake_filter(priv, filter_ptr);
51130dd9e0cSJames Hogan break;
51230dd9e0cSJames Hogan default:
51330dd9e0cSJames Hogan ret = -EINVAL;
51454ece68dSJames Hogan }
51530dd9e0cSJames Hogan
51630dd9e0cSJames Hogan unlock:
51730dd9e0cSJames Hogan spin_unlock_irq(&priv->lock);
51830dd9e0cSJames Hogan return ret;
51930dd9e0cSJames Hogan }
52030dd9e0cSJames Hogan
img_ir_set_normal_filter(struct rc_dev * dev,struct rc_scancode_filter * sc_filter)52123c843b5SDavid Härdeman static int img_ir_set_normal_filter(struct rc_dev *dev,
52223c843b5SDavid Härdeman struct rc_scancode_filter *sc_filter)
52323c843b5SDavid Härdeman {
52423c843b5SDavid Härdeman return img_ir_set_filter(dev, RC_FILTER_NORMAL, sc_filter);
52523c843b5SDavid Härdeman }
52623c843b5SDavid Härdeman
img_ir_set_wakeup_filter(struct rc_dev * dev,struct rc_scancode_filter * sc_filter)52723c843b5SDavid Härdeman static int img_ir_set_wakeup_filter(struct rc_dev *dev,
52823c843b5SDavid Härdeman struct rc_scancode_filter *sc_filter)
52923c843b5SDavid Härdeman {
53023c843b5SDavid Härdeman return img_ir_set_filter(dev, RC_FILTER_WAKEUP, sc_filter);
53123c843b5SDavid Härdeman }
53223c843b5SDavid Härdeman
53330dd9e0cSJames Hogan /**
53430dd9e0cSJames Hogan * img_ir_set_decoder() - Set the current decoder.
53530dd9e0cSJames Hogan * @priv: IR private data.
53630dd9e0cSJames Hogan * @decoder: Decoder to use with immediate effect.
53730dd9e0cSJames Hogan * @proto: Protocol bitmap (or 0 to use decoder->type).
53830dd9e0cSJames Hogan */
img_ir_set_decoder(struct img_ir_priv * priv,const struct img_ir_decoder * decoder,u64 proto)53930dd9e0cSJames Hogan static void img_ir_set_decoder(struct img_ir_priv *priv,
54030dd9e0cSJames Hogan const struct img_ir_decoder *decoder,
54130dd9e0cSJames Hogan u64 proto)
54230dd9e0cSJames Hogan {
54330dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
54430dd9e0cSJames Hogan struct rc_dev *rdev = hw->rdev;
54530dd9e0cSJames Hogan u32 ir_status, irq_en;
54630dd9e0cSJames Hogan spin_lock_irq(&priv->lock);
54730dd9e0cSJames Hogan
548ac030860SJames Hogan /*
549ac030860SJames Hogan * First record that the protocol is being stopped so that the end timer
550ac030860SJames Hogan * isn't restarted while we're trying to stop it.
551ac030860SJames Hogan */
552ac030860SJames Hogan hw->stopping = true;
553ac030860SJames Hogan
554ac030860SJames Hogan /*
555ac030860SJames Hogan * Release the lock to stop the end timer, since the end timer handler
556ac030860SJames Hogan * acquires the lock and we don't want to deadlock waiting for it.
557ac030860SJames Hogan */
558ac030860SJames Hogan spin_unlock_irq(&priv->lock);
559ac030860SJames Hogan del_timer_sync(&hw->end_timer);
56002744c8cSSifan Naeem del_timer_sync(&hw->suspend_timer);
561ac030860SJames Hogan spin_lock_irq(&priv->lock);
562ac030860SJames Hogan
563ac030860SJames Hogan hw->stopping = false;
564ac030860SJames Hogan
56530dd9e0cSJames Hogan /* switch off and disable interrupts */
56630dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_CONTROL, 0);
56730dd9e0cSJames Hogan irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE);
56830dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en & IMG_IR_IRQ_EDGE);
56930dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_ALL & ~IMG_IR_IRQ_EDGE);
57030dd9e0cSJames Hogan
57130dd9e0cSJames Hogan /* ack any data already detected */
57230dd9e0cSJames Hogan ir_status = img_ir_read(priv, IMG_IR_STATUS);
57330dd9e0cSJames Hogan if (ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2)) {
57430dd9e0cSJames Hogan ir_status &= ~(IMG_IR_RXDVAL | IMG_IR_RXDVALD2);
57530dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_STATUS, ir_status);
576ea0de4ecSDylan Rajaratnam }
577ea0de4ecSDylan Rajaratnam
578ea0de4ecSDylan Rajaratnam /* always read data to clear buffer if IR wakes the device */
57930dd9e0cSJames Hogan img_ir_read(priv, IMG_IR_DATA_LW);
58030dd9e0cSJames Hogan img_ir_read(priv, IMG_IR_DATA_UP);
58130dd9e0cSJames Hogan
582ac030860SJames Hogan /* switch back to normal mode */
58330dd9e0cSJames Hogan hw->mode = IMG_IR_M_NORMAL;
58430dd9e0cSJames Hogan
58530dd9e0cSJames Hogan /* clear the wakeup scancode filter */
586c5540fbbSDavid Härdeman rdev->scancode_wakeup_filter.data = 0;
587c5540fbbSDavid Härdeman rdev->scancode_wakeup_filter.mask = 0;
5886d741bfeSSean Young rdev->wakeup_protocol = RC_PROTO_UNKNOWN;
58930dd9e0cSJames Hogan
59030dd9e0cSJames Hogan /* clear raw filters */
59130dd9e0cSJames Hogan _img_ir_set_filter(priv, NULL);
59230dd9e0cSJames Hogan _img_ir_set_wake_filter(priv, NULL);
59330dd9e0cSJames Hogan
59430dd9e0cSJames Hogan /* clear the enabled protocols */
59530dd9e0cSJames Hogan hw->enabled_protocols = 0;
59630dd9e0cSJames Hogan
59730dd9e0cSJames Hogan /* switch decoder */
59830dd9e0cSJames Hogan hw->decoder = decoder;
59930dd9e0cSJames Hogan if (!decoder)
60030dd9e0cSJames Hogan goto unlock;
60130dd9e0cSJames Hogan
60230dd9e0cSJames Hogan /* set the enabled protocols */
60330dd9e0cSJames Hogan if (!proto)
60430dd9e0cSJames Hogan proto = decoder->type;
60530dd9e0cSJames Hogan hw->enabled_protocols = proto;
60630dd9e0cSJames Hogan
60730dd9e0cSJames Hogan /* write the new timings */
60830dd9e0cSJames Hogan img_ir_decoder_convert(decoder, &hw->reg_timings, hw->clk_hz);
60930dd9e0cSJames Hogan img_ir_write_timings(priv, &hw->reg_timings.timings, RC_FILTER_NORMAL);
61030dd9e0cSJames Hogan
61130dd9e0cSJames Hogan /* set up and enable */
61230dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl);
61330dd9e0cSJames Hogan
61430dd9e0cSJames Hogan
61530dd9e0cSJames Hogan unlock:
61630dd9e0cSJames Hogan spin_unlock_irq(&priv->lock);
61730dd9e0cSJames Hogan }
61830dd9e0cSJames Hogan
61930dd9e0cSJames Hogan /**
620*a4184b4fSHans Verkuil * img_ir_decoder_compatible() - Find whether a decoder will work with a device.
62130dd9e0cSJames Hogan * @priv: IR private data.
62230dd9e0cSJames Hogan * @dec: Decoder to check.
62330dd9e0cSJames Hogan *
62430dd9e0cSJames Hogan * Returns: true if @dec is compatible with the device @priv refers to.
62530dd9e0cSJames Hogan */
img_ir_decoder_compatible(struct img_ir_priv * priv,const struct img_ir_decoder * dec)62630dd9e0cSJames Hogan static bool img_ir_decoder_compatible(struct img_ir_priv *priv,
62730dd9e0cSJames Hogan const struct img_ir_decoder *dec)
62830dd9e0cSJames Hogan {
62930dd9e0cSJames Hogan unsigned int ct;
63030dd9e0cSJames Hogan
63130dd9e0cSJames Hogan /* don't accept decoders using code types which aren't supported */
63230dd9e0cSJames Hogan ct = dec->control.code_type;
63330dd9e0cSJames Hogan if (priv->hw.ct_quirks[ct] & IMG_IR_QUIRK_CODE_BROKEN)
63430dd9e0cSJames Hogan return false;
63530dd9e0cSJames Hogan
63630dd9e0cSJames Hogan return true;
63730dd9e0cSJames Hogan }
63830dd9e0cSJames Hogan
63930dd9e0cSJames Hogan /**
64030dd9e0cSJames Hogan * img_ir_allowed_protos() - Get allowed protocols from global decoder list.
64130dd9e0cSJames Hogan * @priv: IR private data.
64230dd9e0cSJames Hogan *
64330dd9e0cSJames Hogan * Returns: Mask of protocols supported by the device @priv refers to.
64430dd9e0cSJames Hogan */
img_ir_allowed_protos(struct img_ir_priv * priv)64530dd9e0cSJames Hogan static u64 img_ir_allowed_protos(struct img_ir_priv *priv)
64630dd9e0cSJames Hogan {
64730dd9e0cSJames Hogan u64 protos = 0;
64830dd9e0cSJames Hogan struct img_ir_decoder **decp;
64930dd9e0cSJames Hogan
65030dd9e0cSJames Hogan for (decp = img_ir_decoders; *decp; ++decp) {
65130dd9e0cSJames Hogan const struct img_ir_decoder *dec = *decp;
65230dd9e0cSJames Hogan if (img_ir_decoder_compatible(priv, dec))
65330dd9e0cSJames Hogan protos |= dec->type;
65430dd9e0cSJames Hogan }
65530dd9e0cSJames Hogan return protos;
65630dd9e0cSJames Hogan }
65730dd9e0cSJames Hogan
65830dd9e0cSJames Hogan /* Callback for changing protocol using sysfs */
img_ir_change_protocol(struct rc_dev * dev,u64 * ir_type)65930dd9e0cSJames Hogan static int img_ir_change_protocol(struct rc_dev *dev, u64 *ir_type)
66030dd9e0cSJames Hogan {
66130dd9e0cSJames Hogan struct img_ir_priv *priv = dev->priv;
66230dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
66330dd9e0cSJames Hogan struct rc_dev *rdev = hw->rdev;
66430dd9e0cSJames Hogan struct img_ir_decoder **decp;
66530dd9e0cSJames Hogan u64 wakeup_protocols;
66630dd9e0cSJames Hogan
66730dd9e0cSJames Hogan if (!*ir_type) {
66830dd9e0cSJames Hogan /* disable all protocols */
66930dd9e0cSJames Hogan img_ir_set_decoder(priv, NULL, 0);
67030dd9e0cSJames Hogan goto success;
67130dd9e0cSJames Hogan }
67230dd9e0cSJames Hogan for (decp = img_ir_decoders; *decp; ++decp) {
67330dd9e0cSJames Hogan const struct img_ir_decoder *dec = *decp;
67430dd9e0cSJames Hogan if (!img_ir_decoder_compatible(priv, dec))
67530dd9e0cSJames Hogan continue;
67630dd9e0cSJames Hogan if (*ir_type & dec->type) {
67730dd9e0cSJames Hogan *ir_type &= dec->type;
67830dd9e0cSJames Hogan img_ir_set_decoder(priv, dec, *ir_type);
67930dd9e0cSJames Hogan goto success;
68030dd9e0cSJames Hogan }
68130dd9e0cSJames Hogan }
68230dd9e0cSJames Hogan return -EINVAL;
68330dd9e0cSJames Hogan
68430dd9e0cSJames Hogan success:
68530dd9e0cSJames Hogan /*
68630dd9e0cSJames Hogan * Only allow matching wakeup protocols for now, and only if filtering
68730dd9e0cSJames Hogan * is supported.
68830dd9e0cSJames Hogan */
68930dd9e0cSJames Hogan wakeup_protocols = *ir_type;
69030dd9e0cSJames Hogan if (!hw->decoder || !hw->decoder->filter)
69130dd9e0cSJames Hogan wakeup_protocols = 0;
692c5540fbbSDavid Härdeman rdev->allowed_wakeup_protocols = wakeup_protocols;
69330dd9e0cSJames Hogan return 0;
69430dd9e0cSJames Hogan }
69530dd9e0cSJames Hogan
69630dd9e0cSJames Hogan /* Changes ir-core protocol device attribute */
img_ir_set_protocol(struct img_ir_priv * priv,u64 proto)69730dd9e0cSJames Hogan static void img_ir_set_protocol(struct img_ir_priv *priv, u64 proto)
69830dd9e0cSJames Hogan {
69930dd9e0cSJames Hogan struct rc_dev *rdev = priv->hw.rdev;
70030dd9e0cSJames Hogan
70130dd9e0cSJames Hogan mutex_lock(&rdev->lock);
702c5540fbbSDavid Härdeman rdev->enabled_protocols = proto;
703c5540fbbSDavid Härdeman rdev->allowed_wakeup_protocols = proto;
70430dd9e0cSJames Hogan mutex_unlock(&rdev->lock);
70530dd9e0cSJames Hogan }
70630dd9e0cSJames Hogan
70730dd9e0cSJames Hogan /* Set up IR decoders */
img_ir_init_decoders(void)70830dd9e0cSJames Hogan static void img_ir_init_decoders(void)
70930dd9e0cSJames Hogan {
71030dd9e0cSJames Hogan struct img_ir_decoder **decp;
71130dd9e0cSJames Hogan
71230dd9e0cSJames Hogan spin_lock(&img_ir_decoders_lock);
71330dd9e0cSJames Hogan if (!img_ir_decoders_preprocessed) {
71430dd9e0cSJames Hogan for (decp = img_ir_decoders; *decp; ++decp)
71530dd9e0cSJames Hogan img_ir_decoder_preprocess(*decp);
71630dd9e0cSJames Hogan img_ir_decoders_preprocessed = true;
71730dd9e0cSJames Hogan }
71830dd9e0cSJames Hogan spin_unlock(&img_ir_decoders_lock);
71930dd9e0cSJames Hogan }
72030dd9e0cSJames Hogan
72130dd9e0cSJames Hogan #ifdef CONFIG_PM_SLEEP
72230dd9e0cSJames Hogan /**
72330dd9e0cSJames Hogan * img_ir_enable_wake() - Switch to wake mode.
72430dd9e0cSJames Hogan * @priv: IR private data.
72530dd9e0cSJames Hogan *
72630dd9e0cSJames Hogan * Returns: non-zero if the IR can wake the system.
72730dd9e0cSJames Hogan */
img_ir_enable_wake(struct img_ir_priv * priv)72830dd9e0cSJames Hogan static int img_ir_enable_wake(struct img_ir_priv *priv)
72930dd9e0cSJames Hogan {
73030dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
73130dd9e0cSJames Hogan int ret = 0;
73230dd9e0cSJames Hogan
73330dd9e0cSJames Hogan spin_lock_irq(&priv->lock);
73430dd9e0cSJames Hogan if (hw->flags & IMG_IR_F_WAKE) {
73530dd9e0cSJames Hogan /* interrupt only on a match */
73630dd9e0cSJames Hogan hw->suspend_irqen = img_ir_read(priv, IMG_IR_IRQ_ENABLE);
73730dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_DATA_MATCH);
73830dd9e0cSJames Hogan img_ir_write_filter(priv, &hw->filters[RC_FILTER_WAKEUP]);
73930dd9e0cSJames Hogan img_ir_write_timings(priv, &hw->reg_timings.timings,
74030dd9e0cSJames Hogan RC_FILTER_WAKEUP);
74130dd9e0cSJames Hogan hw->mode = IMG_IR_M_WAKE;
74230dd9e0cSJames Hogan ret = 1;
74330dd9e0cSJames Hogan }
74430dd9e0cSJames Hogan spin_unlock_irq(&priv->lock);
74530dd9e0cSJames Hogan return ret;
74630dd9e0cSJames Hogan }
74730dd9e0cSJames Hogan
74830dd9e0cSJames Hogan /**
74930dd9e0cSJames Hogan * img_ir_disable_wake() - Switch out of wake mode.
75030dd9e0cSJames Hogan * @priv: IR private data
75130dd9e0cSJames Hogan *
75230dd9e0cSJames Hogan * Returns: 1 if the hardware should be allowed to wake from a sleep state.
75330dd9e0cSJames Hogan * 0 otherwise.
75430dd9e0cSJames Hogan */
img_ir_disable_wake(struct img_ir_priv * priv)75530dd9e0cSJames Hogan static int img_ir_disable_wake(struct img_ir_priv *priv)
75630dd9e0cSJames Hogan {
75730dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
75830dd9e0cSJames Hogan int ret = 0;
75930dd9e0cSJames Hogan
76030dd9e0cSJames Hogan spin_lock_irq(&priv->lock);
76130dd9e0cSJames Hogan if (hw->flags & IMG_IR_F_WAKE) {
76230dd9e0cSJames Hogan /* restore normal filtering */
76330dd9e0cSJames Hogan if (hw->flags & IMG_IR_F_FILTER) {
76430dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_ENABLE,
76530dd9e0cSJames Hogan (hw->suspend_irqen & IMG_IR_IRQ_EDGE) |
76630dd9e0cSJames Hogan IMG_IR_IRQ_DATA_MATCH);
76730dd9e0cSJames Hogan img_ir_write_filter(priv,
76830dd9e0cSJames Hogan &hw->filters[RC_FILTER_NORMAL]);
76930dd9e0cSJames Hogan } else {
77030dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_IRQ_ENABLE,
77130dd9e0cSJames Hogan (hw->suspend_irqen & IMG_IR_IRQ_EDGE) |
77230dd9e0cSJames Hogan IMG_IR_IRQ_DATA_VALID |
77330dd9e0cSJames Hogan IMG_IR_IRQ_DATA2_VALID);
77430dd9e0cSJames Hogan img_ir_write_filter(priv, NULL);
77530dd9e0cSJames Hogan }
77630dd9e0cSJames Hogan img_ir_write_timings(priv, &hw->reg_timings.timings,
77730dd9e0cSJames Hogan RC_FILTER_NORMAL);
77830dd9e0cSJames Hogan hw->mode = IMG_IR_M_NORMAL;
77930dd9e0cSJames Hogan ret = 1;
78030dd9e0cSJames Hogan }
78130dd9e0cSJames Hogan spin_unlock_irq(&priv->lock);
78230dd9e0cSJames Hogan return ret;
78330dd9e0cSJames Hogan }
78430dd9e0cSJames Hogan #endif /* CONFIG_PM_SLEEP */
78530dd9e0cSJames Hogan
78630dd9e0cSJames Hogan /* lock must be held */
img_ir_begin_repeat(struct img_ir_priv * priv)78730dd9e0cSJames Hogan static void img_ir_begin_repeat(struct img_ir_priv *priv)
78830dd9e0cSJames Hogan {
78930dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
79030dd9e0cSJames Hogan if (hw->mode == IMG_IR_M_NORMAL) {
79130dd9e0cSJames Hogan /* switch to repeat timings */
79230dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_CONTROL, 0);
79330dd9e0cSJames Hogan hw->mode = IMG_IR_M_REPEATING;
79430dd9e0cSJames Hogan img_ir_write_timings(priv, &hw->reg_timings.rtimings,
79530dd9e0cSJames Hogan RC_FILTER_NORMAL);
79630dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl);
79730dd9e0cSJames Hogan }
79830dd9e0cSJames Hogan }
79930dd9e0cSJames Hogan
80030dd9e0cSJames Hogan /* lock must be held */
img_ir_end_repeat(struct img_ir_priv * priv)80130dd9e0cSJames Hogan static void img_ir_end_repeat(struct img_ir_priv *priv)
80230dd9e0cSJames Hogan {
80330dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
80430dd9e0cSJames Hogan if (hw->mode == IMG_IR_M_REPEATING) {
80530dd9e0cSJames Hogan /* switch to normal timings */
80630dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_CONTROL, 0);
80730dd9e0cSJames Hogan hw->mode = IMG_IR_M_NORMAL;
80830dd9e0cSJames Hogan img_ir_write_timings(priv, &hw->reg_timings.timings,
80930dd9e0cSJames Hogan RC_FILTER_NORMAL);
81030dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl);
81130dd9e0cSJames Hogan }
81230dd9e0cSJames Hogan }
81330dd9e0cSJames Hogan
81430dd9e0cSJames Hogan /* lock must be held */
img_ir_handle_data(struct img_ir_priv * priv,u32 len,u64 raw)81530dd9e0cSJames Hogan static void img_ir_handle_data(struct img_ir_priv *priv, u32 len, u64 raw)
81630dd9e0cSJames Hogan {
81730dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
81830dd9e0cSJames Hogan const struct img_ir_decoder *dec = hw->decoder;
81930dd9e0cSJames Hogan int ret = IMG_IR_SCANCODE;
820ab93ce06SSifan Naeem struct img_ir_scancode_req request;
821ab93ce06SSifan Naeem
8226d741bfeSSean Young request.protocol = RC_PROTO_UNKNOWN;
82333e01833SSifan Naeem request.toggle = 0;
824120703f9SDavid Härdeman
82530dd9e0cSJames Hogan if (dec->scancode)
826ab93ce06SSifan Naeem ret = dec->scancode(len, raw, hw->enabled_protocols, &request);
82730dd9e0cSJames Hogan else if (len >= 32)
828ab93ce06SSifan Naeem request.scancode = (u32)raw;
82930dd9e0cSJames Hogan else if (len < 32)
830ab93ce06SSifan Naeem request.scancode = (u32)raw & ((1 << len)-1);
83130dd9e0cSJames Hogan dev_dbg(priv->dev, "data (%u bits) = %#llx\n",
83230dd9e0cSJames Hogan len, (unsigned long long)raw);
83330dd9e0cSJames Hogan if (ret == IMG_IR_SCANCODE) {
83433e01833SSifan Naeem dev_dbg(priv->dev, "decoded scan code %#x, toggle %u\n",
83533e01833SSifan Naeem request.scancode, request.toggle);
83633e01833SSifan Naeem rc_keydown(hw->rdev, request.protocol, request.scancode,
83733e01833SSifan Naeem request.toggle);
83830dd9e0cSJames Hogan img_ir_end_repeat(priv);
83930dd9e0cSJames Hogan } else if (ret == IMG_IR_REPEATCODE) {
84030dd9e0cSJames Hogan if (hw->mode == IMG_IR_M_REPEATING) {
84130dd9e0cSJames Hogan dev_dbg(priv->dev, "decoded repeat code\n");
84230dd9e0cSJames Hogan rc_repeat(hw->rdev);
84330dd9e0cSJames Hogan } else {
84430dd9e0cSJames Hogan dev_dbg(priv->dev, "decoded unexpected repeat code, ignoring\n");
84530dd9e0cSJames Hogan }
84630dd9e0cSJames Hogan } else {
84730dd9e0cSJames Hogan dev_dbg(priv->dev, "decode failed (%d)\n", ret);
84830dd9e0cSJames Hogan return;
84930dd9e0cSJames Hogan }
85030dd9e0cSJames Hogan
85130dd9e0cSJames Hogan
852ac030860SJames Hogan /* we mustn't update the end timer while trying to stop it */
853ac030860SJames Hogan if (dec->repeat && !hw->stopping) {
85430dd9e0cSJames Hogan unsigned long interval;
85530dd9e0cSJames Hogan
85630dd9e0cSJames Hogan img_ir_begin_repeat(priv);
85730dd9e0cSJames Hogan
85830dd9e0cSJames Hogan /* update timer, but allowing for 1/8th tolerance */
85930dd9e0cSJames Hogan interval = dec->repeat + (dec->repeat >> 3);
86030dd9e0cSJames Hogan mod_timer(&hw->end_timer,
86130dd9e0cSJames Hogan jiffies + msecs_to_jiffies(interval));
86230dd9e0cSJames Hogan }
86330dd9e0cSJames Hogan }
86430dd9e0cSJames Hogan
86530dd9e0cSJames Hogan /* timer function to end waiting for repeat. */
img_ir_end_timer(struct timer_list * t)866b17ec78aSKees Cook static void img_ir_end_timer(struct timer_list *t)
86730dd9e0cSJames Hogan {
868b17ec78aSKees Cook struct img_ir_priv *priv = from_timer(priv, t, hw.end_timer);
86930dd9e0cSJames Hogan
87030dd9e0cSJames Hogan spin_lock_irq(&priv->lock);
87130dd9e0cSJames Hogan img_ir_end_repeat(priv);
87230dd9e0cSJames Hogan spin_unlock_irq(&priv->lock);
87330dd9e0cSJames Hogan }
87430dd9e0cSJames Hogan
87502744c8cSSifan Naeem /*
87602744c8cSSifan Naeem * Timer function to re-enable the current protocol after it had been
87702744c8cSSifan Naeem * cleared when invalid interrupts were generated due to a quirk in the
87802744c8cSSifan Naeem * img-ir decoder.
87902744c8cSSifan Naeem */
img_ir_suspend_timer(struct timer_list * t)880b17ec78aSKees Cook static void img_ir_suspend_timer(struct timer_list *t)
88102744c8cSSifan Naeem {
882b17ec78aSKees Cook struct img_ir_priv *priv = from_timer(priv, t, hw.suspend_timer);
88302744c8cSSifan Naeem
88402744c8cSSifan Naeem spin_lock_irq(&priv->lock);
88502744c8cSSifan Naeem /*
88602744c8cSSifan Naeem * Don't overwrite enabled valid/match IRQs if they have already been
88702744c8cSSifan Naeem * changed by e.g. a filter change.
88802744c8cSSifan Naeem */
88902744c8cSSifan Naeem if ((priv->hw.quirk_suspend_irq & IMG_IR_IRQ_EDGE) ==
89002744c8cSSifan Naeem img_ir_read(priv, IMG_IR_IRQ_ENABLE))
89102744c8cSSifan Naeem img_ir_write(priv, IMG_IR_IRQ_ENABLE,
89202744c8cSSifan Naeem priv->hw.quirk_suspend_irq);
89302744c8cSSifan Naeem /* enable */
89402744c8cSSifan Naeem img_ir_write(priv, IMG_IR_CONTROL, priv->hw.reg_timings.ctrl);
89502744c8cSSifan Naeem spin_unlock_irq(&priv->lock);
89602744c8cSSifan Naeem }
89702744c8cSSifan Naeem
89830dd9e0cSJames Hogan #ifdef CONFIG_COMMON_CLK
img_ir_change_frequency(struct img_ir_priv * priv,struct clk_notifier_data * change)89930dd9e0cSJames Hogan static void img_ir_change_frequency(struct img_ir_priv *priv,
90030dd9e0cSJames Hogan struct clk_notifier_data *change)
90130dd9e0cSJames Hogan {
90230dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
90330dd9e0cSJames Hogan
90430dd9e0cSJames Hogan dev_dbg(priv->dev, "clk changed %lu HZ -> %lu HZ\n",
90530dd9e0cSJames Hogan change->old_rate, change->new_rate);
90630dd9e0cSJames Hogan
90730dd9e0cSJames Hogan spin_lock_irq(&priv->lock);
90830dd9e0cSJames Hogan if (hw->clk_hz == change->new_rate)
90930dd9e0cSJames Hogan goto unlock;
91030dd9e0cSJames Hogan hw->clk_hz = change->new_rate;
91130dd9e0cSJames Hogan /* refresh current timings */
91230dd9e0cSJames Hogan if (hw->decoder) {
91330dd9e0cSJames Hogan img_ir_decoder_convert(hw->decoder, &hw->reg_timings,
91430dd9e0cSJames Hogan hw->clk_hz);
91530dd9e0cSJames Hogan switch (hw->mode) {
91630dd9e0cSJames Hogan case IMG_IR_M_NORMAL:
91730dd9e0cSJames Hogan img_ir_write_timings(priv, &hw->reg_timings.timings,
91830dd9e0cSJames Hogan RC_FILTER_NORMAL);
91930dd9e0cSJames Hogan break;
92030dd9e0cSJames Hogan case IMG_IR_M_REPEATING:
92130dd9e0cSJames Hogan img_ir_write_timings(priv, &hw->reg_timings.rtimings,
92230dd9e0cSJames Hogan RC_FILTER_NORMAL);
92330dd9e0cSJames Hogan break;
92430dd9e0cSJames Hogan #ifdef CONFIG_PM_SLEEP
92530dd9e0cSJames Hogan case IMG_IR_M_WAKE:
92630dd9e0cSJames Hogan img_ir_write_timings(priv, &hw->reg_timings.timings,
92730dd9e0cSJames Hogan RC_FILTER_WAKEUP);
92830dd9e0cSJames Hogan break;
92930dd9e0cSJames Hogan #endif
93030dd9e0cSJames Hogan }
93130dd9e0cSJames Hogan }
93230dd9e0cSJames Hogan unlock:
93330dd9e0cSJames Hogan spin_unlock_irq(&priv->lock);
93430dd9e0cSJames Hogan }
93530dd9e0cSJames Hogan
img_ir_clk_notify(struct notifier_block * self,unsigned long action,void * data)93630dd9e0cSJames Hogan static int img_ir_clk_notify(struct notifier_block *self, unsigned long action,
93730dd9e0cSJames Hogan void *data)
93830dd9e0cSJames Hogan {
93930dd9e0cSJames Hogan struct img_ir_priv *priv = container_of(self, struct img_ir_priv,
94030dd9e0cSJames Hogan hw.clk_nb);
94130dd9e0cSJames Hogan switch (action) {
94230dd9e0cSJames Hogan case POST_RATE_CHANGE:
94330dd9e0cSJames Hogan img_ir_change_frequency(priv, data);
94430dd9e0cSJames Hogan break;
94530dd9e0cSJames Hogan default:
94630dd9e0cSJames Hogan break;
94730dd9e0cSJames Hogan }
94830dd9e0cSJames Hogan return NOTIFY_OK;
94930dd9e0cSJames Hogan }
95030dd9e0cSJames Hogan #endif /* CONFIG_COMMON_CLK */
95130dd9e0cSJames Hogan
95230dd9e0cSJames Hogan /* called with priv->lock held */
img_ir_isr_hw(struct img_ir_priv * priv,u32 irq_status)95330dd9e0cSJames Hogan void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status)
95430dd9e0cSJames Hogan {
95530dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
95630dd9e0cSJames Hogan u32 ir_status, len, lw, up;
95730dd9e0cSJames Hogan unsigned int ct;
95830dd9e0cSJames Hogan
95930dd9e0cSJames Hogan /* use the current decoder */
96030dd9e0cSJames Hogan if (!hw->decoder)
96130dd9e0cSJames Hogan return;
96230dd9e0cSJames Hogan
96302744c8cSSifan Naeem ct = hw->decoder->control.code_type;
96402744c8cSSifan Naeem
96530dd9e0cSJames Hogan ir_status = img_ir_read(priv, IMG_IR_STATUS);
96602744c8cSSifan Naeem if (!(ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2))) {
96702744c8cSSifan Naeem if (!(priv->hw.ct_quirks[ct] & IMG_IR_QUIRK_CODE_IRQ) ||
96802744c8cSSifan Naeem hw->stopping)
96930dd9e0cSJames Hogan return;
97002744c8cSSifan Naeem /*
97102744c8cSSifan Naeem * The below functionality is added as a work around to stop
97202744c8cSSifan Naeem * multiple Interrupts generated when an incomplete IR code is
97302744c8cSSifan Naeem * received by the decoder.
97402744c8cSSifan Naeem * The decoder generates rapid interrupts without actually
97502744c8cSSifan Naeem * having received any new data. After a single interrupt it's
97602744c8cSSifan Naeem * expected to clear up, but instead multiple interrupts are
97702744c8cSSifan Naeem * rapidly generated. only way to get out of this loop is to
97802744c8cSSifan Naeem * reset the control register after a short delay.
97902744c8cSSifan Naeem */
98002744c8cSSifan Naeem img_ir_write(priv, IMG_IR_CONTROL, 0);
98102744c8cSSifan Naeem hw->quirk_suspend_irq = img_ir_read(priv, IMG_IR_IRQ_ENABLE);
98202744c8cSSifan Naeem img_ir_write(priv, IMG_IR_IRQ_ENABLE,
98302744c8cSSifan Naeem hw->quirk_suspend_irq & IMG_IR_IRQ_EDGE);
98402744c8cSSifan Naeem
98502744c8cSSifan Naeem /* Timer activated to re-enable the protocol. */
98602744c8cSSifan Naeem mod_timer(&hw->suspend_timer,
98702744c8cSSifan Naeem jiffies + msecs_to_jiffies(5));
98802744c8cSSifan Naeem return;
98902744c8cSSifan Naeem }
99030dd9e0cSJames Hogan ir_status &= ~(IMG_IR_RXDVAL | IMG_IR_RXDVALD2);
99130dd9e0cSJames Hogan img_ir_write(priv, IMG_IR_STATUS, ir_status);
99230dd9e0cSJames Hogan
99330dd9e0cSJames Hogan len = (ir_status & IMG_IR_RXDLEN) >> IMG_IR_RXDLEN_SHIFT;
99430dd9e0cSJames Hogan /* some versions report wrong length for certain code types */
99530dd9e0cSJames Hogan if (hw->ct_quirks[ct] & IMG_IR_QUIRK_CODE_LEN_INCR)
99630dd9e0cSJames Hogan ++len;
99730dd9e0cSJames Hogan
99830dd9e0cSJames Hogan lw = img_ir_read(priv, IMG_IR_DATA_LW);
99930dd9e0cSJames Hogan up = img_ir_read(priv, IMG_IR_DATA_UP);
100030dd9e0cSJames Hogan img_ir_handle_data(priv, len, (u64)up << 32 | lw);
100130dd9e0cSJames Hogan }
100230dd9e0cSJames Hogan
img_ir_setup_hw(struct img_ir_priv * priv)100330dd9e0cSJames Hogan void img_ir_setup_hw(struct img_ir_priv *priv)
100430dd9e0cSJames Hogan {
100530dd9e0cSJames Hogan struct img_ir_decoder **decp;
100630dd9e0cSJames Hogan
100730dd9e0cSJames Hogan if (!priv->hw.rdev)
100830dd9e0cSJames Hogan return;
100930dd9e0cSJames Hogan
101030dd9e0cSJames Hogan /* Use the first available decoder (or disable stuff if NULL) */
101130dd9e0cSJames Hogan for (decp = img_ir_decoders; *decp; ++decp) {
101230dd9e0cSJames Hogan const struct img_ir_decoder *dec = *decp;
101330dd9e0cSJames Hogan if (img_ir_decoder_compatible(priv, dec)) {
101430dd9e0cSJames Hogan img_ir_set_protocol(priv, dec->type);
101530dd9e0cSJames Hogan img_ir_set_decoder(priv, dec, 0);
101630dd9e0cSJames Hogan return;
101730dd9e0cSJames Hogan }
101830dd9e0cSJames Hogan }
101930dd9e0cSJames Hogan img_ir_set_decoder(priv, NULL, 0);
102030dd9e0cSJames Hogan }
102130dd9e0cSJames Hogan
102230dd9e0cSJames Hogan /**
102330dd9e0cSJames Hogan * img_ir_probe_hw_caps() - Probe capabilities of the hardware.
102430dd9e0cSJames Hogan * @priv: IR private data.
102530dd9e0cSJames Hogan */
img_ir_probe_hw_caps(struct img_ir_priv * priv)102630dd9e0cSJames Hogan static void img_ir_probe_hw_caps(struct img_ir_priv *priv)
102730dd9e0cSJames Hogan {
102830dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
102930dd9e0cSJames Hogan /*
103030dd9e0cSJames Hogan * When a version of the block becomes available without these quirks,
103130dd9e0cSJames Hogan * they'll have to depend on the core revision.
103230dd9e0cSJames Hogan */
103330dd9e0cSJames Hogan hw->ct_quirks[IMG_IR_CODETYPE_PULSELEN]
103430dd9e0cSJames Hogan |= IMG_IR_QUIRK_CODE_LEN_INCR;
103530dd9e0cSJames Hogan hw->ct_quirks[IMG_IR_CODETYPE_BIPHASE]
103602744c8cSSifan Naeem |= IMG_IR_QUIRK_CODE_IRQ;
103730dd9e0cSJames Hogan hw->ct_quirks[IMG_IR_CODETYPE_2BITPULSEPOS]
103830dd9e0cSJames Hogan |= IMG_IR_QUIRK_CODE_BROKEN;
103930dd9e0cSJames Hogan }
104030dd9e0cSJames Hogan
img_ir_probe_hw(struct img_ir_priv * priv)104130dd9e0cSJames Hogan int img_ir_probe_hw(struct img_ir_priv *priv)
104230dd9e0cSJames Hogan {
104330dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
104430dd9e0cSJames Hogan struct rc_dev *rdev;
104530dd9e0cSJames Hogan int error;
104630dd9e0cSJames Hogan
104730dd9e0cSJames Hogan /* Ensure hardware decoders have been preprocessed */
104830dd9e0cSJames Hogan img_ir_init_decoders();
104930dd9e0cSJames Hogan
105030dd9e0cSJames Hogan /* Probe hardware capabilities */
105130dd9e0cSJames Hogan img_ir_probe_hw_caps(priv);
105230dd9e0cSJames Hogan
105330dd9e0cSJames Hogan /* Set up the end timer */
1054b17ec78aSKees Cook timer_setup(&hw->end_timer, img_ir_end_timer, 0);
1055b17ec78aSKees Cook timer_setup(&hw->suspend_timer, img_ir_suspend_timer, 0);
105630dd9e0cSJames Hogan
105730dd9e0cSJames Hogan /* Register a clock notifier */
105830dd9e0cSJames Hogan if (!IS_ERR(priv->clk)) {
105930dd9e0cSJames Hogan hw->clk_hz = clk_get_rate(priv->clk);
106030dd9e0cSJames Hogan #ifdef CONFIG_COMMON_CLK
106130dd9e0cSJames Hogan hw->clk_nb.notifier_call = img_ir_clk_notify;
106230dd9e0cSJames Hogan error = clk_notifier_register(priv->clk, &hw->clk_nb);
106330dd9e0cSJames Hogan if (error)
106430dd9e0cSJames Hogan dev_warn(priv->dev,
106530dd9e0cSJames Hogan "failed to register clock notifier\n");
106630dd9e0cSJames Hogan #endif
106730dd9e0cSJames Hogan } else {
106830dd9e0cSJames Hogan hw->clk_hz = 32768;
106930dd9e0cSJames Hogan }
107030dd9e0cSJames Hogan
107130dd9e0cSJames Hogan /* Allocate hardware decoder */
10720f7499fdSAndi Shyti hw->rdev = rdev = rc_allocate_device(RC_DRIVER_SCANCODE);
107330dd9e0cSJames Hogan if (!rdev) {
107430dd9e0cSJames Hogan dev_err(priv->dev, "cannot allocate input device\n");
107530dd9e0cSJames Hogan error = -ENOMEM;
107630dd9e0cSJames Hogan goto err_alloc_rc;
107730dd9e0cSJames Hogan }
107830dd9e0cSJames Hogan rdev->priv = priv;
107930dd9e0cSJames Hogan rdev->map_name = RC_MAP_EMPTY;
1080c5540fbbSDavid Härdeman rdev->allowed_protocols = img_ir_allowed_protos(priv);
1081518f4b26SSean Young rdev->device_name = "IMG Infrared Decoder";
108223c843b5SDavid Härdeman rdev->s_filter = img_ir_set_normal_filter;
108323c843b5SDavid Härdeman rdev->s_wakeup_filter = img_ir_set_wakeup_filter;
108430dd9e0cSJames Hogan
108530dd9e0cSJames Hogan /* Register hardware decoder */
108630dd9e0cSJames Hogan error = rc_register_device(rdev);
108730dd9e0cSJames Hogan if (error) {
108830dd9e0cSJames Hogan dev_err(priv->dev, "failed to register IR input device\n");
108930dd9e0cSJames Hogan goto err_register_rc;
109030dd9e0cSJames Hogan }
109130dd9e0cSJames Hogan
109230dd9e0cSJames Hogan /*
109330dd9e0cSJames Hogan * Set this after rc_register_device as no protocols have been
109430dd9e0cSJames Hogan * registered yet.
109530dd9e0cSJames Hogan */
109630dd9e0cSJames Hogan rdev->change_protocol = img_ir_change_protocol;
109730dd9e0cSJames Hogan
109830dd9e0cSJames Hogan device_init_wakeup(priv->dev, 1);
109930dd9e0cSJames Hogan
110030dd9e0cSJames Hogan return 0;
110130dd9e0cSJames Hogan
110230dd9e0cSJames Hogan err_register_rc:
110330dd9e0cSJames Hogan img_ir_set_decoder(priv, NULL, 0);
110430dd9e0cSJames Hogan hw->rdev = NULL;
110530dd9e0cSJames Hogan rc_free_device(rdev);
110630dd9e0cSJames Hogan err_alloc_rc:
110730dd9e0cSJames Hogan #ifdef CONFIG_COMMON_CLK
110830dd9e0cSJames Hogan if (!IS_ERR(priv->clk))
110930dd9e0cSJames Hogan clk_notifier_unregister(priv->clk, &hw->clk_nb);
111030dd9e0cSJames Hogan #endif
111130dd9e0cSJames Hogan return error;
111230dd9e0cSJames Hogan }
111330dd9e0cSJames Hogan
img_ir_remove_hw(struct img_ir_priv * priv)111430dd9e0cSJames Hogan void img_ir_remove_hw(struct img_ir_priv *priv)
111530dd9e0cSJames Hogan {
111630dd9e0cSJames Hogan struct img_ir_priv_hw *hw = &priv->hw;
111730dd9e0cSJames Hogan struct rc_dev *rdev = hw->rdev;
111830dd9e0cSJames Hogan if (!rdev)
111930dd9e0cSJames Hogan return;
112030dd9e0cSJames Hogan img_ir_set_decoder(priv, NULL, 0);
112130dd9e0cSJames Hogan hw->rdev = NULL;
112230dd9e0cSJames Hogan rc_unregister_device(rdev);
112330dd9e0cSJames Hogan #ifdef CONFIG_COMMON_CLK
112430dd9e0cSJames Hogan if (!IS_ERR(priv->clk))
112530dd9e0cSJames Hogan clk_notifier_unregister(priv->clk, &hw->clk_nb);
112630dd9e0cSJames Hogan #endif
112730dd9e0cSJames Hogan }
112830dd9e0cSJames Hogan
112930dd9e0cSJames Hogan #ifdef CONFIG_PM_SLEEP
img_ir_suspend(struct device * dev)113030dd9e0cSJames Hogan int img_ir_suspend(struct device *dev)
113130dd9e0cSJames Hogan {
113230dd9e0cSJames Hogan struct img_ir_priv *priv = dev_get_drvdata(dev);
113330dd9e0cSJames Hogan
113430dd9e0cSJames Hogan if (device_may_wakeup(dev) && img_ir_enable_wake(priv))
113530dd9e0cSJames Hogan enable_irq_wake(priv->irq);
113630dd9e0cSJames Hogan return 0;
113730dd9e0cSJames Hogan }
113830dd9e0cSJames Hogan
img_ir_resume(struct device * dev)113930dd9e0cSJames Hogan int img_ir_resume(struct device *dev)
114030dd9e0cSJames Hogan {
114130dd9e0cSJames Hogan struct img_ir_priv *priv = dev_get_drvdata(dev);
114230dd9e0cSJames Hogan
114330dd9e0cSJames Hogan if (device_may_wakeup(dev) && img_ir_disable_wake(priv))
114430dd9e0cSJames Hogan disable_irq_wake(priv->irq);
114530dd9e0cSJames Hogan return 0;
114630dd9e0cSJames Hogan }
114730dd9e0cSJames Hogan #endif /* CONFIG_PM_SLEEP */
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