Lines Matching +full:max +full:- +full:clk +full:- +full:rate +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/nvmem-consumer.h>
18 #include "phy-mtk-io.h"
19 #include "phy-mtk-hdmi.h"
20 #include "phy-mtk-hdmi-mt8195.h"
25 mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN);
31 void __iomem *regs = hdmi_phy->regs;
35 /* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G,
47 void __iomem *regs = hdmi_phy->regs;
59 void __iomem *regs = hdmi_phy->regs;
92 void __iomem *regs = hdmi_phy->regs;
132 return -EINVAL;
153 return -EINVAL;
176 return -EINVAL;
205 mtk_phy_update_field(regs + HDMI_CTL_3, REG_HDMITXPLL_DIV, digital_div - 1);
212 unsigned long rate, unsigned long parent_rate)
220 pixel_clk = rate;
224 return -EINVAL;
227 hdmi_phy->tmds_over_340M = true;
229 hdmi_phy->tmds_over_340M = false;
231 /* in Hz */
235 * 0M < TMDS clk < 54M /8
236 * 54M <= TMDS clk < 148.35M /4
237 * 148.35M <=TMDS clk < 296.7M /2
238 * 296.7 <=TMDS clk <= 594M /1
249 return -EINVAL;
252 * ICO clk = 5*TMDS_CLK*TXPOSDIV*TXPREDIV
253 * ICO clk constraint: 5G =< ICO clk <= 12G
261 if (i == (ARRAY_SIZE(txpredivs) - 1) &&
263 return -EINVAL;
266 return -EINVAL;
279 return -EINVAL;
286 * 24bit -> posdiv1 /10, 30bit -> posdiv1 /12.5,
287 * 36bit -> posdiv1 /15, 48bit -> posdiv1 /10
292 /* Digital clk divider, max /32 */
295 return -EINVAL;
305 void __iomem *regs = hdmi_phy->regs;
309 u32 pixel_clk = hdmi_phy->pll_rate;
314 * 3G < data rate <= 6G: enable impedance 100ohm,
316 * pixel clk >= HD, 74.175MHZ <= pixel clk <= 300MHZ:
319 * 27M =< pixel clk < 74.175: disable impedance
323 /* 3G < data rate <= 6G, 300M < tmds rate <= 594M */
340 return -EINVAL;
362 void __iomem *regs = hdmi_phy->regs;
396 void __iomem *regs = hdmi_phy->regs;
410 static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
415 dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, rate,
418 return mtk_hdmi_pll_calc(hdmi_phy, hw, rate, parent_rate);
421 static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
426 hdmi_phy->pll_rate = rate;
427 return rate;
435 return hdmi_phy->pll_rate;
448 void __iomem *regs = hdmi_phy->regs;
469 struct phy_configure_opts_dp *dp_opts = &opts->dp;
473 ret = clk_set_rate(hdmi_phy->pll, dp_opts->link_rate);
478 mtk_phy_tmds_clk_ratio(hdmi_phy, hdmi_phy->tmds_over_340M);
487 mtk_phy_set_bits(hdmi_phy->regs + HDMI_CTL_1, RG_HDMITX_PWR5V_O);
496 mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CTL_1, RG_HDMITX_PWR5V_O);
505 return !!(readl(hdmi_phy->regs + HDMI_CTL_1) & RG_HDMITX_PWR5V_O);
515 .name = "hdmi-pwr5v",
516 .id = -1,