Lines Matching +full:max +full:- +full:clk +full:- +full:rate +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
17 #include <linux/clk.h>
18 #include "clk.h"
51 struct rockchip_clk_pll *pll, unsigned long rate)
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
56 for (i = 0; i < pll->rate_count; i++) {
57 if (rate == rate_table[i].rate)
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
72 for (i = 0; i < pll->rate_count; i++) {
73 if (drate >= rate_table[i].rate)
74 return rate_table[i].rate;
78 return rate_table[i - 1].rate;
88 struct regmap *grf = pll->ctx->grf;
92 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val,
93 val & BIT(pll->lock_shift), 0, 1000);
126 * Lock time typical 250, max 500 input clock cycles @24MHz
129 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
140 struct rockchip_pll_rate_table *rate)
144 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
145 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
147 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
150 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
151 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
153 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
155 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
158 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
159 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
190 const struct rockchip_pll_rate_table *rate)
192 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
193 struct clk_mux *pll_mux = &pll->pll_mux;
200 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
202 rate->postdiv2, rate->dsmpd, rate->frac);
205 cur.rate = 0;
207 if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {
208 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
210 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
216 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
218 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
220 pll->reg_base + RK3036_PLLCON(0));
222 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
224 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
226 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
228 pll->reg_base + RK3036_PLLCON(1));
231 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
233 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
234 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
245 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
254 const struct rockchip_pll_rate_table *rate;
256 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
257 __func__, __clk_get_name(hw->clk), drate, prate);
259 /* Get required rate settings from table */
260 rate = rockchip_get_pll_settings(pll, drate);
261 if (!rate) {
262 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
263 drate, __clk_get_name(hw->clk));
264 return -EINVAL;
267 return rockchip_rk3036_pll_set_params(pll, rate);
275 pll->reg_base + RK3036_PLLCON(1));
287 pll->reg_base + RK3036_PLLCON(1));
293 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
301 const struct rockchip_pll_rate_table *rate;
305 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
309 rate = rockchip_get_pll_settings(pll, drate);
311 /* when no rate setting for the current rate, rely on clk_set_rate */
312 if (!rate)
317 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
319 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
322 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
323 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
324 rate->dsmpd, rate->frac);
326 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
327 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
328 rate->dsmpd != cur.dsmpd ||
329 (!cur.dsmpd && (rate->frac != cur.frac))) {
330 struct clk *parent = clk_get_parent(hw->clk);
334 __func__, __clk_get_name(hw->clk));
338 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
339 __func__, __clk_get_name(hw->clk));
340 rockchip_rk3036_pll_set_params(pll, rate);
383 struct rockchip_pll_rate_table *rate)
387 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
388 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)
390 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)
393 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
394 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)
397 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
398 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)
410 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
427 const struct rockchip_pll_rate_table *rate)
429 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
430 struct clk_mux *pll_mux = &pll->pll_mux;
436 pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
437 __func__, rate->rate, rate->nr, rate->no, rate->nf);
440 cur.rate = 0;
442 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
444 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
450 pll->reg_base + RK3066_PLLCON(3));
453 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
455 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
457 pll->reg_base + RK3066_PLLCON(0));
459 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
461 pll->reg_base + RK3066_PLLCON(1));
462 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
464 pll->reg_base + RK3066_PLLCON(2));
468 pll->reg_base + RK3066_PLLCON(3));
469 udelay(RK3066_PLL_RESET_DELAY(rate->nr));
480 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
489 const struct rockchip_pll_rate_table *rate;
491 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
494 /* Get required rate settings from table */
495 rate = rockchip_get_pll_settings(pll, drate);
496 if (!rate) {
497 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
499 return -EINVAL;
502 return rockchip_rk3066_pll_set_params(pll, rate);
510 pll->reg_base + RK3066_PLLCON(3));
522 pll->reg_base + RK3066_PLLCON(3));
528 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
536 const struct rockchip_pll_rate_table *rate;
540 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
544 rate = rockchip_get_pll_settings(pll, drate);
546 /* when no rate setting for the current rate, rely on clk_set_rate */
547 if (!rate)
553 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,
554 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
555 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
556 || rate->nb != cur.nb) {
557 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
559 rockchip_rk3066_pll_set_params(pll, rate);
608 * Lock time typical 250, max 500 input clock cycles @24MHz
611 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
622 struct rockchip_pll_rate_table *rate)
626 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
627 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT)
630 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
631 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT)
633 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT)
635 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT)
638 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
639 rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT)
642 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
643 rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT)
674 const struct rockchip_pll_rate_table *rate)
676 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
677 struct clk_mux *pll_mux = &pll->pll_mux;
684 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
685 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
686 rate->postdiv2, rate->dsmpd, rate->frac);
689 cur.rate = 0;
691 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
693 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
698 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
700 pll->reg_base + RK3399_PLLCON(0));
702 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
704 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,
706 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
708 pll->reg_base + RK3399_PLLCON(1));
711 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
713 pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT;
714 writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
716 writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
718 pll->reg_base + RK3399_PLLCON(3));
729 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
738 const struct rockchip_pll_rate_table *rate;
740 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
741 __func__, __clk_get_name(hw->clk), drate, prate);
743 /* Get required rate settings from table */
744 rate = rockchip_get_pll_settings(pll, drate);
745 if (!rate) {
746 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
747 drate, __clk_get_name(hw->clk));
748 return -EINVAL;
751 return rockchip_rk3399_pll_set_params(pll, rate);
759 pll->reg_base + RK3399_PLLCON(3));
771 pll->reg_base + RK3399_PLLCON(3));
777 u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
785 const struct rockchip_pll_rate_table *rate;
789 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
793 rate = rockchip_get_pll_settings(pll, drate);
795 /* when no rate setting for the current rate, rely on clk_set_rate */
796 if (!rate)
801 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
803 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
806 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
807 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
808 rate->dsmpd, rate->frac);
810 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
811 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
812 rate->dsmpd != cur.dsmpd ||
813 (!cur.dsmpd && (rate->frac != cur.frac))) {
814 struct clk *parent = clk_get_parent(hw->clk);
818 __func__, __clk_get_name(hw->clk));
822 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
823 __func__, __clk_get_name(hw->clk));
824 rockchip_rk3399_pll_set_params(pll, rate);
869 * Lock time typical 250, max 500 input clock cycles @24MHz
872 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6),
883 struct rockchip_pll_rate_table *rate)
887 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0));
888 rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK);
890 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1));
891 rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK);
892 rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK);
894 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2));
895 rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK);
919 if (pll->type == pll_rk3588_ddr)
926 const struct rockchip_pll_rate_table *rate)
928 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
929 struct clk_mux *pll_mux = &pll->pll_mux;
935 pr_debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n",
936 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k);
939 cur.rate = 0;
941 if (pll->type == pll_rk3588) {
942 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
944 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
952 pll->reg_base + RK3399_PLLCON(1));
955 writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT),
956 pll->reg_base + RK3399_PLLCON(0));
958 writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) |
959 HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT),
960 pll->reg_base + RK3399_PLLCON(1));
962 writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT),
963 pll->reg_base + RK3399_PLLCON(2));
967 pll->reg_base + RK3588_PLLCON(1));
977 if ((pll->type == pll_rk3588) && rate_change_remuxed)
978 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
987 const struct rockchip_pll_rate_table *rate;
989 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
990 __func__, __clk_get_name(hw->clk), drate, prate);
992 /* Get required rate settings from table */
993 rate = rockchip_get_pll_settings(pll, drate);
994 if (!rate) {
995 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
996 drate, __clk_get_name(hw->clk));
997 return -EINVAL;
1000 return rockchip_rk3588_pll_set_params(pll, rate);
1008 pll->reg_base + RK3588_PLLCON(1));
1019 pll->reg_base + RK3588_PLLCON(1));
1025 u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1));
1050 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
1062 struct clk *pll_clk, *mux_clk;
1068 return ERR_PTR(-EINVAL);
1076 return ERR_PTR(-ENOMEM);
1079 pll->pll_mux_ops = &clk_mux_ops;
1080 pll_mux = &pll->pll_mux;
1081 pll_mux->reg = ctx->reg_base + mode_offset;
1082 pll_mux->shift = mode_shift;
1084 pll_mux->mask = PLL_RK3328_MODE_MASK;
1086 pll_mux->mask = PLL_MODE_MASK;
1087 pll_mux->flags = 0;
1088 pll_mux->lock = &ctx->lock;
1089 pll_mux->hw.init = &init;
1096 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
1098 /* the actual muxing is xin24m, pll-output, xin32k */
1105 init.ops = pll->pll_mux_ops;
1112 mux_clk = clk_register(NULL, &pll_mux->hw);
1129 for (len = 0; rate_table[len].rate != 0; )
1132 pll->rate_count = len;
1133 pll->rate_table = kmemdup_array(rate_table,
1134 pll->rate_count,
1135 sizeof(*pll->rate_table),
1137 WARN(!pll->rate_table,
1138 "%s: could not allocate rate table for %s\n",
1145 if (!pll->rate_table)
1151 if (!pll->rate_table || IS_ERR(ctx->grf))
1157 if (!pll->rate_table)
1165 if (!pll->rate_table)
1172 pr_warn("%s: Unknown pll type for pll clk %s\n",
1176 pll->hw.init = &init;
1177 pll->type = pll_type;
1178 pll->reg_base = ctx->reg_base + con_offset;
1179 pll->lock_offset = grf_lock_offset;
1180 pll->lock_shift = lock_shift;
1181 pll->flags = clk_pll_flags;
1182 pll->lock = &ctx->lock;
1183 pll->ctx = ctx;
1185 pll_clk = clk_register(NULL, &pll->hw);
1195 kfree(pll->rate_table);