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/linux/drivers/clk/sprd/
H A Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
28 #include "ccu-sun4i-a10.h"
34 .m = _SUNXI_CCU_DIV(0, 2),
38 .hw.init = CLK_HW_INIT("pll-core",
50 * With sigma-delta modulation for fractional-N on the audio PLL,
60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
67 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
73 .hw.init = CLK_HW_INIT("pll-audio-base",
[all …]
H A Dccu-sun5i.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun5i.h"
30 .m = _SUNXI_CCU_DIV(0, 2),
34 .hw.init = CLK_HW_INIT("pll-core",
46 * With sigma-delta modulation for fractional-N on the audio PLL,
56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
68 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
74 .hw.init = CLK_HW_INIT("pll-audio-base",
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H A Dccu-sun55i-a523-mcu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2025 Chen-Yu Tsai <wens@csie.org>
6 * Copyright (C) 2023-2024 Arm Ltd.
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/sun55i-a523-mcu-ccu.h>
15 #include <dt-bindings/reset/sun55i-a523-mcu-ccu.h>
30 static const struct clk_parent_data ahb[] = { variable
31 { .fw_name = "r-ahb" }
35 { .fw_name = "r-apb0" }
40 { .rate = 2167603200, .pattern = 0xa000a234, .m = 1, .n = 90 }, /* div2->22.5792 */
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H A Dccu-suniv-f1c100s.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include "ccu-suniv-f1c100s.h"
33 .m = _SUNXI_CCU_DIV(0, 2),
39 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
55 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
58 0, 5, /* M */
63 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
66 0, 4, /* M */
75 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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H A Dccu-sun50i-a100-r.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
18 #include "ccu-sun50i-a100-r.h"
21 "iosc", "pll-periph0" };
47 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
54 .hw.init = CLK_HW_INIT("r-apb1",
55 "r-ahb",
75 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
90 static SUNXI_CCU_GATE_DATA(r_apb1_timer_clk, "r-apb1-timer", clk_parent_r_apb1,
93 static SUNXI_CCU_GATE_DATA(r_apb1_twd_clk, "r-apb1-twd", clk_parent_r_apb1,
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H A Dccu-sun20i-d1-r.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include "ccu-sun20i-d1-r.h"
23 { .fw_name = "pll-periph" },
25 static SUNXI_CCU_MP_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
27 0, 5, /* M */
33 static SUNXI_CCU_MP_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
35 0, 5, /* M */
41 static SUNXI_CCU_GATE_HWS(bus_r_timer_clk, "bus-r-timer", &r_apb0_hw,
43 static SUNXI_CCU_GATE_HWS(bus_r_twd_clk, "bus-r-twd", &r_apb0_hw,
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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub
30 clock-names:
38 "#address-cells":
41 "#size-cells":
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/linux/Documentation/devicetree/bindings/arm/stm32/
H A Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 ML-AHB interconnect
10 - Fabien Dessenne <fabien.dessenne@foss.st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
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/linux/drivers/clk/sunxi/
H A Dclk-sun9i-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
9 #include <linux/clk-provider.h>
14 #include "clk-factors.h"
18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
20 * rate = (parent_rate * n >> p) / (m + 1);
23 * p and m are named div1 and div2 in Allwinner's SDK
29 int m = 1; in sun9i_a80_get_pll4_factors() local
33 n = DIV_ROUND_UP(req->rate, 6000000); in sun9i_a80_get_pll4_factors()
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H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
37 /* Normalize value to a 6M multiple */ in sun4i_get_pll1_factors()
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
41 /* m is always zero for pll1 */ in sun4i_get_pll1_factors()
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/linux/drivers/clk/
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx27.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
9 #include <dt-bindings/clock/imx27-clock.h>
40 "ahb", "ipg", "per1_div", "per2_div",
42 "nfc_div", "mshc_div", "vpu_div", "60m",
69 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); in _mx27_clocks_init()
70 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
72 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); in _mx27_clocks_init()
73 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in _mx27_clocks_init()
76 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); in _mx27_clocks_init()
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H A Dclk-imx6sx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <linux/clk-provider.h>
37 static const char *pcie_axi_sels[] = { "axi", "ahb", };
61 "lcdif1_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
131 clk_hw_data->num = IMX6SX_CLK_CLK_END; in imx6sx_clocks_init()
132 hws = clk_hw_data->hws; in imx6sx_clocks_init()
147 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
179 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
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/linux/drivers/clk/microchip/
H A Dclk-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/microchip,mpfs-clock.h>
120 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
121 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
159 msspll_hw->base = data->msspll_base; in mpfs_clk_register_mssplls()
160 ret = devm_clk_hw_register(dev, &msspll_hw->hw); in mpfs_clk_register_mssplls()
165 data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; in mpfs_clk_register_mssplls()
207 msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset; in mpfs_clk_register_msspll_outs()
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/linux/sound/soc/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 Say Y or M if you want to add support for I2S driver for
18 Say Y or M if you want to add support for the I2S/TDM driver for
20 interface between the AHB bus and the I2S bus, and support up to a
29 Say Y or M if you want to add support for PDM driver for
37 Say Y or M if you want to add support for the Rockchip Serial Audio
46 Say Y or M if you want to add support for SPDIF driver for
57 Say Y or M here if you want to add support for SoC audio on Rockchip
66 Say Y or M here if you want to add support for SoC audio on Rockchip
78 Say Y or M here if you want to add support for SoC audio on Rockchip
[all …]
/linux/drivers/pci/controller/
H A Dpci-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-rcar-gen2: internal PCI bus support
26 /* AHB-PCI Bridge PCI communication registers */
108 struct rcar_pci *priv = bus->sysdata; in rcar_pci_cfg_base()
114 /* Only one EHCI/OHCI device built-in */ in rcar_pci_cfg_base()
126 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); in rcar_pci_cfg_base()
127 return priv->reg + (slot >> 1) * 0x100 + where; in rcar_pci_cfg_base()
136 struct device *dev = priv->dev; in rcar_pci_err_irq()
137 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); in rcar_pci_err_irq()
144 priv->reg + RCAR_PCI_INT_STATUS_REG); in rcar_pci_err_irq()
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
[all …]
H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
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/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun55i-a523-ccu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun55i-a523-ccu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andre Przywara <andre.przywara@arm.com>
13 "#clock-cells":
16 "#reset-cells":
21 - allwinner,sun55i-a523-ccu
22 - allwinner,sun55i-a523-mcu-ccu
23 - allwinner,sun55i-a523-r-ccu
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/linux/arch/mips/ath25/
H A Dar5312.c9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
65 pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", in ar5312_ahb_err_handler()
68 machine_restart("AHB error"); /* Catastrophic failure */ in ar5312_ahb_err_handler()
96 ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq)); in ar5312_misc_irq_unmask()
102 ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0); in ar5312_misc_irq_mask()
107 .name = "ar5312-misc",
152 if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error", in ar5312_arch_init_irq()
154 pr_err("Failed to register ar5312-ahb-error interrupt\n"); in ar5312_arch_init_irq()
168 .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
173 .name = "physmap-flash",
[all …]
/linux/drivers/gpu/drm/imx/lcdc/
H A Dimx-lcdc.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: 2020 Marian Cichy <M.Cichy@pengutronix.de>
22 #include <linux/dma-mapping.h>
126 DRM_WARN("Format not supported - fallback to XRGB8888\n"); in imx_lcdc_get_format()
141 struct drm_crtc *crtc = &pipe->crtc; in imx_lcdc_update_hw_registers()
142 struct drm_plane_state *new_state = pipe->plane.state; in imx_lcdc_update_hw_registers()
143 struct drm_framebuffer *fb = new_state->fb; in imx_lcdc_update_hw_registers()
144 struct imx_lcdc *lcdc = imx_lcdc_from_drmdev(pipe->crtc.dev); in imx_lcdc_update_hw_registers()
151 writel(addr, lcdc->base + IMX21LCDC_LSSAR); in imx_lcdc_update_hw_registers()
157 if (old_state && old_state->crtc && old_state->crtc->enabled) in imx_lcdc_update_hw_registers()
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A DKconfig1 # SPDX-License-Identifier: ISC
20 If you choose to build a module, it'll be called ath5k. Say M if
32 mount -t debugfs debug /sys/kernel/debug
54 bool "Atheros 5xxx AHB bus support"
71 This enables non-standard IEEE 802.11 channels on ath5k, which
/linux/Documentation/devicetree/bindings/sound/
H A Drockchip,i2s-tdm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
18 - $ref: dai-common.yaml#
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
[all …]
H A Drockchip,rk3576-sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,rk3576-sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
17 - $ref: dai-common.yaml#
21 const: rockchip,rk3576-sai
33 dma-names:
36 - enum: [tx, rx]
37 - const: rx
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