135b97bb9SSamuel Holland // SPDX-License-Identifier: GPL-2.0
235b97bb9SSamuel Holland /*
335b97bb9SSamuel Holland * Copyright (c) 2020 huangzhenwei@allwinnertech.com
435b97bb9SSamuel Holland * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
535b97bb9SSamuel Holland */
635b97bb9SSamuel Holland
735b97bb9SSamuel Holland #include <linux/clk-provider.h>
835b97bb9SSamuel Holland #include <linux/module.h>
935b97bb9SSamuel Holland #include <linux/platform_device.h>
1035b97bb9SSamuel Holland
1135b97bb9SSamuel Holland #include "ccu_common.h"
1235b97bb9SSamuel Holland #include "ccu_reset.h"
1335b97bb9SSamuel Holland
1435b97bb9SSamuel Holland #include "ccu_gate.h"
1535b97bb9SSamuel Holland #include "ccu_mp.h"
1635b97bb9SSamuel Holland
1735b97bb9SSamuel Holland #include "ccu-sun20i-d1-r.h"
1835b97bb9SSamuel Holland
1935b97bb9SSamuel Holland static const struct clk_parent_data r_ahb_apb0_parents[] = {
2035b97bb9SSamuel Holland { .fw_name = "hosc" },
2135b97bb9SSamuel Holland { .fw_name = "losc" },
2235b97bb9SSamuel Holland { .fw_name = "iosc" },
2335b97bb9SSamuel Holland { .fw_name = "pll-periph" },
2435b97bb9SSamuel Holland };
2535b97bb9SSamuel Holland static SUNXI_CCU_MP_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
2635b97bb9SSamuel Holland r_ahb_apb0_parents, 0x000,
2735b97bb9SSamuel Holland 0, 5, /* M */
2835b97bb9SSamuel Holland 8, 2, /* P */
2935b97bb9SSamuel Holland 24, 3, /* mux */
3035b97bb9SSamuel Holland 0);
3135b97bb9SSamuel Holland static const struct clk_hw *r_ahb_hw = &r_ahb_clk.common.hw;
3235b97bb9SSamuel Holland
3335b97bb9SSamuel Holland static SUNXI_CCU_MP_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
3435b97bb9SSamuel Holland r_ahb_apb0_parents, 0x00c,
3535b97bb9SSamuel Holland 0, 5, /* M */
3635b97bb9SSamuel Holland 8, 2, /* P */
3735b97bb9SSamuel Holland 24, 3, /* mux */
3835b97bb9SSamuel Holland 0);
3935b97bb9SSamuel Holland static const struct clk_hw *r_apb0_hw = &r_apb0_clk.common.hw;
4035b97bb9SSamuel Holland
4135b97bb9SSamuel Holland static SUNXI_CCU_GATE_HWS(bus_r_timer_clk, "bus-r-timer", &r_apb0_hw,
4235b97bb9SSamuel Holland 0x11c, BIT(0), 0);
4335b97bb9SSamuel Holland static SUNXI_CCU_GATE_HWS(bus_r_twd_clk, "bus-r-twd", &r_apb0_hw,
4435b97bb9SSamuel Holland 0x12c, BIT(0), 0);
4535b97bb9SSamuel Holland static SUNXI_CCU_GATE_HWS(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_hw,
4635b97bb9SSamuel Holland 0x1ac, BIT(0), 0);
4735b97bb9SSamuel Holland
4835b97bb9SSamuel Holland static const struct clk_parent_data r_ir_rx_parents[] = {
4935b97bb9SSamuel Holland { .fw_name = "losc" },
5035b97bb9SSamuel Holland { .fw_name = "hosc" },
5135b97bb9SSamuel Holland };
5235b97bb9SSamuel Holland static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx",
5335b97bb9SSamuel Holland r_ir_rx_parents, 0x1c0,
5435b97bb9SSamuel Holland 0, 5, /* M */
5535b97bb9SSamuel Holland 8, 2, /* P */
5635b97bb9SSamuel Holland 24, 2, /* mux */
5735b97bb9SSamuel Holland BIT(31), /* gate */
5835b97bb9SSamuel Holland 0);
5935b97bb9SSamuel Holland
6035b97bb9SSamuel Holland static SUNXI_CCU_GATE_HWS(bus_r_ir_rx_clk, "bus-r-ir-rx", &r_apb0_hw,
6135b97bb9SSamuel Holland 0x1cc, BIT(0), 0);
6235b97bb9SSamuel Holland static SUNXI_CCU_GATE_HWS(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_hw,
6335b97bb9SSamuel Holland 0x20c, BIT(0), 0);
6435b97bb9SSamuel Holland static SUNXI_CCU_GATE_HWS(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_hw,
6535b97bb9SSamuel Holland 0x22c, BIT(0), 0);
6635b97bb9SSamuel Holland
6735b97bb9SSamuel Holland static struct ccu_common *sun20i_d1_r_ccu_clks[] = {
6835b97bb9SSamuel Holland &r_ahb_clk.common,
6935b97bb9SSamuel Holland &r_apb0_clk.common,
7035b97bb9SSamuel Holland &bus_r_timer_clk.common,
7135b97bb9SSamuel Holland &bus_r_twd_clk.common,
7235b97bb9SSamuel Holland &bus_r_ppu_clk.common,
7335b97bb9SSamuel Holland &r_ir_rx_clk.common,
7435b97bb9SSamuel Holland &bus_r_ir_rx_clk.common,
7535b97bb9SSamuel Holland &bus_r_rtc_clk.common,
7635b97bb9SSamuel Holland &bus_r_cpucfg_clk.common,
7735b97bb9SSamuel Holland };
7835b97bb9SSamuel Holland
7935b97bb9SSamuel Holland static struct clk_hw_onecell_data sun20i_d1_r_hw_clks = {
8035b97bb9SSamuel Holland .num = CLK_NUMBER,
8135b97bb9SSamuel Holland .hws = {
8235b97bb9SSamuel Holland [CLK_R_AHB] = &r_ahb_clk.common.hw,
8335b97bb9SSamuel Holland [CLK_R_APB0] = &r_apb0_clk.common.hw,
8435b97bb9SSamuel Holland [CLK_BUS_R_TIMER] = &bus_r_timer_clk.common.hw,
8535b97bb9SSamuel Holland [CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
8635b97bb9SSamuel Holland [CLK_BUS_R_PPU] = &bus_r_ppu_clk.common.hw,
8735b97bb9SSamuel Holland [CLK_R_IR_RX] = &r_ir_rx_clk.common.hw,
8835b97bb9SSamuel Holland [CLK_BUS_R_IR_RX] = &bus_r_ir_rx_clk.common.hw,
8935b97bb9SSamuel Holland [CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw,
9035b97bb9SSamuel Holland [CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw,
9135b97bb9SSamuel Holland },
9235b97bb9SSamuel Holland };
9335b97bb9SSamuel Holland
9435b97bb9SSamuel Holland static struct ccu_reset_map sun20i_d1_r_ccu_resets[] = {
9535b97bb9SSamuel Holland [RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
9635b97bb9SSamuel Holland [RST_BUS_R_TWD] = { 0x12c, BIT(16) },
9735b97bb9SSamuel Holland [RST_BUS_R_PPU] = { 0x1ac, BIT(16) },
9835b97bb9SSamuel Holland [RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
9935b97bb9SSamuel Holland [RST_BUS_R_RTC] = { 0x20c, BIT(16) },
10035b97bb9SSamuel Holland [RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
10135b97bb9SSamuel Holland };
10235b97bb9SSamuel Holland
10335b97bb9SSamuel Holland static const struct sunxi_ccu_desc sun20i_d1_r_ccu_desc = {
10435b97bb9SSamuel Holland .ccu_clks = sun20i_d1_r_ccu_clks,
10535b97bb9SSamuel Holland .num_ccu_clks = ARRAY_SIZE(sun20i_d1_r_ccu_clks),
10635b97bb9SSamuel Holland
10735b97bb9SSamuel Holland .hw_clks = &sun20i_d1_r_hw_clks,
10835b97bb9SSamuel Holland
10935b97bb9SSamuel Holland .resets = sun20i_d1_r_ccu_resets,
11035b97bb9SSamuel Holland .num_resets = ARRAY_SIZE(sun20i_d1_r_ccu_resets),
11135b97bb9SSamuel Holland };
11235b97bb9SSamuel Holland
sun20i_d1_r_ccu_probe(struct platform_device * pdev)11335b97bb9SSamuel Holland static int sun20i_d1_r_ccu_probe(struct platform_device *pdev)
11435b97bb9SSamuel Holland {
11535b97bb9SSamuel Holland void __iomem *reg;
11635b97bb9SSamuel Holland
11735b97bb9SSamuel Holland reg = devm_platform_ioremap_resource(pdev, 0);
11835b97bb9SSamuel Holland if (IS_ERR(reg))
11935b97bb9SSamuel Holland return PTR_ERR(reg);
12035b97bb9SSamuel Holland
12135b97bb9SSamuel Holland return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun20i_d1_r_ccu_desc);
12235b97bb9SSamuel Holland }
12335b97bb9SSamuel Holland
12435b97bb9SSamuel Holland static const struct of_device_id sun20i_d1_r_ccu_ids[] = {
12535b97bb9SSamuel Holland { .compatible = "allwinner,sun20i-d1-r-ccu" },
12635b97bb9SSamuel Holland { }
12735b97bb9SSamuel Holland };
128c60f6804SKrzysztof Kozlowski MODULE_DEVICE_TABLE(of, sun20i_d1_r_ccu_ids);
12935b97bb9SSamuel Holland
13035b97bb9SSamuel Holland static struct platform_driver sun20i_d1_r_ccu_driver = {
13135b97bb9SSamuel Holland .probe = sun20i_d1_r_ccu_probe,
13235b97bb9SSamuel Holland .driver = {
13335b97bb9SSamuel Holland .name = "sun20i-d1-r-ccu",
13435b97bb9SSamuel Holland .suppress_bind_attrs = true,
13535b97bb9SSamuel Holland .of_match_table = sun20i_d1_r_ccu_ids,
13635b97bb9SSamuel Holland },
13735b97bb9SSamuel Holland };
13835b97bb9SSamuel Holland module_platform_driver(sun20i_d1_r_ccu_driver);
13935b97bb9SSamuel Holland
14035b97bb9SSamuel Holland MODULE_IMPORT_NS(SUNXI_CCU);
141*4e7134faSJeff Johnson MODULE_DESCRIPTION("Support for the Allwinner D1/R528/T113 PRCM CCU");
14235b97bb9SSamuel Holland MODULE_LICENSE("GPL");
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