Home
last modified time | relevance | path

Searched +full:lvds +full:- +full:controller (Results 1 – 25 of 143) sorted by relevance

123456

/linux/drivers/gpu/drm/bridge/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 Simple transparent bridge that is used by several non-DRM drivers to
36 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
43 ICN6211 is MIPI-DSI/RGB Converter bridge from chipone.
67 ChromeOS EC ANX7688 is an ultra-low power
68 4K Ultra-HD (4096x2160p60) mobile HD transmitter
70 2.0 to DisplayPort 1.3 Ultra-HD. It is connected
71 to the ChromeOS Embedded Controller.
77 Driver for display connectors with support for DDC and hot-plug
81 on ARM-based platforms. Saying Y here when this driver is not needed
[all …]
H A Dmicrochip-lvds.c1 // SPDX-License-Identifier: GPL-2.0-only
69 static inline u32 lvds_readl(struct mchp_lvds *lvds, u32 offset) in lvds_readl() argument
71 return readl_relaxed(lvds->regs + offset); in lvds_readl()
74 static inline void lvds_writel(struct mchp_lvds *lvds, u32 offset, u32 val) in lvds_writel() argument
76 writel_relaxed(val, lvds->regs + offset); in lvds_writel()
79 static void lvds_serialiser_on(struct mchp_lvds *lvds) in lvds_serialiser_on() argument
84 lvds_writel(lvds, LVDSC_WPMR, (LVDSC_WPMR_WPKEY_PSSWD & in lvds_serialiser_on()
88 while (lvds_readl(lvds, LVDSC_SR) & LVDSC_SR_CS) { in lvds_serialiser_on()
90 dev_err(lvds->dev, "%s: timeout error\n", __func__); in lvds_serialiser_on()
97 lvds_writel(lvds, LVDSC_CFGR, (LVDSC_CFGR_MAPPING_JEIDA | in lvds_serialiser_on()
[all …]
H A Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
52 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
93 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
119 /* Mux Input Select for LVDS LINK Input */
162 #define LVCFG 0x049C /* LVDS Configuration */
163 #define LVPHY0 0x04A0 /* LVDS PHY 0 */
169 #define LVPHY1 0x04A4 /* LVDS PHY 1 */
[all …]
H A Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
24 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
67 /* LVDS registers */
110 #define LV_CFG 0x049C /* LVDS Configuration */
111 #define LV_PHY0 0x04A0 /* LVDS PHY 0 */
121 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
122 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
123 #define SYS_RST_LCD BIT(2) /* Reset LCD controller */
124 #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dmicrochip,sam9x75-lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/microchip,sam9x75-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip SAM9X75 LVDS Controller
10 - Dharma Balasubiramani <dharma.b@microchip.com>
13 The Low Voltage Differential Signaling Controller (LVDSC) manages data
14 format conversion from the LCD Controller internal DPI bus to OpenLDI
15 LVDS output signals. LVDSC functions include bit mapping, balanced mode
20 const: microchip,sam9x75-lvds
[all …]
H A Dlontium,lt9211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.
10 - Marek Vasut <marex@denx.de>
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
19 - lontium,lt9211
27 reset-gpios:
31 vccio-supply:
[all …]
H A Dfsl,imx8qxp-pxl2dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 interfaces the pixel link 36-bit data output and the DSI controller’s
15 MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
16 used in LVDS mode, to remap the pixel color codings between those modules.
20 The CSR module, as a system controller, contains the PXL2DPI's configuration
25 const: fsl,imx8qxp-pxl2dpi
[all …]
H A Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
16 The CSR module, as a system controller, contains the LDB's configuration
23 LDB split mode to support a dual link LVDS display. The channel indexes
41 - fsl,imx8qm-ldb
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-tcon.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Timings Controller (TCON)
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The TCON acts as a timing controller for RGB, LVDS and TV
18 "#clock-cells":
23 - const: allwinner,sun4i-a10-tcon
[all …]
H A Dst,stm32mp25-lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 LVDS Display Interface Transmitter
10 - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
15 LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
16 onto the LVDS PHY.
[all …]
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC display controller
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The Xylon LogiCVC is a display controller that supports multiple layers.
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
19 configuration of the controller takes place at logic configuration bitstream
[all …]
H A Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson Display Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic Meson Display controller is composed of several components
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
10 - Liu Ying <victor.liu@nxp.com>
13 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
15 groups of four data lanes of LVDS data streams. A phase-locked
17 data streams over a fifth LVDS link. Every cycle of the transmit
19 through the two groups of LVDS data streams. Together with the
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-lvds.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic LVDS panel driver
52 struct panel_lvds *lvds = to_panel_lvds(panel); in panel_lvds_unprepare() local
54 if (lvds->enable_gpio) in panel_lvds_unprepare()
55 gpiod_set_value_cansleep(lvds->enable_gpio, 0); in panel_lvds_unprepare()
57 if (lvds->supply) in panel_lvds_unprepare()
58 regulator_disable(lvds->supply); in panel_lvds_unprepare()
65 struct panel_lvds *lvds = to_panel_lvds(panel); in panel_lvds_prepare() local
67 if (lvds->supply) { in panel_lvds_prepare()
70 err = regulator_enable(lvds->supply); in panel_lvds_prepare()
[all …]
/linux/drivers/gpu/drm/stm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 Enable support for the on-chip display controller on
17 will be called stm-drm.
27 tristate "STMicroelectronics LVDS Display Interface Transmitter DRM driver"
30 Enable support for LVDS encoders on STMicroelectronics SoC.
31 The STM LVDS is a bridge which serialize pixel stream onto
32 a LVDS protocol.
35 called lvds.
/linux/drivers/gpu/drm/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
106 bool "Rockchip LVDS support"
112 Choose this option to enable support for Rockchip LVDS controllers.
113 Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
114 support LVDS, rgb, dual LVDS output mode. say Y to enable its
/linux/drivers/gpu/drm/radeon/
H A Dradeon_atombios.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
52 if ((rdev->family == CHIP_R420) || in radeon_lookup_i2c_gpio_quirks()
53 (rdev->family == CHIP_R423) || in radeon_lookup_i2c_gpio_quirks()
54 (rdev->family == CHIP_RV410)) { in radeon_lookup_i2c_gpio_quirks()
55 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || in radeon_lookup_i2c_gpio_quirks()
56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || in radeon_lookup_i2c_gpio_quirks()
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { in radeon_lookup_i2c_gpio_quirks()
58 gpio->ucClkMaskShift = 0x19; in radeon_lookup_i2c_gpio_quirks()
59 gpio->ucDataMaskShift = 0x18; in radeon_lookup_i2c_gpio_quirks()
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dfsl,imx8qxp-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
13 As a system controller, the Freescale i.MX8qm/qxp Control and Status
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
23 pattern: "^syscon@[0-9a-f]+$"
27 - enum:
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dti,lmk04832.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments LMK04832 Clock Controller
10 - Liam Beguin <liambeguin@gmail.com>
21 - ti,lmk04832
26 '#address-cells':
29 '#size-cells':
32 '#clock-cells':
35 spi-max-frequency:
[all …]
/linux/drivers/gpu/drm/tegra/
H A Drgb.c1 // SPDX-License-Identifier: GPL-2.0-only
96 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); in tegra_rgb_encoder_disable()
97 tegra_dc_commit(rgb->dc); in tegra_rgb_encoder_disable()
102 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; in tegra_rgb_encoder_enable()
107 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); in tegra_rgb_encoder_enable()
110 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
112 /* configure H- and V-sync signal polarities */ in tegra_rgb_encoder_enable()
113 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
115 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tegra_rgb_encoder_enable()
120 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tegra_rgb_encoder_enable()
[all …]
/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DPI and DP_INTF Controller
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
21 - enum:
22 - mediatek,mt2701-dpi
23 - mediatek,mt7623-dpi
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 from i.MX8 System Controller Unit (SCU) which is used to control power,
16 clock and reset through the i.MX8 Distributed Slave System Controller (DSC).
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
24 Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems,
25 like I2C controller, PWM controller, MIPI DSI controller and Control and
[all …]
/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Kontron SMARC-sAL28";
33 compatible = "gpio-keys";
35 power-button {
[all …]
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tqmls1021a-mbls1021a.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
5 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/linux-event-codes.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/leds/leds-pca9532.h>
15 #include <dt-bindings/net/ti-dp83867.h>
[all …]

123456