xref: /linux/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1*3e859cc7SLiu Ying# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*3e859cc7SLiu Ying%YAML 1.2
3*3e859cc7SLiu Ying---
4*3e859cc7SLiu Ying$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
5*3e859cc7SLiu Ying$schema: http://devicetree.org/meta-schemas/core.yaml#
6*3e859cc7SLiu Ying
7*3e859cc7SLiu Yingtitle: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
8*3e859cc7SLiu Ying
9*3e859cc7SLiu Yingmaintainers:
10*3e859cc7SLiu Ying  - Liu Ying <victor.liu@nxp.com>
11*3e859cc7SLiu Ying
12*3e859cc7SLiu Yingdescription: |
13*3e859cc7SLiu Ying  The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
14*3e859cc7SLiu Ying  interfaces the pixel link 36-bit data output and the DSI controllers
15*3e859cc7SLiu Ying  MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
16*3e859cc7SLiu Ying  used in LVDS mode, to remap the pixel color codings between those modules.
17*3e859cc7SLiu Ying  This module is purely combinatorial.
18*3e859cc7SLiu Ying
19*3e859cc7SLiu Ying  The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
20*3e859cc7SLiu Ying  The CSR module, as a system controller, contains the PXL2DPI's configuration
21*3e859cc7SLiu Ying  register.
22*3e859cc7SLiu Ying
23*3e859cc7SLiu Yingproperties:
24*3e859cc7SLiu Ying  compatible:
25*3e859cc7SLiu Ying    const: fsl,imx8qxp-pxl2dpi
26*3e859cc7SLiu Ying
27*3e859cc7SLiu Ying  fsl,sc-resource:
28*3e859cc7SLiu Ying    $ref: /schemas/types.yaml#/definitions/uint32
29*3e859cc7SLiu Ying    description: The SCU resource ID associated with this PXL2DPI instance.
30*3e859cc7SLiu Ying
31*3e859cc7SLiu Ying  power-domains:
32*3e859cc7SLiu Ying    maxItems: 1
33*3e859cc7SLiu Ying
34*3e859cc7SLiu Ying  fsl,companion-pxl2dpi:
35*3e859cc7SLiu Ying    $ref: /schemas/types.yaml#/definitions/phandle
36*3e859cc7SLiu Ying    description: |
37*3e859cc7SLiu Ying      A phandle which points to companion PXL2DPI which is used by downstream
38*3e859cc7SLiu Ying      LVDS Display Bridge(LDB) in split mode.
39*3e859cc7SLiu Ying
40*3e859cc7SLiu Ying  ports:
41*3e859cc7SLiu Ying    $ref: /schemas/graph.yaml#/properties/ports
42*3e859cc7SLiu Ying
43*3e859cc7SLiu Ying    properties:
44*3e859cc7SLiu Ying      port@0:
45*3e859cc7SLiu Ying        $ref: /schemas/graph.yaml#/properties/port
46*3e859cc7SLiu Ying        description: The PXL2DPI input port node from pixel link.
47*3e859cc7SLiu Ying
48*3e859cc7SLiu Ying      port@1:
49*3e859cc7SLiu Ying        $ref: /schemas/graph.yaml#/properties/port
50*3e859cc7SLiu Ying        description: The PXL2DPI output port node to downstream bridge.
51*3e859cc7SLiu Ying
52*3e859cc7SLiu Ying    required:
53*3e859cc7SLiu Ying      - port@0
54*3e859cc7SLiu Ying      - port@1
55*3e859cc7SLiu Ying
56*3e859cc7SLiu Yingrequired:
57*3e859cc7SLiu Ying  - compatible
58*3e859cc7SLiu Ying  - fsl,sc-resource
59*3e859cc7SLiu Ying  - power-domains
60*3e859cc7SLiu Ying  - ports
61*3e859cc7SLiu Ying
62*3e859cc7SLiu YingadditionalProperties: false
63*3e859cc7SLiu Ying
64*3e859cc7SLiu Yingexamples:
65*3e859cc7SLiu Ying  - |
66*3e859cc7SLiu Ying    #include <dt-bindings/firmware/imx/rsrc.h>
67*3e859cc7SLiu Ying    pxl2dpi {
68*3e859cc7SLiu Ying        compatible = "fsl,imx8qxp-pxl2dpi";
69*3e859cc7SLiu Ying        fsl,sc-resource = <IMX_SC_R_MIPI_0>;
70*3e859cc7SLiu Ying        power-domains = <&pd IMX_SC_R_MIPI_0>;
71*3e859cc7SLiu Ying
72*3e859cc7SLiu Ying        ports {
73*3e859cc7SLiu Ying            #address-cells = <1>;
74*3e859cc7SLiu Ying            #size-cells = <0>;
75*3e859cc7SLiu Ying
76*3e859cc7SLiu Ying            port@0 {
77*3e859cc7SLiu Ying                #address-cells = <1>;
78*3e859cc7SLiu Ying                #size-cells = <0>;
79*3e859cc7SLiu Ying                reg = <0>;
80*3e859cc7SLiu Ying
81*3e859cc7SLiu Ying                mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
82*3e859cc7SLiu Ying                    reg = <0>;
83*3e859cc7SLiu Ying                    remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
84*3e859cc7SLiu Ying                };
85*3e859cc7SLiu Ying
86*3e859cc7SLiu Ying                mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
87*3e859cc7SLiu Ying                     reg = <1>;
88*3e859cc7SLiu Ying                     remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
89*3e859cc7SLiu Ying                };
90*3e859cc7SLiu Ying            };
91*3e859cc7SLiu Ying
92*3e859cc7SLiu Ying            port@1 {
93*3e859cc7SLiu Ying                #address-cells = <1>;
94*3e859cc7SLiu Ying                #size-cells = <0>;
95*3e859cc7SLiu Ying                reg = <1>;
96*3e859cc7SLiu Ying
97*3e859cc7SLiu Ying                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
98*3e859cc7SLiu Ying                    reg = <0>;
99*3e859cc7SLiu Ying                    remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
100*3e859cc7SLiu Ying                };
101*3e859cc7SLiu Ying
102*3e859cc7SLiu Ying                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
103*3e859cc7SLiu Ying                    reg = <1>;
104*3e859cc7SLiu Ying                    remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
105*3e859cc7SLiu Ying                };
106*3e859cc7SLiu Ying            };
107*3e859cc7SLiu Ying        };
108*3e859cc7SLiu Ying    };
109