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/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx6q-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale LVDS Display Bridge (ldb)
10 The LVDS Display Bridge device tree node contains up to two lvds-channel
11 nodes describing each of the two LVDS encoder channels of the bridge.
14 - Frank Li <Frank.Li@nxp.com>
19 - enum:
20 - fsl,imx53-ldb
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
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H A Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
19 For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
23 LDB split mode to support a dual link LVDS display. The channel indexes
27 For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
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H A Dfsl,ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8MP DPI to LVDS bridge chip
10 - Marek Vasut <marex@denx.de>
14 for configuring the on-SoC DPI-to-LVDS serializer. This describes
20 - fsl,imx6sx-ldb
21 - fsl,imx8mp-ldb
22 - fsl,imx93-ldb
27 clock-names:
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H A Dtoshiba,tc358764.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358764 MIPI-DSI to LVDS bridge
10 - Andrzej Hajda <andrzej.hajda@intel.com>
17 description: Virtual channel number of a DSI peripheral
20 reset-gpios:
23 vddc-supply:
26 vddio-supply:
29 vddlvds-supply:
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/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-tcon.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The TCON acts as a timing controller for RGB, LVDS and TV
18 "#clock-cells":
23 - const: allwinner,sun4i-a10-tcon
24 - const: allwinner,sun5i-a13-tcon
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/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
10 - Liu Ying <victor.liu@nxp.com>
13 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
15 groups of four data lanes of LVDS data streams. A phase-locked
17 data streams over a fifth LVDS link. Every cycle of the transmit
19 through the two groups of LVDS data streams. Together with the
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_lvds.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
44 struct sun4i_lvds *lvds = in sun4i_lvds_get_modes() local
47 return drm_panel_get_modes(lvds->panel, connector); in sun4i_lvds_get_modes()
70 struct sun4i_lvds *lvds = drm_encoder_to_sun4i_lvds(encoder); in sun4i_lvds_encoder_enable() local
72 DRM_DEBUG_DRIVER("Enabling LVDS output\n"); in sun4i_lvds_encoder_enable()
74 if (lvds->panel) { in sun4i_lvds_encoder_enable()
75 drm_panel_prepare(lvds->panel); in sun4i_lvds_encoder_enable()
76 drm_panel_enable(lvds->panel); in sun4i_lvds_encoder_enable()
82 struct sun4i_lvds *lvds = drm_encoder_to_sun4i_lvds(encoder); in sun4i_lvds_encoder_disable() local
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H A Dsun4i_tcon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/media-bus-format.h>
48 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector()
50 if (connector->encoder == encoder) { in sun4i_tcon_get_connector()
66 return -EINVAL; in sun4i_tcon_get_pixel_depth()
68 info = &connector->display_info; in sun4i_tcon_get_pixel_depth()
69 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth()
70 return -EINVAL; in sun4i_tcon_get_pixel_depth()
72 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
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H A Dsun4i_tcon.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
27 #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe))
30 #define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe))
67 #define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16)
68 #define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff)
71 #define SUN4I_TCON0_BASIC1_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16)
72 #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff)
76 #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff)
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d-colibri-iris-v2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
7 #include "imx7d-colibri.dtsi"
8 #include "imx7-colibri-iris-v2.dtsi"
12 compatible = "toradex,colibri-imx7d-iris-v2",
13 "toradex,colibri-imx7d",
31 * This switches the LVDS transceiver to VESA color mapping mode.
33 lvds-color-map-hog {
34 gpio-hog;
36 line-name = "LVDS_COLOR_MAP";
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H A Dimx7s-colibri-iris-v2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
7 #include "imx7s-colibri.dtsi"
8 #include "imx7-colibri-iris-v2.dtsi"
12 compatible = "toradex,colibri-imx7s-iris-v2",
13 "toradex,colibri-imx7s",
31 * This switches the LVDS transceiver to VESA color mapping mode.
33 lvds-color-map-hog {
34 gpio-hog;
36 line-name = "LVDS_COLOR_MAP";
[all …]
H A Dimx6ull-colibri-wifi-iris-v2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2018-2022 Toradex
6 /dts-v1/;
8 #include "imx6ull-colibri-wifi.dtsi"
9 #include "imx6ull-colibri-iris-v2.dtsi"
13 compatible = "toradex,colibri-imx6ull-wifi-iris-v2",
14 "toradex,colibri-imx6ull-wifi",
31 /* This turns the LVDS transceiver on */
32 lvds-power-on-hog {
33 gpio-hog;
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H A Dimx6q-var-mx6customboard.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Support for Variscite MX6 Carrier-board
9 /dts-v1/;
11 #include "imx6qdl-var-som.dtsi"
12 #include <dt-bindings/pwm/pwm.h>
15 model = "Variscite i.MX6 QUAD/DUAL VAR-SOM-MX6 Custom Board";
16 compatible = "variscite,mx6customboard", "variscite,var-som-imx6q", "fsl,imx6q";
18 panel0: lvds-panel0 {
19 compatible = "panel-lvds";
21 width-mm = <152>;
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H A Dimx6ull-colibri-iris-v2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2018-2022 Toradex
6 /dts-v1/;
8 #include "imx6ull-colibri-nonwifi.dtsi"
9 #include "imx6ull-colibri-iris-v2.dtsi"
13 compatible = "toradex,colibri-imx6ull-iris-v2",
14 "toradex,colibri-imx6ull",
31 /* This turns the LVDS transceiver on */
32 lvds-power-on-hog {
33 gpio-hog;
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H A Dimx53-sk-imx53-atm0700d4-lvds.dts1 // SPDX-License-Identifier: GPL-2.0+
5 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
8 #include "imx53-sk-imx53-atm0700d4.dtsi"
11 lvds-decoder {
12 compatible = "ti,sn65lvds94", "lvds-decoder";
15 #address-cells = <1>;
16 #size-cells = <0>;
22 remote-endpoint = <&lvds0_out>;
30 remote-endpoint = <&panel_rgb_in>;
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H A Dimx53-tx53-x13x.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
3 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
6 /dts-v1/;
7 #include "imx53-tx53.dtsi"
8 #include <dt-bindings/input/input.h>
11 model = "Ka-Ro electronics TX53 module (LVDS)";
21 compatible = "pwm-backlight";
23 power-supply = <&reg_3v3>;
24 brightness-levels = <
37 default-brightness-level = <50>;
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H A Dimx6q-var-dt6customboard.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Support for Variscite DART-MX6 Carrier-board
9 /dts-v1/;
12 #include "imx6qdl-var-dart.dtsi"
13 #include <dt-bindings/input/linux-event-codes.h>
16 model = "Variscite DART-MX6 Carrier-board";
20 compatible = "pwm-backlight";
22 brightness-levels = <0 4 8 16 32 64 128 248>;
23 default-brightness-level = <7>;
27 gpio-keys {
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H A Dimx6q-icore-ofcap12.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
10 #include "imx6qdl-icore.dtsi"
14 compatible = "engicam,imx6-icore", "fsl,imx6q";
22 remote-endpoint = <&lvds0_out>;
31 lvds-channel@0 {
39 remote-endpoint = <&panel_in>;
/linux/drivers/video/fbdev/via/
H A Dlcd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
7 #include <linux/via-core.h>
75 viaparinfo->lvds_setting_info2->lcd_panel_hres = in viafb_init_lcd_size()
76 viaparinfo->lvds_setting_info->lcd_panel_hres; in viafb_init_lcd_size()
77 viaparinfo->lvds_setting_info2->lcd_panel_vres = in viafb_init_lcd_size()
78 viaparinfo->lvds_setting_info->lcd_panel_vres; in viafb_init_lcd_size()
79 viaparinfo->lvds_setting_info2->device_lcd_dualedge = in viafb_init_lcd_size()
80 viaparinfo->lvds_setting_info->device_lcd_dualedge; in viafb_init_lcd_size()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_lvds_regs.h1 /* SPDX-License-Identifier: MIT */
11 /* LVDS port control */
12 #define LVDS _MMIO(0x61180) macro
14 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
15 * the DPLL semantics change when the LVDS is assigned to that pipe.
18 /* Selects pipe B for LVDS data. Must be set on pre-965. */
23 /* LVDS dithering flag on 965/g4x platform */
25 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
29 /* Enable border for unscaled (or aspect-scaled) display */
32 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
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/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
48 /* The single-channel range is 25-112Mhz, and dual-channel
49 * is 80-224Mhz. Prefer single channel as much as possible.
70 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
71 clock->p = clock->p1 * clock->p2; in psb_intel_clock()
72 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
73 clock->dot = clock->vco / clock->p; in psb_intel_clock()
78 * or -1 if the panel fitter is not present or not in use
88 return -1; in psb_intel_panel_fitter_pipe()
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H A Dcdv_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
118 ret__ = -ETIMEDOUT; \
217 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
288 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
290 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
293 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
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/linux/Documentation/fb/
H A Dviafb.rst6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
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/linux/drivers/video/fbdev/sis/
H A Dinitdef.h6 * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
23 * * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
56 #define IS_SIS330 (SiS_Pr->ChipType == SIS_330)
57 #define IS_SIS550 (SiS_Pr->ChipType == SIS_550)
58 #define IS_SIS650 (SiS_Pr->ChipType == SIS_650) /* All versions, incl 651, M65x */
59 #define IS_SIS740 (SiS_Pr->ChipType == SIS_740)
60 #define IS_SIS651 (SiS_Pr->SiS_SysFlags & (SF_Is651 | SF_Is652))
61 #define IS_SISM650 (SiS_Pr->SiS_SysFlags & (SF_IsM650 | SF_IsM652 | SF_IsM653))
63 #define IS_SIS661 (SiS_Pr->ChipType == SIS_661)
64 #define IS_SIS741 (SiS_Pr->ChipType == SIS_741)
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