xref: /linux/arch/arm/boot/dts/nxp/imx/imx6q-var-mx6customboard.dts (revision 06d07429858317ded2db7986113a9e0129cd599b)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Support for Variscite MX6 Carrier-board
4 *
5 * Copyright 2016 Variscite, Ltd. All Rights Reserved
6 * Copyright 2022 Bootlin
7 */
8
9/dts-v1/;
10
11#include "imx6qdl-var-som.dtsi"
12#include <dt-bindings/pwm/pwm.h>
13
14/ {
15	model = "Variscite i.MX6 QUAD/DUAL VAR-SOM-MX6 Custom Board";
16	compatible = "variscite,mx6customboard", "variscite,var-som-imx6q", "fsl,imx6q";
17
18	panel0: lvds-panel0 {
19		compatible = "panel-lvds";
20		backlight = <&backlight_lvds>;
21		width-mm = <152>;
22		height-mm = <91>;
23		label = "etm070001adh6";
24		data-mapping = "jeida-18";
25
26		panel-timing {
27			clock-frequency = <32000000>;
28			hactive = <800>;
29			vactive = <480>;
30			hback-porch = <39>;
31			hfront-porch = <39>;
32			vback-porch = <29>;
33			vfront-porch = <13>;
34			hsync-len = <47>;
35			vsync-len = <2>;
36		};
37
38		port {
39			panel_in_lvds0: endpoint {
40				remote-endpoint = <&lvds0_out>;
41			};
42		};
43	};
44
45	panel1: lvds-panel1 {
46		compatible = "panel-lvds";
47		width-mm = <152>;
48		height-mm = <91>;
49		data-mapping = "jeida-18";
50
51		panel-timing {
52			clock-frequency = <38251000>;
53			hactive = <800>;
54			vactive = <600>;
55			hback-porch = <112>;
56			hfront-porch = <32>;
57			vback-porch = <3>;
58			vfront-porch = <17>;
59			hsync-len = <80>;
60			vsync-len = <4>;
61		};
62
63		port {
64			panel_in_lvds1: endpoint {
65				remote-endpoint = <&lvds1_out>;
66			};
67		};
68	};
69
70	backlight_lvds: backlight-lvds {
71		compatible = "pwm-backlight";
72		pwms = <&pwm2 0 50000 0>;
73		brightness-levels = <0 4 8 16 32 64 128 248>;
74		default-brightness-level = <7>;
75		power-supply = <&reg_3p3v>;
76	};
77};
78
79&i2c3 {
80	pinctrl-names = "default";
81	pinctrl-0 = <&pinctrl_i2c3>;
82	status = "okay";
83
84	touchscreen@24 {
85		compatible = "cypress,tt21000";
86		reg = <0x24>;
87		interrupt-parent = <&gpio3>;
88		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
89		reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
90		vdd-supply = <&reg_3p3v>;
91		touchscreen-size-x = <880>;
92		touchscreen-size-y = <1280>;
93	};
94
95	touchscreen@38 {
96		compatible = "edt,edt-ft5306";
97		reg = <0x38>;
98		interrupt-parent = <&gpio3>;
99		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
100		touchscreen-size-x = <1800>;
101		touchscreen-size-y = <1000>;
102	};
103};
104
105&iomuxc {
106	pinctrl_camera: cameragrp {
107		fsl,pins = <
108			MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12		0x1b0b0
109			MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13		0x1b0b0
110			MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14		0x1b0b0
111			MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15		0x1b0b0
112			MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16		0x1b0b0
113			MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17		0x1b0b0
114			MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18		0x1b0b0
115			MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19		0x1b0b0
116			MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN	0x1b0b0
117			MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK	0x1b0b0
118			MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC		0x1b0b0
119			MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC		0x1b0b0
120		>;
121	};
122
123	pinctrl_flexcan1: flexcan1grp {
124		fsl,pins = <
125			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX		0x1b0b0
126			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX		0x1b0b0
127		>;
128	};
129
130	pinctrl_ipu1: ipu1grp {
131		fsl,pins = <
132			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x10
133			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x10
134			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x10
135			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x10
136			MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04		0x10
137			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x10
138			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x10
139			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x10
140			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x10
141			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x10
142			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x10
143			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x10
144			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x10
145			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x10
146			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x10
147			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x10
148			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x10
149			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x10
150			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x10
151			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x10
152			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x10
153			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x10
154			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x10
155			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18	0x10
156			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19	0x10
157			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20	0x10
158			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x10
159			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x10
160			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x10
161		>;
162	};
163
164	pinctrl_uart3: uart3grp {
165		fsl,pins = <
166			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
167			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
168			MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
169			MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
170		>;
171	};
172
173	pinctrl_usbotg_var: usbotggrp {
174		fsl,pins = <
175			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x17059
176		>;
177	};
178
179	pinctrl_usdhc1: usdhc1grp {
180		fsl,pins = <
181			MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17071
182			MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10071
183			MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17071
184			MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17071
185			MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17071
186			MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17071
187		>;
188	};
189
190	pinctrl_usdhc2: usdhc2grp {
191		fsl,pins = <
192			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
193			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
194			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
195			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
196			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
197			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
198		>;
199	};
200};
201
202&ldb {
203	status = "okay";
204
205	lvds-channel@0 {
206		fsl,data-mapping = "spwg";
207		fsl,data-width = <24>;
208		status = "okay";
209
210		port@4 {
211			reg = <4>;
212
213			lvds0_out: endpoint {
214				remote-endpoint = <&panel_in_lvds0>;
215			};
216		};
217	};
218
219	lvds-channel@1 {
220		fsl,data-mapping = "spwg";
221		fsl,data-width = <24>;
222		status = "okay";
223
224		port@4 {
225			reg = <4>;
226
227			lvds1_out: endpoint {
228				remote-endpoint = <&panel_in_lvds1>;
229			};
230		};
231	};
232};
233
234&uart3 {
235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_uart3>;
237	uart-has-rtscts;
238	status = "okay";
239};
240
241&usdhc2 {
242	pinctrl-names = "default";
243	pinctrl-0 = <&pinctrl_usdhc2>;
244	cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
245	wp-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
246	status = "okay";
247};
248