xref: /linux/Documentation/devicetree/bindings/display/imx/fsl,imx6q-ldb.yaml (revision bf373e4c786bfe989e637195252698f45b157a68) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale LVDS Display Bridge (ldb)
8
9description:
10  The LVDS Display Bridge device tree node contains up to two lvds-channel
11  nodes describing each of the two LVDS encoder channels of the bridge.
12
13maintainers:
14  - Frank Li <Frank.Li@nxp.com>
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - fsl,imx53-ldb
21      - items:
22          - enum:
23              - fsl,imx6q-ldb
24          - const: fsl,imx53-ldb
25
26  reg:
27    maxItems: 1
28
29  '#address-cells':
30    const: 1
31
32  '#size-cells':
33    const: 0
34
35  gpr:
36    $ref: /schemas/types.yaml#/definitions/phandle
37    description:
38      The phandle points to the iomuxc-gpr region containing the LVDS
39      control register.
40
41  clocks:
42    minItems: 6
43    maxItems: 8
44
45  clock-names:
46    oneOf:
47      - items:
48          - const: di0_pll
49          - const: di1_pll
50          - const: di0_sel
51          - const: di1_sel
52          - const: di0
53          - const: di1
54      - items:
55          - const: di0_pll
56          - const: di1_pll
57          - const: di0_sel
58          - const: di1_sel
59          - const: di2_sel
60          - const: di3_sel
61          - const: di0
62          - const: di1
63
64  fsl,dual-channel:
65    $ref: /schemas/types.yaml#/definitions/flag
66    description:
67      if it exists, only LVDS channel 0 should
68      be configured - one input will be distributed on both outputs in dual
69      channel mode
70
71patternProperties:
72  '^lvds-channel@[0-1]$':
73    type: object
74    description:
75      Each LVDS Channel has to contain either an of graph link to a panel device node
76      or a display-timings node that describes the video timings for the connected
77      LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
78
79    properties:
80      reg:
81        maxItems: 1
82
83      '#address-cells':
84        const: 1
85
86      '#size-cells':
87        const: 0
88
89      display-timings:
90        $ref: /schemas/display/panel/display-timings.yaml#
91
92      fsl,data-mapping:
93        enum:
94          - spwg
95          - jeida
96
97      fsl,data-width:
98        $ref: /schemas/types.yaml#/definitions/uint32
99        description: should be <18> or <24>
100        enum:
101          - 18
102          - 24
103
104      fsl,panel:
105        $ref: /schemas/types.yaml#/definitions/phandle
106        description: phandle to lcd panel
107
108    patternProperties:
109      '^port@[0-4]$':
110        $ref: /schemas/graph.yaml#/properties/port
111        description:
112          On i.MX5, the internal two-input-multiplexer is used. Due to hardware
113          limitations, only one input port (port@[0,1]) can be used for each channel
114          (lvds-channel@[0,1], respectively).
115          On i.MX6, there should be four input ports (port@[0-3]) that correspond
116          to the four LVDS multiplexer inputs.
117          A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
118          to a panel input port. Optionally, the output port can be left out if
119          display-timings are used instead.
120
121    additionalProperties: false
122
123required:
124  - compatible
125  - gpr
126  - clocks
127  - clock-names
128
129additionalProperties: false
130
131examples:
132  - |
133    #include <dt-bindings/clock/imx5-clock.h>
134
135    ldb@53fa8008 {
136        compatible = "fsl,imx53-ldb";
137        reg = <0x53fa8008 0x4>;
138        #address-cells = <1>;
139        #size-cells = <0>;
140        gpr = <&gpr>;
141        clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
142                 <&clks IMX5_CLK_LDB_DI1_SEL>,
143                 <&clks IMX5_CLK_IPU_DI0_SEL>,
144                 <&clks IMX5_CLK_IPU_DI1_SEL>,
145                 <&clks IMX5_CLK_LDB_DI0_GATE>,
146                 <&clks IMX5_CLK_LDB_DI1_GATE>;
147        clock-names = "di0_pll", "di1_pll",
148                      "di0_sel", "di1_sel",
149                      "di0", "di1";
150
151        /* Using an of-graph endpoint link to connect the panel */
152        lvds-channel@0 {
153                reg = <0>;
154                #address-cells = <1>;
155                #size-cells = <0>;
156
157                port@0 {
158                    reg = <0>;
159
160                    endpoint {
161                        remote-endpoint = <&ipu_di0_lvds0>;
162                    };
163                };
164
165                port@2 {
166                    reg = <2>;
167
168                    endpoint {
169                        remote-endpoint = <&panel_in>;
170                    };
171               };
172        };
173
174        /* Using display-timings and fsl,data-mapping/width instead */
175        lvds-channel@1 {
176                reg = <1>;
177                #address-cells = <1>;
178                #size-cells = <0>;
179                fsl,data-mapping = "spwg";
180                fsl,data-width = <24>;
181
182                display-timings {/* ... */
183                };
184
185                port@1 {
186                     reg = <1>;
187
188                     endpoint {
189                         remote-endpoint = <&ipu_di1_lvds1>;
190                     };
191                };
192        };
193    };
194