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/linux/arch/mips/boot/dts/loongson/
H A Dloongson1.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
6 /dts-v1/;
8 #include <dt-bindings/clock/loongson,ls1x-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 compatible = "fixed-clock";
17 clock-output-names = "xtal";
18 #clock-cells = <0>;
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H A Dloongson1c.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
6 /dts-v1/;
10 clkc: clock-controller@1fe78030 {
11 compatible = "loongson,ls1c-clk";
14 #clock-cells = <1>;
20 compatible = "loongson,ls1c-syscon", "syscon";
24 intc4: interrupt-controller@10a0 {
25 compatible = "loongson,ls1x-intc";
27 interrupt-controller;
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,ls1x-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,ls1x-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1 Interrupt Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1 interrupt controller is connected to the MIPS core interrupt
18 const: loongson,ls1x-intc
23 interrupt-controller: true
25 '#interrupt-cells':
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/linux/drivers/irqchip/
H A Dirq-ls1x.c1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson-1 platform IRQ support
26 * struct ls1x_intc_priv - private ls1x-intc data.
28 * @intc_base: IO Base of intc registers.
44 pending = readl(priv->intc_base + LS_REG_INTC_STATUS) & in ls1x_chained_handle_irq()
45 readl(priv->intc_base + LS_REG_INTC_EN); in ls1x_chained_handle_irq()
53 generic_handle_domain_irq(priv->domain, bit); in ls1x_chained_handle_irq()
65 writel(readl(gc->reg_base + offset) | mask, in ls_intc_set_bit()
66 gc->reg_base + offset); in ls_intc_set_bit()
68 writel(readl(gc->reg_base + offset) & ~mask, in ls_intc_set_bit()
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