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/freebsd/share/examples/pf/
H A Dqueue36 altq on $ext_if priq bandwidth 10Mb queue { pri-low pri-med pri-high }
7 queue pri-low priority 0
8 queue pri-med priority 1 priq(default)
9 queue pri-high priority 2
12 queue(pri-med, pri-high)
13 pass out on $ext_if proto tcp from any to any port 80 queue pri-med
14 pass in on $ext_if proto tcp from any to any port 80 queue pri-low
/freebsd/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
24 compatible = "gpio-leds";
[all …]
H A Dsparx5_pcb134_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux-0 {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
23 i2c0_emux: i2c-mux-1 {
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/freebsd/share/doc/smm/18.net/
H A Dc.t53 occurs must kept small compared to the average inter-packet
97 amounts define the high and low water marks used by the socket routines
119 acting as a gateway from a high bandwidth network to a low bandwidth
/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A Dicx-metrics.json3 …Total pipeline cost of branch related instructions (used for program control-flow including functi…
4 … 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR…
9 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
10 …- INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) …
39 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
45 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
51 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
57 "BriefDescription": "The ratio of Executed- by Issued-Uops",
61 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
64 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dmediatek,mt76.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Felix Fietkau <nbd@nbd.name>
12 - Lorenzo Bianconi <lorenzo@kernel.org>
13 - Ryder Lee <ryder.lee@mediatek.com>
25 - mediatek,mt76
26 - mediatek,mt7628-wmac
27 - mediatek,mt7622-wmac
[all …]
/freebsd/share/man/man7/
H A Dtuning.731 .Sh SYSTEM SETUP - DISKLABEL, NEWFS, TUNEFS, SWAP
63 partitions are read-mostly, with very little writing, while
68 heavily write-loaded partitions will not bleed over into the mostly-read
81 .Dq Li "tunefs -n enable /filesystem" .
82 Softupdates drastically improves meta-data performance, mainly file
103 A number of run-time
117 file systems normally update the last-accessed time of a file or
138 atime turned on for mostly read-only partitions such as
161 or essentially read-only partitions such as
170 File systems tend to store meta-data on power-of-2 boundaries
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/freebsd/sys/dev/bhnd/
H A Dbhndreg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
10 * sbchipc.h distributed with the Asus RT-N16 firmware source code release.
46 * Common per-core clock control/status register available on PMU-equipped
50 * High Throughput (HT) Full bandwidth, low latency. Generally supplied
52 * Active Low Power (ALP) Register access, low speed DMA.
53 * Idle Low Power (ILP) No interconnect activity, or if long latency
70 #define BHND_CCS_ERSRC_MAX 2 /**< maximum ERSRC value (corresponding to bits 0-2) */
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_regs.h22 Boston, MA 02110-1301, USA.
32 /* N-PHY registers. */
41 #define BWN_NPHY_4WI_ADDR BWN_PHY_N(0x00B) /* Four-wire bus address */
42 #define BWN_NPHY_4WI_DATAHI BWN_PHY_N(0x00C) /* Four-wire bus data high */
43 #define BWN_NPHY_4WI_DATALO BWN_PHY_N(0x00D) /* Four-wire bus data low */
44 #define BWN_NPHY_BIST_STAT0 BWN_PHY_N(0x00E) /* Built-in self test status 0 */
45 #define BWN_NPHY_BIST_STAT1 BWN_PHY_N(0x00F) /* Built-in self test status 1 */
87 #define BWN_NPHY_C1_CLIP1_LOGAIN BWN_PHY_N(0x023) /* Core 1 clip1 low gain code */
92 #define BWN_NPHY_C1_LPF_QHPF_BW BWN_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */
145 #define BWN_NPHY_C2_CLIP1_LOGAIN BWN_PHY_N(0x039) /* Core 2 clip1 low gain code */
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/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dmicrochip,corepwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Conor Dooley <conor.dooley@microchip.com>
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
37 microchip,sync-update-mask:
48 Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
[all …]
/freebsd/lib/libpmc/
H A Dpmc.amd.31 .\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
54 .Bl -column "PMC_CAP_INTERRUPT" "Support"
71 .Bl -tag -width indent
77 Configure the counter to only count negated-to-asserted transitions
93 These additional qualifiers are event-specific and are documented
109 .Bl -tag -width indent
110 .It Li k8-b
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/freebsd/lib/libpmc/pmu-events/arch/x86/icelake/
H A Dicl-metrics.json3 …Total pipeline cost of branch related instructions (used for program control-flow including functi…
4 … 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR…
9 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
10 …- INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) …
27 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
33 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
39 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
45 "BriefDescription": "The ratio of Executed- by Issued-Uops",
49 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
52 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dadi,ad4000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4000-4004-4008.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4001-4005.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4002-4006-4010.pdf
18 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4003-4007-4011.pdf
19 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4020-4021-4022.pdf
20 https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4001.pdf
[all …]
/freebsd/share/man/man4/
H A Dice.42 .\" SPDX-License-Identifier: BSD-3-Clause
4 .\" Copyright (c) 2019-2020, Intel Corporation
73 .Bl -bullet -compact
91 .Sx Link-Level Flow Control
113 .Sx Optics and auto-negotiation
115 .Sx PCI-Express Slot Bandwidth
236 To use RDMA monitoring, more MSI-X interrupts may need to be reserved.
241 .Bd -literal -offset indent
245 The number of extra MSI-X interrupt vectors may need to be adjusted.
248 .Bd -literal -offset indent
[all …]
H A Dsume.41 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
36 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
49 driver provides support for NetFPGA SUME Virtex-7 FPGA Development Board
55 which yields low performance.
72 .An -nosplit
85 thus consuming PCI bandwidth, interrupts and CPU cycles in vain.
87 Pre-built FPGA bitstream from the NetFPGA project may not work correctly.
92 Occasionally, the driver can get stuck in a non-IDLE TX state due to
H A Dpcm.42 .\" Copyright (c) 2009-2011 Joel Dahl <joel@FreeBSD.org>
39 .Bd -ragged -offset indent
60 driver are: multichannel audio, per-application
62 duplex operation, bit perfect audio, rate conversion and low latency
74 .Bl -bullet -compact
118 .Xr snd_uaudio 4 (auto-loaded on device plug)
145 .Bl -tag -width ".Va snd_driver_load" -offset indent
177 re-routing of channels.
198 Commonly used for ear-candy or frequency compensation due to the vast
232 .Bl -tag -width indent
[all …]
H A Dsuperio.42 .\" SPDX-License-Identifier: BSD-2-Clause
37 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
48 Super I/O is an I/O controller that combines various low-bandwidth devices
52 .Bl -bullet -compact
66 a controller for general purpose input-output
74 Such devices either use well-known legacy resources or they are advertised
76 They can be configured either using ISA bus hints or they are auto-configured by
105 .Bl -bullet -compact
131 Nuvoton NCT6796D-E
[all …]
H A Dral.41 .\"-
2 .\" SPDX-License-Identifier: ISC
4 .\" Copyright (c) 2005-2010 Damien Bergamini <damien.bergamini@free.fr>
28 .Bd -ragged -offset indent
39 .Bd -literal -offset indent
62 This chipset uses the MIMO (multiple-input multiple-output) technology with
67 The RT2700 chipset is a low-cost version of the RT2800 chipset.
77 It can achieve speeds up to 144Mbps (20MHz bandwidth) and 300Mbps (40MHz
78 bandwidth.)
80 The RT3090 chipset is the first generation of single-chip 802.11n adapters
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-cc
[all...]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Daspeed-lpc.txt2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
11 The LPC controller is represented as a multi-function device to account for the
18 APB-to-LPC bridging amonst other functions.
21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
33 [1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c888374547021…
34 …el.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev…
40 - compatible: One of:
41 "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
42 "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
[all …]
H A Daspeed-lpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mfd/aspeed-lp
[all...]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_dcb_82599.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
41 * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
62 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc)); in ixgbe_dcb_get_tc_stats_82599()
63 /* Transmitted Bytes (read low first to prevent missed carry) */ in ixgbe_dcb_get_tc_stats_82599()
64 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc)); in ixgbe_dcb_get_tc_stats_82599()
65 stats->qbtc[tc] += in ixgbe_dcb_get_tc_stats_82599()
68 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc)); in ixgbe_dcb_get_tc_stats_82599()
69 /* Received Bytes (read low first to prevent missed carry) */ in ixgbe_dcb_get_tc_stats_82599()
70 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc)); in ixgbe_dcb_get_tc_stats_82599()
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_unit_adapter_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
49 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
87 #define AL_PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
93 #define AL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
106 #define AL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
122 #define AL_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
139 #define AL_PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
140 #define AL_PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
277 /* Central Target-ID enabler. If set, then each entry will be used as programmed */
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/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Dmac-cfg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2019, 2021-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
13 * enum iwl_mac_conf_subcmd_ids - mac configuration command IDs
104 * struct iwl_p2p_noa_attr - NOA attr contained in probe resp FW notification
107 * @len_low: length low half
127 * struct iwl_probe_resp_data_notif - notification with NOA and CSA counter
144 * struct iwl_missed_vap_notif - notification of missing vap detection
159 * struct iwl_channel_switch_start_notif_v1 - Channel switch start notification
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A Dskx-metrics.json7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
14 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
18 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4…
21 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
25 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY …
28 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
33 …"MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.A…
36 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
40 … - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.…
43 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
[all …]

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