Lines Matching +full:low +full:- +full:bandwidth

2 .\" SPDX-License-Identifier: BSD-3-Clause
4 .\" Copyright (c) 2019-2020, Intel Corporation
73 .Bl -bullet -compact
91 .Sx Link-Level Flow Control
113 .Sx Optics and auto-negotiation
115 .Sx PCI-Express Slot Bandwidth
236 To use RDMA monitoring, more MSI-X interrupts may need to be reserved.
241 .Bd -literal -offset indent
245 The number of extra MSI-X interrupt vectors may need to be adjusted.
248 .Bd -literal -offset indent
258 .Bd -literal -offset indent
274 Bandwidth can be allocated to each of these priorities, which is enforced at
282 .Bl -bullet -compact
284 Firmware-based LLDP Agent
286 Software-based LLDP Agent
289 In firmware-based mode, firmware intercepts all LLDP traffic and handles DCBX
299 In software-based mode, LLDP traffic is forwarded to the network stack and user
304 This mode requires the FW-based LLDP Agent to be disabled.
306 Firmware-based mode and software-based mode are controlled by the
312 Link-level flow control and priority flow control are mutually exclusive.
317 To enable/disable priority flow control in software-based DCBX mode:
318 .Bd -literal -offset indent
322 Enhanced Transmission Selection (ETS) allows bandwidth to be assigned to certain
325 .Bd -literal -offset indent
329 To set the minimum ETS bandwidth per TC, separate the values by commas.
331 For example, to set all TCs to a minimum bandwidth of 10% and TC 7 to 30%,
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341 .Bd -literal -offset indent
347 driver supports setting DSCP-based Layer 3 Quality of Service (L3 QoS)
352 .Bd -literal -offset indent
359 For example, to map DSCPs 0-3 and DSCP 8 to DCB TCs 0-3 and 4, respectively:
360 .Bd -literal -offset indent
361 sysctl dev.ice.<interface #>.dscp2tc_map.0-7=0,1,2,3,0,0,0,0
362 sysctl dev.ice.<interface #>.dscp2tc_map.8-15=4,0,0,0,0,0,0,0
369 .Bd -literal -offset indent
373 L3 QoS mode is not available when FW-LLDP is enabled.
375 FW-LLDP cannot be enabled if L3 QoS mode is active.
377 Disable FW-LLDP before switching to L3 QoS mode.
381 section in this README for more information on disabling FW-LLDP.
383 Use sysctl to change FW-LLDP settings.
384 The FW-LLDP setting is per port and persists across boots.
386 To enable the FW-LLDP Agent:
387 .Bd -literal -offset indent
391 To disable the FW-LLDP Agebt:
392 .Bd -literal -offset indent
397 .Bd -literal -offset indent
405 attribute is set to disabled, the FW-LLDP Agent cannot be enabled from the
407 .Ss Link-Level Flow Control
423 .Bd -literal -offset indent
428 .Bd -literal -offset indent
470 .Bd -literal -offset indent
478 .Bd -literal -offset indent
483 .Bd -literal -offset indent
488 .Bd -literal -offset indent
489 sysctl -d dev.ice.<interface #>.requested_fec
494 To have the device change the speeds it will use in auto-negotiation or
496 .Bd -literal -offset indent
503 .Bd -literal -offset indent
504 0x0 - Auto
505 0x2 - 100 Mbps
506 0x4 - 1 Gbps
507 0x8 - 2.5 Gbps
508 0x10 - 5 Gbps
509 0x20 - 10 Gbps
510 0x80 - 25 Gbps
511 0x100 - 40 Gbps
512 0x200 - 50 Gbps
513 0x400 - 100 Gbps
514 0x800 - 200 Gbps
525 .Bd -literal -offset indent
538 .Bl -enum -compact
565 .Bl -tag -offset indent -compact -width "task_dispatch"
593 XLR (function-level resets; Bit 13)
601 Intel On-Chip System Fabric (Bit 17)
640 .Bl -item -offset indent -compact
655 .Bd -literal -offset indent
660 .Bd -literal -offset indent
674 .Bd -literal -offset indent
682 .Bd -literal -offset indent
702 human-readable.
715 .Bd -literal -offset indent
724 .Bd -literal -offset indent
725 sysctl -d dev.ice.0.debug.dump.clusters
731 .Bl -bullet -compact
733 0 - Dump all clusters (only supported on Intel Ethernet E810 Series and
736 0x1 - Switch
738 0x2 - ACL
740 0x4 - Tx Scheduler
742 0x8 - Profile Configuration
744 0x20 - Link
746 0x80 - DCB
748 0x100 - L2P
750 0x400000 - Manageability Transactions (only supported on Intel Ethernet
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760 .Bd -literal -offset indent
769 .Bd -literal -offset indent
770 sysctl -b dev.ice.<interface #>.debug.dump.dump=1 > dump.bin
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793 .Bl -bullet
801 .Bd -literal -offset indent
805 NOTE: The contents of the registers are not human-readable.
817 .Bl -bullet
841 .Bd -literal -offset indent
846 may have a low number of network memory buffers (mbufs) by default.
847 If the number of mbufs available is too low, it may cause the driver to fail
849 Check to see if the system is mbuf-starved by running
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866 .Bd -literal -offset indent
879 .Bl -bullet
881 To change the behavior of the QSFP28 ports on E810-C adapters, use the Intel
882 .Sy Ethernet Port Configuration Tool - FreeBSD .
885 .Sy Non-Volatile Memory (NVM) Update Utility for Intel Ethernet Network Adapters E810 series - Free…
887 .Ss Optics and auto-negotiation
888 Modules based on 100GBASE-SR4,
890 do not support auto-negotiation per the IEEE specification.
892 auto-negotiation must be turned off on the link partner's switch ports.
896 that comply with SFF-8431 v4.1 and SFF-8472 v10.4 specifications.
897 .Ss PCI-Express Slot Bandwidth
899 These slots have insufficient bandwidth
902 if a PCIe v4.0 or v3.0-capable adapter is placed into into a PCIe v2.x
903 slot, full bandwidth will not be possible.
907 .Bd -ragged -offset indent
908 PCI-Express bandwidth available for this device
910 Please move the device to a different PCI-e link
917 .Bl -bullet
919 Any 100Gbps-capable Intel(R) Ethernet 800 Series device: Install in a
922 A 200Gbps-capable Intel(R) Ethernet 830 Series device: Install in a
934 .Bl -bullet -compact
936 Intel Ethernet Controller E810-C
938 Intel Ethernet Controller E810-XXV
940 Intel Ethernet Connection E822-C
942 Intel Ethernet Connection E822-L
944 Intel Ethernet Connection E823-C
946 Intel Ethernet Connection E823-L
948 Intel Ethernet Connection E825-C
950 Intel Ethernet Connection E830-C
952 Intel Ethernet Connection E830-CC
954 Intel Ethernet Connection E830-L
956 Intel Ethernet Connection E830-XXV
958 Intel Ethernet Connection E835-C
960 Intel Ethernet Connection E835-CC
962 Intel Ethernet Connection E835-L
964 Intel Ethernet Connection E835-XXV
978 .Bl -bullet -compact
980 Intel 100G QSFP28 100GBASE-SR4   E100GQSFPSR28SRX
982 Intel 100G QSFP28 100GBASE-SR4   SPTMBP1PMCDF
984 Intel 100G QSFP28 100GBASE-CWDM4 SPTSBP3CLCCO
986 Intel 100G QSFP28 100GBASE-DR    SPTSLP2SLCDF
993 .Bl -bullet -compact
995 Intel 10G/25G SFP28 25GBASE-SR E25GSFP28SR
997 Intel     25G SFP28 25GBASE-SR E25GSFP28SRX (Extended Temp)
999 Intel     25G SFP28 25GBASE-LR E25GSFP28LRX (Extended Temp)
1006 .Bl -bullet -compact
1008 Intel 1G/10G SFP+ 10GBASE-SR E10GSFPSR
1010 Intel 1G/10G SFP+ 10GBASE-SR E10GSFPSRG1P5
1012 Intel 1G/10G SFP+ 10GBASE-SR E10GSFPSRG2P5
1014 Intel    10G SFP+ 10GBASE-SR E10GSFPSRX (Extended Temp)
1016 Intel 1G/10G SFP+ 10GBASE-LR E10GSFPLR
1026 .Bl -tag -width indent
1040 Set the maximum number of per-device MSI-X vectors that are allocated for use
1060 Set to 1 to allow the driver to use the 5-layer Tx Scheduler tree topology if
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1069 This is expected to match the speed of the media type in-use displayed by
1095 .Bl -tag -width indent
1096 .It mac-addr Pq unicast-mac
1099 .Dq allow-set-mac
1101 .It mac-anti-spoof Pq bool
1105 .It allow-set-mac Pq bool
1108 .It allow-promisc Pq bool
1112 .It num-queues Pq uint16_t
1114 By default, this is set to the number of MSI-X vectors supported by the VF
1116 .It mirror-src-vsi Pq uint16_t
1118 other than -1.
1125 .Dq allow-promisc
1127 .It max-vlan-allowed Pq uint16_t
1133 .It max-mac-filters Pq uint16_t