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/linux/rust/kernel/debugfs/
H A Dtraits.rs1 // SPDX-License-Identifier: GPL-2.0
43 /// change](https://doc.rust-lang.org/std/fmt/trait.Debug.html#stability)
48 fn write(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result;
52 fn write(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { in write_to_slice()
53 self.lock().write(f) in write_to_slice()
58 fn write(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
67 /// `offset` is the requested offset int in write_to_slice()
54 write_to_slice( &self, writer: &mut UserSliceWriter, offset: &mut file::Offset, ) -> Result<usize> write_to_slice() argument
63 write_to_slice( &self, writer: &mut UserSliceWriter, offset: &mut file::Offset, ) -> Result<usize> write_to_slice() argument
74 write_to_slice( &self, writer: &mut UserSliceWriter, offset: &mut file::Offset, ) -> Result<usize> write_to_slice() argument
91 write_to_slice( &self, writer: &mut UserSliceWriter, offset: &mut file::Offset, ) -> Result<usize> write_to_slice() argument
106 write_to_slice( &self, writer: &mut UserSliceWriter, offset: &mut file::Offset, ) -> Result<usize> write_to_slice() argument
120 write_to_slice( &self, writer: &mut UserSliceWriter, offset: &mut file::Offset, ) -> Result<usize> write_to_slice() argument
135 write_to_slice( &self, writer: &mut UserSliceWriter, offset: &mut file::Offset, ) -> Result<usize> write_to_slice() argument
208 read_from_slice_mut( &mut self, reader: &mut UserSliceReader, offset: &mut file::Offset, ) -> Result<usize> read_from_slice_mut() argument
217 read_from_slice_mut( &mut self, reader: &mut UserSliceReader, offset: &mut file::Offset, ) -> Result<usize> read_from_slice_mut() argument
228 read_from_slice_mut( &mut self, reader: &mut UserSliceReader, offset: &mut file::Offset, ) -> Result<usize> read_from_slice_mut() argument
243 read_from_slice_mut( &mut self, reader: &mut UserSliceReader, offset: &mut file::Offset, ) -> Result<usize> read_from_slice_mut() argument
271 read_from_slice( &self, reader: &mut UserSliceReader, offset: &mut file::Offset, ) -> Result<usize> read_from_slice() argument
280 read_from_slice( &self, reader: &mut UserSliceReader, offset: &mut file::Offset, ) -> Result<usize> read_from_slice() argument
293 read_from_slice( &self, reader: &mut UserSliceReader, offset: &mut file::Offset, ) -> Result<usize> read_from_slice() argument
304 read_from_slice( &self, reader: &mut UserSliceReader, offset: &mut file::Offset, ) -> Result<usize> read_from_slice() argument
315 read_from_slice( &self, reader: &mut UserSliceReader, offset: &mut file::Offset, ) -> Result<usize> read_from_slice() argument
[all...]
/linux/drivers/gpio/
H A Dgpio-siox.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015-2018 Pengutronix, Uwe Kleine-König <kernel@pengutronix.de>
13 struct mutex lock; member
29 struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev); in gpio_siox_set_data()
31 mutex_lock(&ddata->lock); in gpio_siox_set_data()
32 buf[0] = ddata->setdata[0]; in gpio_siox_set_data()
33 mutex_unlock(&ddata->lock); in gpio_siox_set_data()
40 struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev); in gpio_siox_get_data()
41 size_t offset; in gpio_siox_get_data() local
44 mutex_lock(&ddata->lock); in gpio_siox_get_data()
[all …]
H A Dgpio-sch311x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * GPIO driver for the SMSC SCH311x Super-I/O chips
20 #define DRV_NAME "gpio-sch311x"
44 spinlock_t lock; /* lock for this GPIO block */ member
93 * Super-IO functions
102 return -EBUSY; in sch311x_sio_enter()
132 static int sch311x_gpio_request(struct gpio_chip *chip, unsigned offset) in sch311x_gpio_request() argument
136 if (block->config_regs[offset] == 0) /* GPIO is not available */ in sch311x_gpio_request()
137 return -ENODEV; in sch311x_gpio_request()
139 if (!request_region(block->runtime_reg + block->config_regs[offset], in sch311x_gpio_request()
[all …]
H A Dgpio-max730x.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * - DIN must be stable at the rising edge of clock.
12 * - when writing:
13 * - always clock in 16 clocks at once
14 * - at DIN: D15 first, D0 last
15 * - D0..D7 = databyte, D8..D14 = commandbyte
16 * - D15 = low -> write command
17 * - when reading
18 * - always clock in 16 clocks at once
19 * - at DIN: D15 first, D0 last
[all …]
H A Dgpio-sim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
53 struct mutex lock; member
59 unsigned int offset; member
69 unsigned int offset, int value) in gpio_sim_apply_pull() argument
73 guard(mutex)(&chip->lock); in gpio_sim_apply_pull()
75 if (test_bit(offset, chip->request_map) && in gpio_sim_apply_pull()
76 test_bit(offset, chip->direction_map)) { in gpio_sim_apply_pull()
77 if (value == !!test_bit(offset, chip->value_map)) in gpio_sim_apply_pull()
81 * This is fine - it just means, nobody is listening in gpio_sim_apply_pull()
86 irq = irq_find_mapping(chip->irq_sim, offset); in gpio_sim_apply_pull()
[all …]
H A Dgpio-timberdale.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #define DRIVER_NAME "timb-gpio"
35 spinlock_t lock; /* mutual exclusion */ member
42 unsigned offset, bool enabled) in timbgpio_update_bit() argument
48 spin_lock_irqsave(&tgpio->lock, flags); in timbgpio_update_bit()
49 reg = ioread32(tgpio->membase + offset); in timbgpio_update_bit()
56 iowrite32(reg, tgpio->membase + offset); in timbgpio_update_bit()
57 spin_unlock_irqrestore(&tgpio->lock, flags); in timbgpio_update_bit()
72 value = ioread32(tgpio->membase + TGPIOVAL); in timbgpio_gpio_get()
87 static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset) in timbgpio_to_irq() argument
[all …]
H A Dgpio-mb86s7x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/gpio/gpio-mb86s7x.c
22 #include "gpiolib-acpi.h"
32 #define OFFSET(x) BIT((x) % 8) macro
37 spinlock_t lock; member
46 spin_lock_irqsave(&gchip->lock, flags); in mb86s70_gpio_request()
48 val = readl(gchip->base + PFR(gpio)); in mb86s70_gpio_request()
49 val &= ~OFFSET(gpio); in mb86s70_gpio_request()
50 writel(val, gchip->base + PFR(gpio)); in mb86s70_gpio_request()
52 spin_unlock_irqrestore(&gchip->lock, flags); in mb86s70_gpio_request()
[all …]
H A Dgpio-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * gpio-reg: single register individually fixed-direction GPIOs
19 #include <linux/gpio/gpio-reg.h>
23 spinlock_t lock; member
33 static int gpio_reg_get_direction(struct gpio_chip *gc, unsigned offset) in gpio_reg_get_direction() argument
37 return r->direction & BIT(offset) ? GPIO_LINE_DIRECTION_IN : in gpio_reg_get_direction()
41 static int gpio_reg_direction_output(struct gpio_chip *gc, unsigned offset, in gpio_reg_direction_output() argument
46 if (r->direction & BIT(offset)) in gpio_reg_direction_output()
47 return -ENOTSUPP; in gpio_reg_direction_output()
49 gc->set(gc, offset, value); in gpio_reg_direction_output()
[all …]
H A Dgpio-lpc18xx.c1 // SPDX-License-Identifier: GPL-2.0
44 struct raw_spinlock lock; member
52 spinlock_t lock; member
58 u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL); in lpc18xx_gpio_pin_ic_isel()
65 writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL); in lpc18xx_gpio_pin_ic_isel()
71 writel_relaxed(BIT(pin), ic->base + reg); in lpc18xx_gpio_pin_ic_set()
76 struct lpc18xx_gpio_pin_ic *ic = d->chip_data; in lpc18xx_gpio_pin_ic_mask()
80 raw_spin_lock(&ic->lock); in lpc18xx_gpio_pin_ic_mask()
83 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
87 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
[all …]
H A Dgpio-aggregator.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2019-2020 Glider bv
7 #define DRV_NAME "gpio-aggregator"
45 struct mutex lock; member
69 int offset; member
88 return -ENOMEM; in gpio_aggregator_alloc()
96 new->id = ret; in gpio_aggregator_alloc()
97 INIT_LIST_HEAD(&new->list_head); in gpio_aggregator_alloc()
98 mutex_init(&new->lock); in gpio_aggregator_alloc()
106 idr_remove(&gpio_aggregator_idr, aggr->id); in gpio_aggregator_free()
[all …]
/linux/Documentation/netlink/specs/
H A Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
28 provides information of dpll device lock status, valid values for
31 -
[all …]
/linux/drivers/pinctrl/actions/
H A Dpinctrl-owl.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
25 #include <linux/pinctrl/pinconf-generic.h>
31 #include "../pinctrl-utils.h"
32 #include "pinctrl-owl.h"
35 * struct owl_pinctrl - pinctrl state of the device
39 * @lock: spinlock to protect registers
50 raw_spinlock_t lock; member
74 tmp = readl_relaxed(pctrl->base + reg); in owl_read_field()
75 mask = (1 << width) - 1; in owl_read_field()
[all …]
/linux/drivers/gpu/drm/lima/
H A Dlima_vm.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
[all …]
/linux/arch/sparc/lib/
H A Dbitext.c1 // SPDX-License-Identifier: GPL-2.0
19 * bit_map_string_get - find and set a bit string in bit map.
24 * Returns offset in the map or -1 if out of space.
30 int offset, count; /* siamese twins */ in bit_map_string_get() local
35 if (t->num_colors) { in bit_map_string_get()
38 align = t->num_colors; in bit_map_string_get()
44 align1 = align - 1; in bit_map_string_get()
47 if (align < 0 || align >= t->size) in bit_map_string_get()
49 if (len <= 0 || len > t->size) in bit_map_string_get()
53 spin_lock(&t->lock); in bit_map_string_get()
[all …]
/linux/drivers/pinctrl/spear/
H A Dpinctrl-plgpio.c56 * lock: lock for guarding gpio registers
59 * p2o: function ptr for pin to offset conversion. This is required only for
60 * machines where mapping b/w pin and offset is not 1-to-1.
61 * o2p: function ptr for offset to pin conversion. This is required only for
62 * machines where mapping b/w pin and offset is not 1-to-1.
68 spinlock_t lock; member
73 int (*o2p)(int offset); /* offset_to_pin */
84 u32 offset = PIN_OFFSET(pin); in is_plgpio_set() local
90 return !!(val & (1 << offset)); in is_plgpio_set()
95 u32 offset = PIN_OFFSET(pin); in plgpio_reg_set() local
[all …]
/linux/drivers/clk/hisilicon/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
11 #include <linux/reset-controller.h>
21 spinlock_t lock; member
33 u32 offset; in hisi_reset_of_xlate() local
36 offset = (reset_spec->args[0] << HISI_RESET_OFFSET_SHIFT) in hisi_reset_of_xlate()
38 bit = reset_spec->args[1] & HISI_RESET_BIT_MASK; in hisi_reset_of_xlate()
40 return (offset | bit); in hisi_reset_of_xlate()
48 u32 offset, reg; in hisi_reset_assert() local
51 offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT; in hisi_reset_assert()
[all …]
/linux/arch/loongarch/kvm/intc/
H A Dipi.c1 // SPDX-License-Identifier: GPL-2.0
14 spin_lock(&vcpu->arch.ipi_state.lock); in ipi_set()
15 status = vcpu->arch.ipi_state.status; in ipi_set()
16 vcpu->arch.ipi_state.status |= data; in ipi_set()
21 spin_unlock(&vcpu->arch.ipi_state.lock); in ipi_set()
43 spin_lock(&vcpu->arch.ipi_state.lock); in ipi_clear()
44 vcpu->arch.ipi_state.status &= ~data; in ipi_clear()
45 status = vcpu->arch.ipi_state.status; in ipi_clear()
50 spin_unlock(&vcpu->arch.ipi_state.lock); in ipi_clear()
53 static uint64_t read_mailbox(struct kvm_vcpu *vcpu, int offset, int len) in read_mailbox() argument
[all …]
H A Deiointc.c1 // SPDX-License-Identifier: GPL-2.0
16 ipnum = (s->ipmap >> (irq / 32 * 8)) & 0xff; in eiointc_set_sw_coreisr()
17 if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) { in eiointc_set_sw_coreisr()
23 cpuid = ((u8 *)s->coremap)[irq]; in eiointc_set_sw_coreisr()
24 vcpu = kvm_get_vcpu_by_cpuid(s->kvm, cpuid); in eiointc_set_sw_coreisr()
28 cpu = vcpu->vcpu_id; in eiointc_set_sw_coreisr()
29 if (test_bit(irq, (unsigned long *)s->coreisr[cpu])) in eiointc_set_sw_coreisr()
30 __set_bit(irq, s->sw_coreisr[cpu][ipnum]); in eiointc_set_sw_coreisr()
32 __clear_bit(irq, s->sw_coreisr[cpu][ipnum]); in eiointc_set_sw_coreisr()
41 ipnum = (s->ipmap >> (irq / 32 * 8)) & 0xff; in eiointc_update_irq()
[all …]
/linux/drivers/mfd/
H A Drz-mtu3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L Multi-Function Timer Pulse Unit 3(MTU3a) Core driver
13 #include <linux/mfd/rz-mtu3.h>
19 #include "rz-mtu3.h"
23 spinlock_t lock; member
26 /******* MTU3 registers (original offset is +0x1200) *******/
55 static bool rz_mtu3_is_16bit_shared_reg(u16 offset) in rz_mtu3_is_16bit_shared_reg() argument
57 return (offset == RZ_MTU3_TDDRA || offset == RZ_MTU3_TDDRB || in rz_mtu3_is_16bit_shared_reg()
58 offset == RZ_MTU3_TCDRA || offset == RZ_MTU3_TCDRB || in rz_mtu3_is_16bit_shared_reg()
59 offset == RZ_MTU3_TCBRA || offset == RZ_MTU3_TCBRB || in rz_mtu3_is_16bit_shared_reg()
[all …]
/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
103 * @lock: register lock
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
/linux/include/drm/
H A Ddrm_vma_manager.h34 * that the faked up offset will fit
84 * drm_vma_offset_exact_lookup_locked() - Look up node by exact address
86 * @start: Start address (page-based, not byte-based)
87 * @pages: Size of object (page-based)
89 * Same as drm_vma_offset_lookup_locked() but does not allow any offset into the node.
103 return (node && node->vm_node.start == start) ? node : NULL; in drm_vma_offset_exact_lookup_locked()
107 * drm_vma_offset_lock_lookup() - Lock lookup for extended private use
110 * Lock VMA manager for extended lookups. Only locked VMA function calls
111 * are allowed while holding this lock. All other contexts are blocked from VMA
112 * until the lock is released via drm_vma_offset_unlock_lookup().
[all …]
/linux/fs/btrfs/
H A Dfree-space-cache.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/error-injection.h>
15 #include "extent-tree.h"
19 #include "free-space-cache.h"
21 #include "disk-io.h"
23 #include "space-info.h"
24 #include "block-group.h"
27 #include "inode-item.h"
29 #include "file-item.h"
52 struct btrfs_free_space *bitmap_info, u64 *offset,
[all …]
/linux/drivers/clk/rockchip/
H A Dsoftrst.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/reset-controller.h>
20 spinlock_t lock; member
29 int bank, offset; in rockchip_softrst_assert() local
31 if (softrst->lut) in rockchip_softrst_assert()
32 id = softrst->lut[id]; in rockchip_softrst_assert()
34 bank = id / softrst->num_per_reg; in rockchip_softrst_assert()
35 offset = id % softrst->num_per_reg; in rockchip_softrst_assert()
37 if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) { in rockchip_softrst_assert()
38 writel(BIT(offset) | (BIT(offset) << 16), in rockchip_softrst_assert()
[all …]
/linux/drivers/iio/adc/
H A Dti-ads8688.c1 // SPDX-License-Identifier: GPL-2.0-only
41 * enum ads8688_range - ADS8688 reference voltage range
45 * @ADS8688_PLUS25VREF: Device is configured for input range 0 - 2.5 * VREF
46 * @ADS8688_PLUS125VREF: Device is configured for input range 0 - 1.25 * VREF
62 struct mutex lock; member
82 int offset; member
90 .offset = -(1 << (ADS8688_REALBITS - 1)),
95 .offset = -(1 << (ADS8688_REALBITS - 1)),
100 .offset = -(1 << (ADS8688_REALBITS - 1)),
105 .offset = 0,
[all …]
/linux/drivers/rtc/
H A Drtc-armada38x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Gregory Clement <gregory.clement@free-electrons.com>
72 spinlock_t lock; member
85 /* Initialize the RTC-MBUS bridge timing */
97 * According to errata RES-3124064, Write to any RTC register
103 static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset) in rtc_delayed_write() argument
105 writel(0, rtc->regs + RTC_STATUS); in rtc_delayed_write()
106 writel(0, rtc->regs + RTC_STATUS); in rtc_delayed_write()
107 writel(val, rtc->regs + offset); in rtc_delayed_write()
111 /* Update RTC-MBUS bridge timing parameters */
[all …]

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