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/linux/drivers/gpio/
H A Dgpio-cs5535.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
17 #define DRV_NAME "cs5535-gpio"
21 * 31-29,23 : reserved (always mask out)
24 * 22-16 : LPC
44 * design pattern, see Documentation/driver-api/driver-model/design-patterns.rst
51 spinlock_t lock; member
63 unsigned long addr = chip->base + 0x80 + reg; in errata_outl()
68 * non-selected bits; the recommended workaround is a in errata_outl()
69 * read-modify-write operation. in errata_outl()
[all …]
H A Dgpio-viperboard.c1 // SPDX-License-Identifier: GPL-2.0+
45 u8 offset; member
77 …"gpio-a sampling freq in Hz (default is 1000Hz) valid values: 10, 100, 1000, 10000, 100000, 100000…
79 /* ----- begin of gipo a chip -------------------------------------------- */
82 unsigned int offset) in vprbrd_gpioa_get() argument
86 struct vprbrd *vb = gpio->vb; in vprbrd_gpioa_get()
87 struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf; in vprbrd_gpioa_get()
90 if (gpio->gpioa_out & (1 << offset)) in vprbrd_gpioa_get()
91 return !!(gpio->gpioa_val & (1 << offset)); in vprbrd_gpioa_get()
93 mutex_lock(&vb->lock); in vprbrd_gpioa_get()
[all …]
H A Dgpio-siox.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015-2018 Pengutronix, Uwe Kleine-König <kernel@pengutronix.de>
13 struct mutex lock; member
29 struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev); in gpio_siox_set_data()
31 mutex_lock(&ddata->lock); in gpio_siox_set_data()
32 buf[0] = ddata->setdata[0]; in gpio_siox_set_data()
33 mutex_unlock(&ddata->lock); in gpio_siox_set_data()
40 struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev); in gpio_siox_get_data()
41 size_t offset; in gpio_siox_get_data() local
44 mutex_lock(&ddata->lock); in gpio_siox_get_data()
[all …]
H A Dgpio-sch311x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * GPIO driver for the SMSC SCH311x Super-I/O chips
20 #define DRV_NAME "gpio-sch311x"
44 spinlock_t lock; /* lock for this GPIO block */ member
93 * Super-IO functions
102 return -EBUSY; in sch311x_sio_enter()
132 static int sch311x_gpio_request(struct gpio_chip *chip, unsigned offset) in sch311x_gpio_request() argument
136 if (block->config_regs[offset] == 0) /* GPIO is not available */ in sch311x_gpio_request()
137 return -ENODEV; in sch311x_gpio_request()
139 if (!request_region(block->runtime_reg + block->config_regs[offset], in sch311x_gpio_request()
[all …]
H A Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
34 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
35 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
70 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
83 raw_spinlock_t lock; member
123 * Array Value: Indicates the offset for configuring the debounce timer.
129 * Array Value: offset for configuring debounce timer 0 (g4: 0x50, g7: 0x00)
131 * Array Value: offset for configuring debounce timer 1 (g4: 0x54, g7: 0x04)
133 * Array Value: offset for configuring debounce timer 2 (g4: 0x58, g7: 0x8)
[all …]
H A Dgpio-sim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
54 struct mutex lock; member
60 unsigned int offset; member
70 unsigned int offset, int value) in gpio_sim_apply_pull() argument
74 guard(mutex)(&chip->lock); in gpio_sim_apply_pull()
76 if (test_bit(offset, chip->request_map) && in gpio_sim_apply_pull()
77 test_bit(offset, chip->direction_map)) { in gpio_sim_apply_pull()
78 if (value == !!test_bit(offset, chip->value_map)) in gpio_sim_apply_pull()
82 * This is fine - it just means, nobody is listening in gpio_sim_apply_pull()
87 irq = irq_find_mapping(chip->irq_sim, offset); in gpio_sim_apply_pull()
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H A Dgpio-timberdale.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #define DRIVER_NAME "timb-gpio"
36 spinlock_t lock; /* mutual exclusion */ member
43 unsigned offset, bool enabled) in timbgpio_update_bit() argument
49 spin_lock_irqsave(&tgpio->lock, flags); in timbgpio_update_bit()
50 reg = ioread32(tgpio->membase + offset); in timbgpio_update_bit()
57 iowrite32(reg, tgpio->membase + offset); in timbgpio_update_bit()
58 spin_unlock_irqrestore(&tgpio->lock, flags); in timbgpio_update_bit()
73 value = ioread32(tgpio->membase + TGPIOVAL); in timbgpio_gpio_get()
89 static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset) in timbgpio_to_irq() argument
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H A Dgpio-mb86s7x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/gpio/gpio-mb86s7x.c
23 #include "gpiolib-acpi.h"
33 #define OFFSET(x) BIT((x) % 8) macro
38 spinlock_t lock; member
47 spin_lock_irqsave(&gchip->lock, flags); in mb86s70_gpio_request()
49 val = readl(gchip->base + PFR(gpio)); in mb86s70_gpio_request()
50 val &= ~OFFSET(gpio); in mb86s70_gpio_request()
51 writel(val, gchip->base + PFR(gpio)); in mb86s70_gpio_request()
53 spin_unlock_irqrestore(&gchip->lock, flags); in mb86s70_gpio_request()
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H A Dgpio-cgbc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 struct mutex lock; member
36 static int cgbc_gpio_get(struct gpio_chip *chip, unsigned int offset) in cgbc_gpio_get() argument
39 struct cgbc_device_data *cgbc = gpio->cgbc; in cgbc_gpio_get()
43 scoped_guard(mutex, &gpio->lock) in cgbc_gpio_get()
44 ret = cgbc_gpio_cmd(cgbc, CGBC_GPIO_CMD_GET, (offset > 7) ? 1 : 0, 0, &val); in cgbc_gpio_get()
46 offset %= 8; in cgbc_gpio_get()
51 return (int)(val & (u8)BIT(offset)); in cgbc_gpio_get()
55 unsigned int offset, int value) in __cgbc_gpio_set() argument
58 struct cgbc_device_data *cgbc = gpio->cgbc; in __cgbc_gpio_set()
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H A Dgpio-xgene.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AppliedMicro X-Gene SoC GPIO Driver
33 spinlock_t lock; member
37 static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset) in xgene_gpio_get() argument
43 bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset); in xgene_gpio_get()
44 bit_offset = GPIO_BIT_OFFSET(offset); in xgene_gpio_get()
45 return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); in xgene_gpio_get()
48 static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) in __xgene_gpio_set() argument
54 bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset); in __xgene_gpio_set()
55 bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK; in __xgene_gpio_set()
[all …]
H A Dgpio-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * gpio-reg: single register individually fixed-direction GPIOs
19 #include <linux/gpio/gpio-reg.h>
23 spinlock_t lock; member
33 static int gpio_reg_get_direction(struct gpio_chip *gc, unsigned offset) in gpio_reg_get_direction() argument
37 return r->direction & BIT(offset) ? GPIO_LINE_DIRECTION_IN : in gpio_reg_get_direction()
41 static int gpio_reg_direction_output(struct gpio_chip *gc, unsigned offset, in gpio_reg_direction_output() argument
46 if (r->direction & BIT(offset)) in gpio_reg_direction_output()
47 return -ENOTSUPP; in gpio_reg_direction_output()
49 gc->set(gc, offset, value); in gpio_reg_direction_output()
[all …]
H A Dgpio-amd8111.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012 Dmitry Eremin-Solenikov
72 spinlock_t lock; /* guards hw registers and orig table */ member
76 static int amd_gpio_request(struct gpio_chip *chip, unsigned offset) in amd_gpio_request() argument
80 agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) & in amd_gpio_request()
83 dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]); in amd_gpio_request()
88 static void amd_gpio_free(struct gpio_chip *chip, unsigned offset) in amd_gpio_free() argument
92 dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]); in amd_gpio_free()
94 iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset)); in amd_gpio_free()
97 static void amd_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in amd_gpio_set() argument
[all …]
/linux/drivers/pinctrl/actions/
H A Dpinctrl-owl.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
25 #include <linux/pinctrl/pinconf-generic.h>
31 #include "../pinctrl-utils.h"
32 #include "pinctrl-owl.h"
35 * struct owl_pinctrl - pinctrl state of the device
39 * @lock: spinlock to protect registers
50 raw_spinlock_t lock; member
74 tmp = readl_relaxed(pctrl->base + reg); in owl_read_field()
75 mask = (1 << width) - 1; in owl_read_field()
[all …]
/linux/Documentation/locking/
H A Drobust-futex-ABI.rst48 kernel, then it can actually have two such structures - one using 32 bit
56 pointer to a single linked list of 'lock entries', one per lock,
58 to itself, 'head'. The last 'lock entry' points back to the 'head'.
60 The second word, called 'offset', specifies the offset from the
61 address of the associated 'lock entry', plus or minus, of what will
62 be called the 'lock word', from that 'lock entry'. The 'lock word'
63 is always a 32 bit word, unlike the other words above. The 'lock
65 of the thread holding the lock in the bottom 30 bits. See further
69 the address of the 'lock entry', during list insertion and removal,
73 Each 'lock entry' on the single linked list starting at 'head' consists
[all …]
/linux/arch/sparc/lib/
H A Dbitext.c1 // SPDX-License-Identifier: GPL-2.0
19 * bit_map_string_get - find and set a bit string in bit map.
24 * Returns offset in the map or -1 if out of space.
30 int offset, count; /* siamese twins */ in bit_map_string_get() local
35 if (t->num_colors) { in bit_map_string_get()
38 align = t->num_colors; in bit_map_string_get()
44 align1 = align - 1; in bit_map_string_get()
47 if (align < 0 || align >= t->size) in bit_map_string_get()
49 if (len <= 0 || len > t->size) in bit_map_string_get()
53 spin_lock(&t->lock); in bit_map_string_get()
[all …]
/linux/arch/loongarch/kvm/intc/
H A Dipi.c1 // SPDX-License-Identifier: GPL-2.0
25 spin_lock(&vcpu->arch.ipi_state.lock); in ipi_send()
26 status = vcpu->arch.ipi_state.status; in ipi_send()
27 vcpu->arch.ipi_state.status |= action; in ipi_send()
28 spin_unlock(&vcpu->arch.ipi_state.lock); in ipi_send()
40 spin_lock(&vcpu->arch.ipi_state.lock); in ipi_clear()
41 vcpu->arch.ipi_state.status &= ~data; in ipi_clear()
42 status = vcpu->arch.ipi_state.status; in ipi_clear()
43 spin_unlock(&vcpu->arch.ipi_state.lock); in ipi_clear()
45 irq.irq = -LARCH_INT_IPI; in ipi_clear()
[all …]
/linux/drivers/gpu/drm/lima/
H A Dlima_vm.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
[all …]
/linux/drivers/pinctrl/spear/
H A Dpinctrl-plgpio.c56 * lock: lock for guarding gpio registers
59 * p2o: function ptr for pin to offset conversion. This is required only for
60 * machines where mapping b/w pin and offset is not 1-to-1.
61 * o2p: function ptr for offset to pin conversion. This is required only for
62 * machines where mapping b/w pin and offset is not 1-to-1.
68 spinlock_t lock; member
73 int (*o2p)(int offset); /* offset_to_pin */
84 u32 offset = PIN_OFFSET(pin); in is_plgpio_set() local
90 return !!(val & (1 << offset)); in is_plgpio_set()
95 u32 offset = PIN_OFFSET(pin); in plgpio_reg_set() local
[all …]
/linux/drivers/clk/hisilicon/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
11 #include <linux/reset-controller.h>
21 spinlock_t lock; member
33 u32 offset; in hisi_reset_of_xlate() local
36 offset = (reset_spec->args[0] << HISI_RESET_OFFSET_SHIFT) in hisi_reset_of_xlate()
38 bit = reset_spec->args[1] & HISI_RESET_BIT_MASK; in hisi_reset_of_xlate()
40 return (offset | bit); in hisi_reset_of_xlate()
48 u32 offset, reg; in hisi_reset_assert() local
51 offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT; in hisi_reset_assert()
[all …]
/linux/drivers/misc/mchp_pci1xxxx/
H A Dmchp_pci1xxxx_gpio.c1 // SPDX-License-Identifier: GPL-2.0
41 spinlock_t lock; member
49 int ret = -EINVAL; in pci1xxxx_gpio_get_direction()
51 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
55 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
81 spin_lock_irqsave(&priv->lock, flags); in pci1xxxx_gpio_direction_input()
82 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_input()
83 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_input()
84 spin_unlock_irqrestore(&priv->lock, flags); in pci1xxxx_gpio_direction_input()
93 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1; in pci1xxxx_gpio_get()
[all …]
/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
103 * @lock: register lock
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
/linux/fs/btrfs/
H A Dfree-space-cache.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/error-injection.h>
15 #include "extent-tree.h"
19 #include "free-space-cache.h"
21 #include "disk-io.h"
23 #include "space-info.h"
24 #include "block-group.h"
27 #include "inode-item.h"
29 #include "file-item.h"
51 struct btrfs_free_space *bitmap_info, u64 *offset,
[all …]
/linux/mm/
H A Dswapfile.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/blk-cgroup.h>
31 #include <linux/backing-dev.h>
63 unsigned long offset);
75 /* protected with swap_lock. reading in vm_swap_full() doesn't need lock */
77 static int least_priority = -1;
85 static const char Bad_offset[] = "Bad swap offset entry ";
86 static const char Unused_offset[] = "Unused swap offset entry ";
100 * This uses its own lock instead of swap_lock because when a
101 * swap_info_struct changes between not-full/full, it needs to
[all …]
/linux/include/drm/
H A Ddrm_vma_manager.h34 * that the faked up offset will fit
84 * drm_vma_offset_exact_lookup_locked() - Look up node by exact address
86 * @start: Start address (page-based, not byte-based)
87 * @pages: Size of object (page-based)
89 * Same as drm_vma_offset_lookup_locked() but does not allow any offset into the node.
103 return (node && node->vm_node.start == start) ? node : NULL; in drm_vma_offset_exact_lookup_locked()
107 * drm_vma_offset_lock_lookup() - Lock lookup for extended private use
110 * Lock VMA manager for extended lookups. Only locked VMA function calls
111 * are allowed while holding this lock. All other contexts are blocked from VMA
112 * until the lock is released via drm_vma_offset_unlock_lookup().
[all …]
/linux/drivers/iio/adc/
H A Dti-ads8688.c1 // SPDX-License-Identifier: GPL-2.0-only
44 * enum ads8688_range - ADS8688 reference voltage range
48 * @ADS8688_PLUS25VREF: Device is configured for input range 0 - 2.5 * VREF
49 * @ADS8688_PLUS125VREF: Device is configured for input range 0 - 1.25 * VREF
65 struct mutex lock; member
84 int offset; member
92 .offset = -(1 << (ADS8688_REALBITS - 1)),
97 .offset = -(1 << (ADS8688_REALBITS - 1)),
102 .offset = -(1 << (ADS8688_REALBITS - 1)),
107 .offset = 0,
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