Lines Matching +full:lock +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
20 #include "pinctrl-equilibrium.h"
22 #define PIN_NAME_FMT "io-%d"
30 unsigned int offset = irqd_to_hwirq(d); in eqbr_irq_mask() local
33 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_irq_mask()
34 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_irq_mask()
35 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_irq_mask()
36 gpiochip_disable_irq(gc, offset); in eqbr_irq_mask()
43 unsigned int offset = irqd_to_hwirq(d); in eqbr_irq_unmask() local
46 gc->direction_input(gc, offset); in eqbr_irq_unmask()
47 gpiochip_enable_irq(gc, offset); in eqbr_irq_unmask()
48 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_irq_unmask()
49 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_irq_unmask()
50 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_irq_unmask()
57 unsigned int offset = irqd_to_hwirq(d); in eqbr_irq_ack() local
60 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_irq_ack()
61 writel(BIT(offset), gctrl->membase + GPIO_IRNCR); in eqbr_irq_ack()
62 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_irq_ack()
69 unsigned int offset = irqd_to_hwirq(d); in eqbr_irq_mask_ack() local
72 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_irq_mask_ack()
73 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_irq_mask_ack()
74 writel(BIT(offset), gctrl->membase + GPIO_IRNCR); in eqbr_irq_mask_ack()
75 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_irq_mask_ack()
79 unsigned int offset, unsigned int set) in eqbr_cfg_bit() argument
82 writel(readl(addr) | BIT(offset), addr); in eqbr_cfg_bit()
84 writel(readl(addr) & ~BIT(offset), addr); in eqbr_cfg_bit()
89 unsigned int offset) in eqbr_irq_type_cfg() argument
93 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_irq_type_cfg()
94 eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type); in eqbr_irq_type_cfg()
95 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type); in eqbr_irq_type_cfg()
96 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type); in eqbr_irq_type_cfg()
97 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_irq_type_cfg()
106 unsigned int offset = irqd_to_hwirq(d); in eqbr_irq_set_type() local
146 return -EINVAL; in eqbr_irq_set_type()
149 eqbr_irq_type_cfg(&it, gctrl, offset); in eqbr_irq_set_type()
163 unsigned long pins, offset; in eqbr_irq_handler() local
166 pins = readl(gctrl->membase + GPIO_IRNCR); in eqbr_irq_handler()
168 for_each_set_bit(offset, &pins, gc->ngpio) in eqbr_irq_handler()
169 generic_handle_domain_irq(gc->irq.domain, offset); in eqbr_irq_handler()
190 gc = &gctrl->chip.gc; in gpiochip_setup()
191 gc->label = gctrl->name; in gpiochip_setup()
192 gc->fwnode = gctrl->fwnode; in gpiochip_setup()
193 gc->request = gpiochip_generic_request; in gpiochip_setup()
194 gc->free = gpiochip_generic_free; in gpiochip_setup()
196 if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) { in gpiochip_setup()
198 gctrl->name); in gpiochip_setup()
202 girq = &gctrl->chip.gc.irq; in gpiochip_setup()
204 girq->parent_handler = eqbr_irq_handler; in gpiochip_setup()
205 girq->num_parents = 1; in gpiochip_setup()
206 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL); in gpiochip_setup()
207 if (!girq->parents) in gpiochip_setup()
208 return -ENOMEM; in gpiochip_setup()
210 girq->default_type = IRQ_TYPE_NONE; in gpiochip_setup()
211 girq->handler = handle_bad_irq; in gpiochip_setup()
212 girq->parents[0] = gctrl->virq; in gpiochip_setup()
220 struct device *dev = drvdata->dev; in gpiolib_reg()
226 for (i = 0; i < drvdata->nr_gpio_ctrls; i++) { in gpiolib_reg()
227 gctrl = drvdata->gpio_ctrls + i; in gpiolib_reg()
228 np = to_of_node(gctrl->fwnode); in gpiolib_reg()
230 gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i); in gpiolib_reg()
231 if (!gctrl->name) in gpiolib_reg()
232 return -ENOMEM; in gpiolib_reg()
236 return -ENXIO; in gpiolib_reg()
239 gctrl->membase = devm_ioremap_resource(dev, &res); in gpiolib_reg()
240 if (IS_ERR(gctrl->membase)) in gpiolib_reg()
241 return PTR_ERR(gctrl->membase); in gpiolib_reg()
243 gctrl->virq = irq_of_parse_and_map(np, 0); in gpiolib_reg()
244 if (!gctrl->virq) { in gpiolib_reg()
246 gctrl->name); in gpiolib_reg()
247 return -ENXIO; in gpiolib_reg()
249 raw_spin_lock_init(&gctrl->lock); in gpiolib_reg()
253 .sz = gctrl->bank->nr_pins / 8, in gpiolib_reg()
254 .dat = gctrl->membase + GPIO_IN, in gpiolib_reg()
255 .set = gctrl->membase + GPIO_OUTSET, in gpiolib_reg()
256 .clr = gctrl->membase + GPIO_OUTCLR, in gpiolib_reg()
257 .dirout = gctrl->membase + GPIO_DIR, in gpiolib_reg()
260 ret = gpio_generic_chip_init(&gctrl->chip, &config); in gpiolib_reg()
270 ret = devm_gpiochip_add_data(dev, &gctrl->chip.gc, gctrl); in gpiolib_reg()
284 for (i = 0; i < pctl->nr_banks; i++) { in find_pinbank_via_pin()
285 bank = &pctl->pin_banks[i]; in find_pinbank_via_pin()
286 if (pin >= bank->pin_base && in find_pinbank_via_pin()
287 (pin - bank->pin_base) < bank->nr_pins) in find_pinbank_via_pin()
307 unsigned int offset; in eqbr_set_pin_mux() local
312 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin); in eqbr_set_pin_mux()
313 return -ENODEV; in eqbr_set_pin_mux()
315 mem = bank->membase; in eqbr_set_pin_mux()
316 offset = pin - bank->pin_base; in eqbr_set_pin_mux()
318 if (!(bank->aval_pinmap & BIT(offset))) { in eqbr_set_pin_mux()
319 dev_err(pctl->dev, in eqbr_set_pin_mux()
321 pin, bank->pin_base, bank->aval_pinmap); in eqbr_set_pin_mux()
322 return -ENODEV; in eqbr_set_pin_mux()
325 raw_spin_lock_irqsave(&pctl->lock, flags); in eqbr_set_pin_mux()
326 writel(pmx, mem + (offset * 4)); in eqbr_set_pin_mux()
327 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_set_pin_mux()
342 return -EINVAL; in eqbr_pinmux_set_mux()
346 return -EINVAL; in eqbr_pinmux_set_mux()
348 pinmux = grp->data; in eqbr_pinmux_set_mux()
349 for (i = 0; i < grp->grp.npins; i++) in eqbr_pinmux_set_mux()
350 eqbr_set_pin_mux(pctl, pinmux[i], grp->grp.pins[i]); in eqbr_pinmux_set_mux()
373 static int get_drv_cur(void __iomem *mem, unsigned int offset) in get_drv_cur() argument
375 unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/ in get_drv_cur()
376 unsigned int pin_offset = offset % DRV_CUR_PINS; in get_drv_cur()
387 for (i = 0; i < pctl->nr_gpio_ctrls; i++) { in get_gpio_ctrls_via_bank()
388 if (pctl->gpio_ctrls[i].bank == bank) in get_gpio_ctrls_via_bank()
389 return &pctl->gpio_ctrls[i]; in get_gpio_ctrls_via_bank()
403 unsigned int offset; in eqbr_pinconf_get() local
409 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin); in eqbr_pinconf_get()
410 return -ENODEV; in eqbr_pinconf_get()
412 mem = bank->membase; in eqbr_pinconf_get()
413 offset = pin - bank->pin_base; in eqbr_pinconf_get()
415 if (!(bank->aval_pinmap & BIT(offset))) { in eqbr_pinconf_get()
416 dev_err(pctl->dev, in eqbr_pinconf_get()
418 pin, bank->pin_base, bank->aval_pinmap); in eqbr_pinconf_get()
419 return -ENODEV; in eqbr_pinconf_get()
422 raw_spin_lock_irqsave(&pctl->lock, flags); in eqbr_pinconf_get()
425 val = !!(readl(mem + REG_PUEN) & BIT(offset)); in eqbr_pinconf_get()
428 val = !!(readl(mem + REG_PDEN) & BIT(offset)); in eqbr_pinconf_get()
431 val = !!(readl(mem + REG_OD) & BIT(offset)); in eqbr_pinconf_get()
434 val = get_drv_cur(mem, offset); in eqbr_pinconf_get()
437 val = !!(readl(mem + REG_SRC) & BIT(offset)); in eqbr_pinconf_get()
442 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n", in eqbr_pinconf_get()
443 bank->pin_base, pin); in eqbr_pinconf_get()
444 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_get()
445 return -ENODEV; in eqbr_pinconf_get()
447 val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset)); in eqbr_pinconf_get()
450 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_get()
451 return -ENOTSUPP; in eqbr_pinconf_get()
453 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_get()
466 unsigned int val, offset; in eqbr_pinconf_set() local
479 dev_err(pctl->dev, in eqbr_pinconf_set()
481 return -ENODEV; in eqbr_pinconf_set()
483 mem = bank->membase; in eqbr_pinconf_set()
484 offset = pin - bank->pin_base; in eqbr_pinconf_set()
489 mask = BIT(offset); in eqbr_pinconf_set()
493 mask = BIT(offset); in eqbr_pinconf_set()
497 mask = BIT(offset); in eqbr_pinconf_set()
500 mem += REG_DRCC(offset / DRV_CUR_PINS); in eqbr_pinconf_set()
501 offset = (offset % DRV_CUR_PINS) * 2; in eqbr_pinconf_set()
502 mask = GENMASK(1, 0) << offset; in eqbr_pinconf_set()
506 mask = BIT(offset); in eqbr_pinconf_set()
511 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n", in eqbr_pinconf_set()
512 bank->pin_base, pin); in eqbr_pinconf_set()
513 return -ENODEV; in eqbr_pinconf_set()
515 gc = &gctrl->chip.gc; in eqbr_pinconf_set()
516 gc->direction_output(gc, offset, 0); in eqbr_pinconf_set()
519 return -ENOTSUPP; in eqbr_pinconf_set()
522 raw_spin_lock_irqsave(&pctl->lock, flags); in eqbr_pinconf_set()
524 regval = (regval & ~mask) | ((val << offset) & mask); in eqbr_pinconf_set()
526 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_set()
545 return -ENOTSUPP; in eqbr_pinconf_group_get()
548 return -ENOTSUPP; in eqbr_pinconf_group_get()
605 struct device_node *node = dev->of_node; in funcs_utils()
621 (char *)prop->value); in funcs_utils()
647 groups[j] = prop->value; in funcs_utils()
652 return -EINVAL; in funcs_utils()
662 struct device *dev = drvdata->dev; in eqbr_build_functions()
673 return -ENOMEM; in eqbr_build_functions()
690 return -ENOMEM; in eqbr_build_functions()
703 ret = pinmux_generic_add_pinfunction(drvdata->pctl_dev, in eqbr_build_functions()
717 struct device *dev = drvdata->dev; in eqbr_build_groups()
718 struct device_node *node = dev->of_node; in eqbr_build_groups()
731 dev_err(dev, "No pins in the group: %s\n", prop->name); in eqbr_build_groups()
734 grp->npins = err; in eqbr_build_groups()
735 grp->name = prop->value; in eqbr_build_groups()
736 pins = devm_kcalloc(dev, grp->npins, sizeof(*pins), GFP_KERNEL); in eqbr_build_groups()
738 return -ENOMEM; in eqbr_build_groups()
740 grp->pins = pins; in eqbr_build_groups()
742 pinmux = devm_kcalloc(dev, grp->npins, sizeof(*pinmux), GFP_KERNEL); in eqbr_build_groups()
744 return -ENOMEM; in eqbr_build_groups()
746 for (j = 0; j < grp->npins; j++) { in eqbr_build_groups()
749 grp->name); in eqbr_build_groups()
750 return -EINVAL; in eqbr_build_groups()
752 if (pin_id >= drvdata->pctl_desc.npins) { in eqbr_build_groups()
754 grp->name, j, pin_id); in eqbr_build_groups()
755 return -EINVAL; in eqbr_build_groups()
760 grp->name); in eqbr_build_groups()
761 return -EINVAL; in eqbr_build_groups()
766 err = pinctrl_generic_add_group(drvdata->pctl_dev, in eqbr_build_groups()
767 grp->name, grp->pins, grp->npins, in eqbr_build_groups()
770 dev_err(dev, "Failed to register group %s\n", grp->name); in eqbr_build_groups()
789 dev = drvdata->dev; in pinctrl_reg()
790 pctl_desc = &drvdata->pctl_desc; in pinctrl_reg()
791 pctl_desc->name = "eqbr-pinctrl"; in pinctrl_reg()
792 pctl_desc->owner = THIS_MODULE; in pinctrl_reg()
793 pctl_desc->pctlops = &eqbr_pctl_ops; in pinctrl_reg()
794 pctl_desc->pmxops = &eqbr_pinmux_ops; in pinctrl_reg()
795 pctl_desc->confops = &eqbr_pinconf_ops; in pinctrl_reg()
796 raw_spin_lock_init(&drvdata->lock); in pinctrl_reg()
798 for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++) in pinctrl_reg()
799 nr_pins += drvdata->pin_banks[i].nr_pins; in pinctrl_reg()
803 return -ENOMEM; in pinctrl_reg()
806 return -ENOMEM; in pinctrl_reg()
814 pctl_desc->pins = pdesc; in pinctrl_reg()
815 pctl_desc->npins = nr_pins; in pinctrl_reg()
819 &drvdata->pctl_dev); in pinctrl_reg()
835 return pinctrl_enable(drvdata->pctl_dev); in pinctrl_reg()
842 struct device *dev = drvdata->dev; in pinbank_init()
846 bank->membase = drvdata->membase + id * PAD_REG_OFF; in pinbank_init()
848 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec); in pinbank_init()
850 dev_err(dev, "gpio-range not available!\n"); in pinbank_init()
854 bank->pin_base = spec.args[1]; in pinbank_init()
855 bank->nr_pins = spec.args[2]; in pinbank_init()
858 bank->aval_pinmap = readl(bank->membase + REG_AVAIL); in pinbank_init()
859 bank->id = id; in pinbank_init()
862 id, bank->membase, bank->pin_base, in pinbank_init()
863 bank->nr_pins, bank->aval_pinmap); in pinbank_init()
870 struct device *dev = drvdata->dev; in pinbank_probe()
885 return -ENODEV; in pinbank_probe()
891 return -ENOMEM; in pinbank_probe()
895 return -ENOMEM; in pinbank_probe()
912 drvdata->pin_banks = banks; in pinbank_probe()
913 drvdata->nr_banks = nr_gpio; in pinbank_probe()
914 drvdata->gpio_ctrls = gctrls; in pinbank_probe()
915 drvdata->nr_gpio_ctrls = nr_gpio; in pinbank_probe()
923 struct device *dev = &pdev->dev; in eqbr_pinctrl_probe()
928 return -ENOMEM; in eqbr_pinctrl_probe()
930 drvdata->dev = dev; in eqbr_pinctrl_probe()
932 drvdata->membase = devm_platform_ioremap_resource(pdev, 0); in eqbr_pinctrl_probe()
933 if (IS_ERR(drvdata->membase)) in eqbr_pinctrl_probe()
934 return PTR_ERR(drvdata->membase); in eqbr_pinctrl_probe()
953 { .compatible = "intel,lgm-io" },
961 .name = "eqbr-pinctrl",