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/linux/drivers/tty/serial/8250/
H A D8250_uniphier.c1 // SPDX-License-Identifier: GPL-2.0+
16 * This hardware is similar to 8250, but its register map is a bit different:
17 * - MMIO32 (regshift = 2)
18 * - FCR is not at 2, but 3
19 * - LCR and MCR are not at 3 and 4, they share 4
20 * - No SCR (Instead, CHAR can be used as a scratch register)
21 * - Divisor latch at 9, no divisor latch access bit
26 /* bit[15:8] = CHAR, bit[7:0] = FCR */
28 /* bit[15:8] = LCR, bit[7:0] = MCR */
30 /* Divisor Latch Register */
[all …]
/linux/arch/sh/include/asm/
H A Dsmc37c93x.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * linux/include/asm-sh/smc37c93x.h
67 #define UART_DLL 0x0 /* Divisor Latch (LS) */
68 #define UART_DLM 0x2 /* Divisor Latch (MS) */
88 /* Alias for Divisor Latch Register */
104 #define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
105 #define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
106 #define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
120 #define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
121 #define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
[all …]
/linux/Documentation/w1/slaves/
H A Dw1_ds2413.rst7 * Maxim DS2413 1-Wire Dual Channel Addressable Switch
18 -----------
20 The DS2413 chip has two open-drain outputs (PIO A and PIO B).
24 -------------
25 The "state" file provides one-byte value which is in the same format as for
29 Bit 0: PIOA Pin State
30 Bit 1: PIOA Output Latch State
31 Bit 2: PIOB Pin State
32 Bit 3: PIOB Output Latch State
33 Bit 4-7: Complement of Bit 3 to Bit 0 (verified by the kernel module)
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/linux/include/linux/ulpi/
H A Dregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
51 #define ULPI_FUNC_CTRL_XCVRSEL BIT(0)
57 #define ULPI_FUNC_CTRL_TERMSELECT BIT(2)
58 #define ULPI_FUNC_CTRL_OPMODE BIT(3)
64 #define ULPI_FUNC_CTRL_RESET BIT(5)
65 #define ULPI_FUNC_CTRL_SUSPENDM BIT(6)
68 #define ULPI_IFC_CTRL_6_PIN_SERIAL_MODE BIT(0)
69 #define ULPI_IFC_CTRL_3_PIN_SERIAL_MODE BIT(1)
70 #define ULPI_IFC_CTRL_CARKITMODE BIT(2)
71 #define ULPI_IFC_CTRL_CLOCKSUSPENDM BIT(3)
[all …]
/linux/Documentation/hwmon/
H A Dadm9240.rst10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
[all …]
/linux/drivers/mtd/nand/raw/
H A Dxway_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
18 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */
19 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
28 * correct line. For example when the bit (1 << 2) is set in the address
31 #define NAND_CMD_ALE BIT(2) /* address latch enable */
32 #define NAND_CMD_CLE BIT(3) /* command latch enable */
33 #define NAND_CMD_CS BIT(4) /* chip select */
34 #define NAND_CMD_SE BIT(5) /* spare area access latch */
35 #define NAND_CMD_WP BIT(6) /* write protect */
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/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,mux-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock assumes a register-mapped multiplexer with multiple inpt clock
31 "index-starts-at-one" modified the scheme as follows:
46 - ti,mux-clock
47 - ti,composite-mux-clock
49 "#clock-cells":
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H A Dti,divider-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock It assumes a register-mapped adjustable clock rate divider
25 ti,index-starts-at-one - valid divisor values start at 1, not the default
32 ti,index-power-of-two - valid divisor values are powers of two. E.g:
49 Any zero value in this array means the corresponding bit-value is invalid
65 - ti,divider-clock
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/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
42 - flags: reserved for future use, currently 0
43 - base field encodes bits [51:16] of the guest physical base address
[all …]
/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
57 controlled by port 61h, bit 0, as illustrated in the following diagram::
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
[all …]
/linux/drivers/clk/ti/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-kristo@ti.com>
12 #include <linux/clk-provider.h>
45 struct clk_iomap *io = clk_memmaps[reg->index]; in clk_memmap_writel()
47 if (reg->ptr) in clk_memmap_writel()
48 writel_relaxed(val, reg->ptr); in clk_memmap_writel()
49 else if (io->regma in clk_memmap_writel()
387 u32 latch; ti_clk_latch() local
[all...]
H A Dclock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Tero Kristo (t-kristo@ti.com)
16 s8 latch; member
32 s8 latch; member
76 #define CLKF_SW_SUP BIT(5)
77 #define CLKF_HW_SUP BIT(6)
78 #define CLKF_NO_IDLEST BIT(7)
82 #define CLKF_SOC_NONSEC BIT(8)
83 #define CLKF_SOC_DRA72 BIT(9)
84 #define CLKF_SOC_DRA74 BIT(10)
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H A Ddivider.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
27 if (clkt->val == val) in _get_table_div()
28 return clkt->div; in _get_table_div()
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
42 if (clkt->val > max_val) in _setup_mask()
43 max_val = clkt->val; in _setup_mask()
[all …]
/linux/drivers/usb/serial/
H A Dio_16654.h1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
23 // to them via LCR bit 0x80 or LCR = 0xBF.
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
40 #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB
41 #define DLM 9 // Bank2[ 1 ] Divisor Latch MSB
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
[all …]
/linux/drivers/clocksource/
H A Dtimer-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on arch/arm/mach-ixp4xx/common.c
8 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
34 * Timer register values and bit definitions
48 u32 latch; member
69 return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET); in ixp4xx_read_timer()
85 struct clock_event_device *evt = &tmr->clkevt; in ixp4xx_timer_interrupt()
89 tmr->base + IXP4XX_OSST_OFFSET); in ixp4xx_timer_interrupt()
91 evt->event_handler(evt); in ixp4xx_timer_interrupt()
102 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_set_next_event()
[all …]
/linux/kernel/time/
H A Dclockevents.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de>
6 * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar
7 * Copyright(C) 2006-2007, Timesys Corp., Thomas Gleixner
17 #include "tick-internal.h"
32 static u64 cev_delta2ns(unsigned long latch, struct clock_event_device *evt, in cev_delta2ns() argument
35 u64 clc = (u64) latch << evt->shift; in cev_delta2ns()
38 if (WARN_ON(!evt->mult)) in cev_delta2ns()
39 evt->mult = 1; in cev_delta2ns()
40 rnd = (u64) evt->mult - 1; in cev_delta2ns()
[all …]
/linux/drivers/rtc/
H A Drtc-msc313.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #define SOFT_RSTZ_BIT BIT(0)
33 #define CNT_EN_BIT BIT(1)
34 #define WRAP_EN_BIT BIT(2)
35 #define LOAD_EN_BIT BIT(3)
36 #define READ_EN_BIT BIT(4)
37 #define INT_MASK_BIT BIT(5)
38 #define INT_FORCE_BIT BIT(6)
39 #define INT_CLEAR_BIT BIT(7)
42 #define RAW_INT_BIT BIT(0)
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra76x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
12 target-module@42c01900 {
13 compatible = "ti,sysc-dra7-mcan", "ti,sysc";
15 #address-cells = <1>;
16 #size-cells = <1>;
20 reg-names = "rev", "sysc", "syss";
21 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
23 ti,syss-mask = <1>;
25 clock-names = "fck";
[all …]
/linux/drivers/comedi/drivers/
H A Ds626.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
24 * Number of extended-capability
36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
73 /* Interrupt enable bit in ISR and IER. */
180 * Shut down all MC1-controlled
231 #define S626_P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */
232 #define S626_P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */
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/linux/drivers/iio/adc/
H A Denvelope-detector.c1 // SPDX-License-Identifier: GPL-2.0
16 * input +------>-------|+ \
18 * .-------. | }---.
20 * | dac|-->--|- / |
24 * | irq|------<-------'
26 * '-------'
71 * interrupt service routine below (envelope_detector_comp_isr) as a latch
72 * (one-bit memory) for if the interrupt has triggered since last calling
75 * need to service a possible interrupt flood from the comparator when no-one
83 spin_lock_irq(&env->comp_lock); in envelope_detector_comp_latch()
[all …]
/linux/arch/mips/sibyte/swarm/
H A Drtc_xicor1241.c1 // SPDX-License-Identifier: GPL-2.0-or-later
28 #define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */
29 #define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */
78 /* Clear error bit by writing a 1 */ in xicor_read()
80 return -1; in xicor_read()
100 /* Clear error bit by writing a 1 */ in xicor_write()
102 return -1; in xicor_write()
154 tm.tm_hour -= 12; in xicor_set_time()
205 return xicor_read(X1241REG_SC) != -1; in xicor_probe()
/linux/drivers/iio/imu/bmi323/
H A Dbmi323_core.c1 // SPDX-License-Identifier: GPL-2.0
3 * IIO core driver for Bosch BMI323 6-Axis IMU.
7 …* Datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmi323-…
83 * The accelerometer supports +-2G/4G/8G/16G ranges, and the resolution of
85 * At +-8G the scale can calculated by
86 * ((8 + 8) * 9.80665 / (2^16 - 1)) * 10^6 = 2394.23819 scale in micro
188 return &data->orientation; in bmi323_get_mount_matrix()
199 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
200 BIT(IIO_EV_INFO_VALUE),
207 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
[all …]
/linux/drivers/media/i2c/
H A Dvpx3220.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-ctrls.h>
25 MODULE_PARM_DESC(debug, "Debug level (0-1)");
30 /* ----------------------------------------------------------------------- */
49 return &container_of(ctrl->handler, struct vpx3220, hdl)->sd; in to_sd()
54 /* ----------------------------------------------------------------------- */
61 decoder->reg[reg] = value; in vpx3220_write()
89 return -1; in vpx3220_fp_status()
96 /* Write the 16-bit address to the FPWR register */ in vpx3220_fp_write()
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/linux/drivers/platform/surface/
H A Dsurface_dtx.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Provides a user-space interface to properly handle clipboard/tablet
9 * use), or request detachment via user-space.
11 * Copyright (C) 2019-2022 Maximilian Luz <luzmaximilian@gmail.com>
34 /* -- SSAM interface. ------------------------------------------------------- */
136 /* -- Main structures. ------------------------------------------------------ */
139 SDTX_DEVICE_SHUTDOWN_BIT = BIT(0),
140 SDTX_DEVICE_DIRTY_BASE_BIT = BIT(1),
141 SDTX_DEVICE_DIRTY_MODE_BIT = BIT(2),
142 SDTX_DEVICE_DIRTY_LATCH_BIT = BIT(3),
[all …]
/linux/drivers/pcmcia/
H A Dtcic.c3 Device driver for Databook TCIC-2 PCMCIA controller
55 MODULE_DESCRIPTION("Databook TCIC-2 PCMCIA socket driver");
62 /* The base port address of the TCIC-2 chip */
66 static int ignore = -1;
71 /* Bit map of interrupts to choose from */
76 /* The card status change interrupt -- 0 means autoselect */
79 /* Poll status interval -- 0 means default to interrupt */
82 /* Delay for card status double-checking */
195 return 2*(ns-14)/cycle_time; in to_cycles()
214 return -1; in try_irq()
[all …]

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